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DAGCombine_trunc_extract.ll
DAGCombiner_illegal_BUILD_VECTOR.ll
DAGCombiner_isAlias.ll
RAbasic-invalid-LR-update.mir
addr-01.ll
addr-02.ll
addr-03.ll
alias-01.ll
alloca-01.ll
alloca-02.ll
alloca-03.ll
alloca-04.ll
and-01.ll
and-02.ll
and-03.ll
and-04.ll
and-05.ll
and-06.ll
and-07.ll
and-08.ll
and-xor-01.ll
args-01.ll
args-02.ll
args-03.ll
args-04.ll
args-05.ll
args-06.ll
args-07.ll
args-08.ll
args-09.ll
args-10.ll
asm-01.ll
asm-02.ll
asm-03.ll
asm-04.ll
asm-05.ll
asm-06.ll
asm-07.ll
asm-08.ll
asm-09.ll
asm-10.ll
asm-11.ll
asm-12.ll
asm-13.ll
asm-14.ll
asm-15.ll
asm-16.ll
asm-17.ll
asm-18.ll
atomic-fence-01.ll
atomic-fence-02.ll
atomic-load-01.ll
atomic-load-02.ll
atomic-load-03.ll
atomic-load-04.ll
atomic-load-05.ll
atomic-store-01.ll
atomic-store-02.ll
atomic-store-03.ll
atomic-store-04.ll
atomic-store-05.ll
atomicrmw-add-01.ll
atomicrmw-add-02.ll
atomicrmw-add-03.ll
atomicrmw-add-04.ll
atomicrmw-add-05.ll
atomicrmw-add-06.ll
atomicrmw-and-01.ll
atomicrmw-and-02.ll
atomicrmw-and-03.ll
atomicrmw-and-04.ll
atomicrmw-and-05.ll
atomicrmw-and-06.ll
atomicrmw-minmax-01.ll
atomicrmw-minmax-02.ll
atomicrmw-minmax-03.ll
atomicrmw-minmax-04.ll
atomicrmw-nand-01.ll
atomicrmw-nand-02.ll
atomicrmw-nand-03.ll
atomicrmw-nand-04.ll
atomicrmw-or-01.ll
atomicrmw-or-02.ll
atomicrmw-or-03.ll
atomicrmw-or-04.ll
atomicrmw-or-05.ll
atomicrmw-or-06.ll
atomicrmw-sub-01.ll
atomicrmw-sub-02.ll
atomicrmw-sub-03.ll
atomicrmw-sub-04.ll
atomicrmw-sub-05.ll
atomicrmw-sub-06.ll
atomicrmw-xchg-01.ll
atomicrmw-xchg-02.ll
atomicrmw-xchg-03.ll
atomicrmw-xchg-04.ll
atomicrmw-xor-01.ll
atomicrmw-xor-02.ll
atomicrmw-xor-03.ll
atomicrmw-xor-04.ll
atomicrmw-xor-05.ll
atomicrmw-xor-06.ll
backchain.ll
branch-01.ll
branch-02.ll
branch-03.ll
branch-04.ll
branch-05.ll
branch-06.ll
branch-07.ll
branch-08.ll
branch-09.ll
branch-10.ll
branch-11.ll
bswap-01.ll
bswap-02.ll
bswap-03.ll
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bswap-07.ll
bswap-08.ll
builtins.ll
call-01.ll
call-02.ll
call-03.ll
call-04.ll
call-05.ll
clear-liverange-spillreg.mir
cmpxchg-01.ll
cmpxchg-02.ll
cmpxchg-03.ll
cmpxchg-04.ll
cmpxchg-05.ll
cmpxchg-06.ll
cond-load-01.ll
cond-load-02.ll
cond-load-03.ll
cond-move-01.ll
cond-move-02.ll
cond-move-03.ll
cond-move-04.mir
cond-move-05.mir
cond-store-01.ll
cond-store-02.ll
cond-store-03.ll
cond-store-04.ll
cond-store-05.ll
cond-store-06.ll
cond-store-07.ll
cond-store-08.ll
cond-store-09.ll
copy-physreg-128.ll
ctpop-01.ll
dag-combine-01.ll
dag-combine-02.ll
dyn-alloca-offset.ll
expand-zext-pseudo.ll
extract-vector-elt-zEC12.ll
fold-memory-op-impl.ll
fp-abs-01.ll
fp-abs-02.ll
fp-abs-03.ll
fp-abs-04.ll
fp-add-01.ll
fp-add-02.ll
fp-add-03.ll
fp-add-04.ll
fp-cmp-01.ll
fp-cmp-02.ll
fp-cmp-03.ll
fp-cmp-04.ll
fp-cmp-05.ll
fp-cmp-06.ll
fp-cmp-07.mir
fp-const-01.ll
fp-const-02.ll
fp-const-03.ll
fp-const-04.ll
fp-const-05.ll
fp-const-06.ll
fp-const-07.ll
fp-const-08.ll
fp-const-09.ll
fp-const-10.ll
fp-const-11.ll
fp-conv-01.ll
fp-conv-02.ll
fp-conv-03.ll
fp-conv-04.ll
fp-conv-05.ll
fp-conv-06.ll
fp-conv-07.ll
fp-conv-08.ll
fp-conv-09.ll
fp-conv-10.ll
fp-conv-11.ll
fp-conv-12.ll
fp-conv-13.ll
fp-conv-14.ll
fp-conv-15.ll
fp-conv-16.ll
fp-conv-17.mir
fp-copysign-01.ll
fp-copysign-02.ll
fp-div-01.ll
fp-div-02.ll
fp-div-03.ll
fp-div-04.ll
fp-libcall.ll
fp-move-01.ll
fp-move-02.ll
fp-move-03.ll
fp-move-04.ll
fp-move-05.ll
fp-move-06.ll
fp-move-07.ll
fp-move-08.ll
fp-move-09.ll
fp-move-10.ll
fp-move-11.ll
fp-move-12.ll
fp-move-13.ll
fp-mul-01.ll
fp-mul-02.ll
fp-mul-03.ll
fp-mul-04.ll
fp-mul-05.ll
fp-mul-06.ll
fp-mul-07.ll
fp-mul-08.ll
fp-mul-09.ll
fp-mul-10.ll
fp-mul-11.ll
fp-mul-12.ll
fp-neg-01.ll
fp-neg-02.ll
fp-round-01.ll
fp-round-02.ll
fp-round-03.ll
fp-sincos-01.ll
fp-sqrt-01.ll
fp-sqrt-02.ll
fp-sqrt-03.ll
fp-sqrt-04.ll
fp-sub-01.ll
fp-sub-02.ll
fp-sub-03.ll
fp-sub-04.ll
fpc-intrinsics.ll
frame-01.ll
frame-02.ll
frame-03.ll
frame-04.ll
frame-05.ll
frame-06.ll
frame-07.ll
frame-08.ll
frame-09.ll
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frame-19.ll
frame-20.ll
frame-21.ll
frameaddr-01.ll
htm-intrinsics.ll
insert-01.ll
insert-02.ll
insert-03.ll
insert-04.ll
insert-05.ll
insert-06.ll
int-abs-01.ll
int-add-01.ll
int-add-02.ll
int-add-03.ll
int-add-04.ll
int-add-05.ll
int-add-06.ll
int-add-07.ll
int-add-08.ll
int-add-09.ll
int-add-10.ll
int-add-11.ll
int-add-12.ll
int-add-13.ll
int-add-14.ll
int-add-15.ll
int-add-16.ll
int-add-17.ll
int-cmp-01.ll
int-cmp-02.ll
int-cmp-03.ll
int-cmp-04.ll
int-cmp-05.ll
int-cmp-06.ll
int-cmp-07.ll
int-cmp-08.ll
int-cmp-09.ll
int-cmp-10.ll
int-cmp-11.ll
int-cmp-12.ll
int-cmp-13.ll
int-cmp-14.ll
int-cmp-15.ll
int-cmp-16.ll
int-cmp-17.ll
int-cmp-18.ll
int-cmp-19.ll
int-cmp-20.ll
int-cmp-21.ll
int-cmp-22.ll
int-cmp-23.ll
int-cmp-24.ll
int-cmp-25.ll
int-cmp-26.ll
int-cmp-27.ll
int-cmp-28.ll
int-cmp-29.ll
int-cmp-30.ll
int-cmp-31.ll
int-cmp-32.ll
int-cmp-33.ll
int-cmp-34.ll
int-cmp-35.ll
int-cmp-36.ll
int-cmp-37.ll
int-cmp-38.ll
int-cmp-39.ll
int-cmp-40.ll
int-cmp-41.ll
int-cmp-42.ll
int-cmp-43.ll
int-cmp-44.ll
int-cmp-45.ll
int-cmp-46.ll
int-cmp-47.ll
int-cmp-48.ll
int-cmp-49.ll
int-cmp-50.ll
int-cmp-51.ll
int-cmp-52.ll
int-cmp-53.ll
int-cmp-54.ll
int-const-01.ll
int-const-02.ll
int-const-03.ll
int-const-04.ll
int-const-05.ll
int-const-06.ll
int-conv-01.ll
int-conv-02.ll
int-conv-03.ll
int-conv-04.ll
int-conv-05.ll
int-conv-06.ll
int-conv-07.ll
int-conv-08.ll
int-conv-09.ll
int-conv-10.ll
int-conv-11.ll
int-conv-12.ll
int-conv-13.ll
int-div-01.ll
int-div-02.ll
int-div-03.ll
int-div-04.ll
int-div-05.ll
int-div-06.ll
int-move-01.ll
int-move-02.ll
int-move-03.ll
int-move-04.ll
int-move-05.ll
int-move-06.ll
int-move-07.ll
int-move-08.ll
int-move-09.ll
int-mul-01.ll
int-mul-02.ll
int-mul-03.ll
int-mul-04.ll
int-mul-05.ll
int-mul-06.ll
int-mul-07.ll
int-mul-08.ll
int-mul-09.ll
int-mul-10.ll
int-mul-11.ll
int-neg-01.ll
int-neg-02.ll
int-sub-01.ll
int-sub-02.ll
int-sub-03.ll
int-sub-04.ll
int-sub-05.ll
int-sub-06.ll
int-sub-07.ll
int-sub-08.ll
int-sub-09.ll
int-sub-10.ll
la-01.ll
la-02.ll
la-03.ll
la-04.ll
list-ilp-crash.ll
lit.local.cfg
locr-legal-regclass.ll
loop-01.ll
loop-02.ll
loop-03.ll
lower-copy-undef-src.mir
mature-mc-support.ll
memchr-01.ll
memchr-nobuiltin.ll
memcmp-01.ll
memcmp-nobuiltin.ll
memcpy-01.ll
memcpy-02.ll
memset-01.ll
memset-02.ll
memset-03.ll
memset-04.ll
or-01.ll
or-02.ll
or-03.ll
or-04.ll
or-05.ll
or-06.ll
or-07.ll
or-08.ll
pie.ll
pr31710.ll
pr32372.ll
pr32505.ll
prefetch-01.ll
regalloc-GR128.ll
regalloc-fast-invalid-kill-flag.mir
ret-addr-01.ll
risbg-01.ll
risbg-02.ll
risbg-03.ll
risbg-04.ll
rnsbg-01.ll
rosbg-01.ll
rosbg-02.ll
rot-01.ll
rot-02.ll
rxsbg-01.ll
selectcc-01.ll
selectcc-02.ll
selectcc-03.ll
setcc-01.ll
setcc-02.ll
shift-01.ll
shift-02.ll
shift-03.ll
shift-04.ll
shift-05.ll
shift-06.ll
shift-07.ll
shift-08.ll
shift-09.ll
shift-10.ll
shift-11.ll
shift-12.ll
spill-01.ll
splitMove_undefReg_mverifier.ll
splitMove_undefReg_mverifier_2.ll
stack-guard.ll
strcmp-01.ll
strcmp-nobuiltin.ll
strcpy-01.ll
strcpy-nobuiltin.ll
strlen-01.ll
strlen-nobuiltin.ll
swift-return.ll
swifterror.ll
swiftself.ll
tail-call-mem-intrinsics.ll
tdc-01.ll
tdc-02.ll
tdc-03.ll
tdc-04.ll
tdc-05.ll
tdc-06.ll
tdc-07.ll
tls-01.ll
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tls-07.ll
trap-01.ll
trap-02.ll
trap-03.ll
trap-04.ll
trap-05.ll
twoaddr-sink.ll
unaligned-01.ll
undef-flag.ll
vec-abi-align.ll
vec-abs-01.ll
vec-abs-02.ll
vec-abs-03.ll
vec-abs-04.ll
vec-abs-05.ll
vec-abs-06.ll
vec-add-01.ll
vec-add-02.ll
vec-and-01.ll
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vec-args-error-07.ll
vec-args-error-08.ll
vec-cmp-01.ll
vec-cmp-02.ll
vec-cmp-03.ll
vec-cmp-04.ll
vec-cmp-05.ll
vec-cmp-06.ll
vec-cmp-07.ll
vec-cmp-cmp-logic-select.ll
vec-cmpsel.ll
vec-combine-01.ll
vec-combine-02.ll
vec-const-01.ll
vec-const-02.ll
vec-const-03.ll
vec-const-04.ll
vec-const-05.ll
vec-const-06.ll
vec-const-07.ll
vec-const-08.ll
vec-const-09.ll
vec-const-10.ll
vec-const-11.ll
vec-const-12.ll
vec-const-13.ll
vec-const-14.ll
vec-const-15.ll
vec-const-16.ll
vec-const-17.ll
vec-const-18.ll
vec-conv-01.ll
vec-conv-02.ll
vec-ctlz-01.ll
vec-ctpop-01.ll
vec-ctpop-02.ll
vec-cttz-01.ll
vec-div-01.ll
vec-div-02.ll
vec-extract-01.ll
vec-extract-02.ll
vec-intrinsics-01.ll.REMOVED.git-id
vec-intrinsics-02.ll
vec-log-01.ll
vec-max-01.ll
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vec-move-03.ll
vec-move-04.ll
vec-move-05.ll
vec-move-06.ll
vec-move-07.ll
vec-move-08.ll
vec-move-09.ll
vec-move-10.ll
vec-move-11.ll
vec-move-12.ll
vec-move-13.ll
vec-move-14.ll
vec-move-15.ll
vec-move-16.ll
vec-move-17.ll
vec-move-18.ll
vec-mul-01.ll
vec-mul-02.ll
vec-mul-03.ll
vec-mul-04.ll
vec-mul-05.ll
vec-neg-01.ll
vec-neg-02.ll
vec-or-01.ll
vec-or-02.ll
vec-or-03.ll
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vec-round-01.ll
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vec-sext.ll
vec-shift-01.ll
vec-shift-02.ll
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vec-shift-04.ll
vec-shift-05.ll
vec-shift-06.ll
vec-shift-07.ll
vec-sqrt-01.ll
vec-sqrt-02.ll
vec-sub-01.ll
vec-sub-02.ll
vec-trunc-to-i1.ll
vec-xor-01.ll
vec-xor-02.ll
vec-zext.ll
vectorizer-output-3xi32.ll
xor-01.ll
xor-02.ll
xor-03.ll
xor-04.ll
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xor-06.ll
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150 lines
3.5 KiB
LLVM
150 lines
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LLVM
![]() |
; Test 32-bit shifts left.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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; Check the low end of the SLLG range.
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define i64 @f1(i64 %a) {
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; CHECK-LABEL: f1:
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; CHECK: sllg %r2, %r2, 1
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; CHECK: br %r14
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%shift = shl i64 %a, 1
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ret i64 %shift
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}
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|
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; Check the high end of the defined SLLG range.
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define i64 @f2(i64 %a) {
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; CHECK-LABEL: f2:
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; CHECK: sllg %r2, %r2, 63
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; CHECK: br %r14
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%shift = shl i64 %a, 63
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ret i64 %shift
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}
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; We don't generate shifts by out-of-range values.
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define i64 @f3(i64 %a) {
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; CHECK-LABEL: f3:
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; CHECK-NOT: sllg
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; CHECK: br %r14
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%shift = shl i64 %a, 64
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ret i64 %shift
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}
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; Check variable shifts.
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define i64 @f4(i64 %a, i64 %amt) {
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; CHECK-LABEL: f4:
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; CHECK: sllg %r2, %r2, 0(%r3)
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; CHECK: br %r14
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%shift = shl i64 %a, %amt
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ret i64 %shift
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}
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; Check shift amounts that have a constant term.
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define i64 @f5(i64 %a, i64 %amt) {
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; CHECK-LABEL: f5:
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; CHECK: sllg %r2, %r2, 10(%r3)
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; CHECK: br %r14
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%add = add i64 %amt, 10
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%shift = shl i64 %a, %add
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ret i64 %shift
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}
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; ...and again with a sign-extended 32-bit shift amount.
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define i64 @f6(i64 %a, i32 %amt) {
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; CHECK-LABEL: f6:
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; CHECK: sllg %r2, %r2, 10(%r3)
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; CHECK: br %r14
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%add = add i32 %amt, 10
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%addext = sext i32 %add to i64
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%shift = shl i64 %a, %addext
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ret i64 %shift
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}
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; ...and now with a zero-extended 32-bit shift amount.
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define i64 @f7(i64 %a, i32 %amt) {
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; CHECK-LABEL: f7:
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; CHECK: sllg %r2, %r2, 10(%r3)
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; CHECK: br %r14
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%add = add i32 %amt, 10
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%addext = zext i32 %add to i64
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%shift = shl i64 %a, %addext
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ret i64 %shift
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}
|
||
|
|
||
|
; Check shift amounts that have the largest in-range constant term. We could
|
||
|
; mask the amount instead.
|
||
|
define i64 @f8(i64 %a, i64 %amt) {
|
||
|
; CHECK-LABEL: f8:
|
||
|
; CHECK: sllg %r2, %r2, 524287(%r3)
|
||
|
; CHECK: br %r14
|
||
|
%add = add i64 %amt, 524287
|
||
|
%shift = shl i64 %a, %add
|
||
|
ret i64 %shift
|
||
|
}
|
||
|
|
||
|
; Check the next value up, which without masking must use a separate
|
||
|
; addition.
|
||
|
define i64 @f9(i64 %a, i64 %amt) {
|
||
|
; CHECK-LABEL: f9:
|
||
|
; CHECK: a{{g?}}fi %r3, 524288
|
||
|
; CHECK: sllg %r2, %r2, 0(%r3)
|
||
|
; CHECK: br %r14
|
||
|
%add = add i64 %amt, 524288
|
||
|
%shift = shl i64 %a, %add
|
||
|
ret i64 %shift
|
||
|
}
|
||
|
|
||
|
; Check cases where 1 is subtracted from the shift amount.
|
||
|
define i64 @f10(i64 %a, i64 %amt) {
|
||
|
; CHECK-LABEL: f10:
|
||
|
; CHECK: sllg %r2, %r2, -1(%r3)
|
||
|
; CHECK: br %r14
|
||
|
%sub = sub i64 %amt, 1
|
||
|
%shift = shl i64 %a, %sub
|
||
|
ret i64 %shift
|
||
|
}
|
||
|
|
||
|
; Check the lowest value that can be subtracted from the shift amount.
|
||
|
; Again, we could mask the shift amount instead.
|
||
|
define i64 @f11(i64 %a, i64 %amt) {
|
||
|
; CHECK-LABEL: f11:
|
||
|
; CHECK: sllg %r2, %r2, -524288(%r3)
|
||
|
; CHECK: br %r14
|
||
|
%sub = sub i64 %amt, 524288
|
||
|
%shift = shl i64 %a, %sub
|
||
|
ret i64 %shift
|
||
|
}
|
||
|
|
||
|
; Check the next value down, which without masking must use a separate
|
||
|
; addition.
|
||
|
define i64 @f12(i64 %a, i64 %amt) {
|
||
|
; CHECK-LABEL: f12:
|
||
|
; CHECK: a{{g?}}fi %r3, -524289
|
||
|
; CHECK: sllg %r2, %r2, 0(%r3)
|
||
|
; CHECK: br %r14
|
||
|
%sub = sub i64 %amt, 524289
|
||
|
%shift = shl i64 %a, %sub
|
||
|
ret i64 %shift
|
||
|
}
|
||
|
|
||
|
; Check that we don't try to generate "indexed" shifts.
|
||
|
define i64 @f13(i64 %a, i64 %b, i64 %c) {
|
||
|
; CHECK-LABEL: f13:
|
||
|
; CHECK: a{{g?}}r {{%r3, %r4|%r4, %r3}}
|
||
|
; CHECK: sllg %r2, %r2, 0({{%r[34]}})
|
||
|
; CHECK: br %r14
|
||
|
%add = add i64 %b, %c
|
||
|
%shift = shl i64 %a, %add
|
||
|
ret i64 %shift
|
||
|
}
|
||
|
|
||
|
; Check that the shift amount uses an address register. It cannot be in %r0.
|
||
|
define i64 @f14(i64 %a, i64 *%ptr) {
|
||
|
; CHECK-LABEL: f14:
|
||
|
; CHECK: l %r1, 4(%r3)
|
||
|
; CHECK: sllg %r2, %r2, 0(%r1)
|
||
|
; CHECK: br %r14
|
||
|
%amt = load i64 , i64 *%ptr
|
||
|
%shift = shl i64 %a, %amt
|
||
|
ret i64 %shift
|
||
|
}
|