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			TableGen
		
	
	
	
	
	
		
		
			
		
	
	
			79 lines
		
	
	
		
			2.8 KiB
		
	
	
	
		
			TableGen
		
	
	
	
	
	
|   | //===-- SystemZ.td - Describe the SystemZ target machine -----*- tblgen -*-===//
 | ||
|  | //
 | ||
|  | //                     The LLVM Compiler Infrastructure
 | ||
|  | //
 | ||
|  | // This file is distributed under the University of Illinois Open Source
 | ||
|  | // License. See LICENSE.TXT for details.
 | ||
|  | //
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|  | //===----------------------------------------------------------------------===//
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|  | 
 | ||
|  | //===----------------------------------------------------------------------===//
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|  | // Target-independent interfaces which we are implementing
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|  | //===----------------------------------------------------------------------===//
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|  | 
 | ||
|  | include "llvm/Target/Target.td" | ||
|  | 
 | ||
|  | //===----------------------------------------------------------------------===//
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|  | // SystemZ subtarget features
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|  | //===----------------------------------------------------------------------===//
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|  | 
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|  | include "SystemZFeatures.td" | ||
|  | 
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|  | //===----------------------------------------------------------------------===//
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|  | // SystemZ subtarget scheduling models
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|  | //===----------------------------------------------------------------------===//
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|  | 
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|  | include "SystemZSchedule.td" | ||
|  | 
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|  | //===----------------------------------------------------------------------===//
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|  | // SystemZ supported processors
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|  | //===----------------------------------------------------------------------===//
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|  | 
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|  | include "SystemZProcessors.td" | ||
|  | 
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|  | //===----------------------------------------------------------------------===//
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|  | // Register file description
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|  | //===----------------------------------------------------------------------===//
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|  | 
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|  | include "SystemZRegisterInfo.td" | ||
|  | 
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|  | //===----------------------------------------------------------------------===//
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|  | // Calling convention description
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|  | //===----------------------------------------------------------------------===//
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|  | 
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|  | include "SystemZCallingConv.td" | ||
|  | 
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|  | //===----------------------------------------------------------------------===//
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|  | // Instruction descriptions
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|  | //===----------------------------------------------------------------------===//
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|  | 
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|  | include "SystemZOperators.td" | ||
|  | include "SystemZOperands.td" | ||
|  | include "SystemZPatterns.td" | ||
|  | include "SystemZInstrFormats.td" | ||
|  | include "SystemZInstrInfo.td" | ||
|  | include "SystemZInstrVector.td" | ||
|  | include "SystemZInstrFP.td" | ||
|  | include "SystemZInstrHFP.td" | ||
|  | include "SystemZInstrDFP.td" | ||
|  | include "SystemZInstrSystem.td" | ||
|  | 
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|  | def SystemZInstrInfo : InstrInfo { let guessInstructionProperties = 0; } | ||
|  | 
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|  | //===----------------------------------------------------------------------===//
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|  | // Assembly parser
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|  | //===----------------------------------------------------------------------===//
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|  | 
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|  | def SystemZAsmParser : AsmParser { | ||
|  |   let ShouldEmitMatchRegisterName = 0; | ||
|  | } | ||
|  | 
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|  | //===----------------------------------------------------------------------===//
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|  | // Top-level target declaration
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|  | //===----------------------------------------------------------------------===//
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|  | 
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|  | def SystemZ : Target { | ||
|  |   let InstructionSet = SystemZInstrInfo; | ||
|  |   let AssemblyParsers = [SystemZAsmParser]; | ||
|  | } |