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			TableGen
		
	
	
	
	
	
		
		
			
		
	
	
			74 lines
		
	
	
		
			2.9 KiB
		
	
	
	
		
			TableGen
		
	
	
	
	
	
|   | //- WebAssembly.td - Describe the WebAssembly Target Machine --*- tablegen -*-//
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|  | //
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|  | //                     The LLVM Compiler Infrastructure
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|  | //
 | ||
|  | // This file is distributed under the University of Illinois Open Source
 | ||
|  | // License. See LICENSE.TXT for details.
 | ||
|  | //
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|  | //===----------------------------------------------------------------------===//
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|  | ///
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|  | /// \file
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|  | /// \brief This is a target description file for the WebAssembly architecture,
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|  | /// which is also known as "wasm".
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|  | ///
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|  | //===----------------------------------------------------------------------===//
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|  | 
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|  | //===----------------------------------------------------------------------===//
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|  | // Target-independent interfaces which we are implementing
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|  | //===----------------------------------------------------------------------===//
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|  | 
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|  | include "llvm/Target/Target.td" | ||
|  | 
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|  | //===----------------------------------------------------------------------===//
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|  | // WebAssembly Subtarget features.
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|  | //===----------------------------------------------------------------------===//
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|  | 
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|  | def FeatureSIMD128 : SubtargetFeature<"simd128", "HasSIMD128", "true", | ||
|  |                                       "Enable 128-bit SIMD">; | ||
|  | def FeatureAtomics : SubtargetFeature<"atomics", "HasAtomics", "true", | ||
|  |                                       "Enable Atomics">; | ||
|  | def FeatureNontrappingFPToInt : | ||
|  |       SubtargetFeature<"nontrapping-fptoint", | ||
|  |                        "HasNontrappingFPToInt", "true", | ||
|  |                        "Enable non-trapping float-to-int conversion operators">; | ||
|  | 
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|  | //===----------------------------------------------------------------------===//
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|  | // Architectures.
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|  | //===----------------------------------------------------------------------===//
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|  | 
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|  | //===----------------------------------------------------------------------===//
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|  | // Register File Description
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|  | //===----------------------------------------------------------------------===//
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|  | 
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|  | include "WebAssemblyRegisterInfo.td" | ||
|  | 
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|  | //===----------------------------------------------------------------------===//
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|  | // Instruction Descriptions
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|  | //===----------------------------------------------------------------------===//
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|  | 
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|  | include "WebAssemblyInstrInfo.td" | ||
|  | 
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|  | def WebAssemblyInstrInfo : InstrInfo; | ||
|  | 
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|  | //===----------------------------------------------------------------------===//
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|  | // WebAssembly Processors supported.
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|  | //===----------------------------------------------------------------------===//
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|  | 
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|  | // Minimal Viable Product.
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|  | def : ProcessorModel<"mvp", NoSchedModel, []>; | ||
|  | 
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|  | // Generic processor: latest stable version.
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|  | def : ProcessorModel<"generic", NoSchedModel, []>; | ||
|  | 
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|  | // Latest and greatest experimental version of WebAssembly. Bugs included!
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|  | def : ProcessorModel<"bleeding-edge", NoSchedModel, | ||
|  |                       [FeatureSIMD128, FeatureAtomics]>; | ||
|  | 
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|  | //===----------------------------------------------------------------------===//
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|  | // Target Declaration
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|  | //===----------------------------------------------------------------------===//
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|  | 
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|  | def WebAssembly : Target { | ||
|  |   let InstructionSet = WebAssemblyInstrInfo; | ||
|  | } |