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402 lines
13 KiB
C
402 lines
13 KiB
C
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//===--- Mips.h - Declare Mips target feature support -----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares Mips TargetInfo objects.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CLANG_LIB_BASIC_TARGETS_MIPS_H
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#define LLVM_CLANG_LIB_BASIC_TARGETS_MIPS_H
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#include "clang/Basic/TargetInfo.h"
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#include "clang/Basic/TargetOptions.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/Support/Compiler.h"
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namespace clang {
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namespace targets {
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class LLVM_LIBRARY_VISIBILITY MipsTargetInfo : public TargetInfo {
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void setDataLayout() {
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StringRef Layout;
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if (ABI == "o32")
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Layout = "m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
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else if (ABI == "n32")
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Layout = "m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
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else if (ABI == "n64")
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Layout = "m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128";
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else
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llvm_unreachable("Invalid ABI");
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if (BigEndian)
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resetDataLayout(("E-" + Layout).str());
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else
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resetDataLayout(("e-" + Layout).str());
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}
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static const Builtin::Info BuiltinInfo[];
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std::string CPU;
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bool IsMips16;
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bool IsMicromips;
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bool IsNan2008;
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bool IsAbs2008;
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bool IsSingleFloat;
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bool IsNoABICalls;
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bool CanUseBSDABICalls;
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enum MipsFloatABI { HardFloat, SoftFloat } FloatABI;
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enum DspRevEnum { NoDSP, DSP1, DSP2 } DspRev;
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bool HasMSA;
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bool DisableMadd4;
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bool UseIndirectJumpHazard;
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protected:
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bool HasFP64;
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std::string ABI;
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public:
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MipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
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: TargetInfo(Triple), IsMips16(false), IsMicromips(false),
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IsNan2008(false), IsAbs2008(false), IsSingleFloat(false),
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IsNoABICalls(false), CanUseBSDABICalls(false), FloatABI(HardFloat),
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DspRev(NoDSP), HasMSA(false), DisableMadd4(false),
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UseIndirectJumpHazard(false), HasFP64(false) {
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TheCXXABI.set(TargetCXXABI::GenericMIPS);
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setABI((getTriple().getArch() == llvm::Triple::mips ||
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getTriple().getArch() == llvm::Triple::mipsel)
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? "o32"
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: "n64");
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CPU = ABI == "o32" ? "mips32r2" : "mips64r2";
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CanUseBSDABICalls = Triple.getOS() == llvm::Triple::FreeBSD ||
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Triple.getOS() == llvm::Triple::OpenBSD;
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}
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bool isIEEE754_2008Default() const {
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return CPU == "mips32r6" || CPU == "mips64r6";
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}
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bool isFP64Default() const {
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return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64";
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}
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bool isNan2008() const override { return IsNan2008; }
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bool processorSupportsGPR64() const;
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StringRef getABI() const override { return ABI; }
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bool setABI(const std::string &Name) override {
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if (Name == "o32") {
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setO32ABITypes();
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ABI = Name;
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return true;
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}
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if (Name == "n32") {
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setN32ABITypes();
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ABI = Name;
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return true;
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}
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if (Name == "n64") {
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setN64ABITypes();
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ABI = Name;
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return true;
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}
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return false;
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}
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void setO32ABITypes() {
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Int64Type = SignedLongLong;
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IntMaxType = Int64Type;
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LongDoubleFormat = &llvm::APFloat::IEEEdouble();
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LongDoubleWidth = LongDoubleAlign = 64;
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LongWidth = LongAlign = 32;
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MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
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PointerWidth = PointerAlign = 32;
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PtrDiffType = SignedInt;
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SizeType = UnsignedInt;
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SuitableAlign = 64;
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}
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void setN32N64ABITypes() {
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LongDoubleWidth = LongDoubleAlign = 128;
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LongDoubleFormat = &llvm::APFloat::IEEEquad();
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if (getTriple().getOS() == llvm::Triple::FreeBSD) {
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LongDoubleWidth = LongDoubleAlign = 64;
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LongDoubleFormat = &llvm::APFloat::IEEEdouble();
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}
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MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
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SuitableAlign = 128;
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}
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void setN64ABITypes() {
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setN32N64ABITypes();
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if (getTriple().getOS() == llvm::Triple::OpenBSD) {
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Int64Type = SignedLongLong;
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} else {
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Int64Type = SignedLong;
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}
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IntMaxType = Int64Type;
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LongWidth = LongAlign = 64;
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PointerWidth = PointerAlign = 64;
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PtrDiffType = SignedLong;
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SizeType = UnsignedLong;
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}
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void setN32ABITypes() {
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setN32N64ABITypes();
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Int64Type = SignedLongLong;
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IntMaxType = Int64Type;
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LongWidth = LongAlign = 32;
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PointerWidth = PointerAlign = 32;
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PtrDiffType = SignedInt;
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SizeType = UnsignedInt;
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}
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bool isValidCPUName(StringRef Name) const override;
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bool setCPU(const std::string &Name) override {
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CPU = Name;
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return isValidCPUName(Name);
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}
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const std::string &getCPU() const { return CPU; }
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bool
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initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
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StringRef CPU,
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const std::vector<std::string> &FeaturesVec) const override {
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if (CPU.empty())
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CPU = getCPU();
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if (CPU == "octeon")
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Features["mips64r2"] = Features["cnmips"] = true;
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else
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Features[CPU] = true;
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return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
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}
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void getTargetDefines(const LangOptions &Opts,
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MacroBuilder &Builder) const override;
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ArrayRef<Builtin::Info> getTargetBuiltins() const override;
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bool hasFeature(StringRef Feature) const override;
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BuiltinVaListKind getBuiltinVaListKind() const override {
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return TargetInfo::VoidPtrBuiltinVaList;
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}
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ArrayRef<const char *> getGCCRegNames() const override {
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static const char *const GCCRegNames[] = {
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// CPU register names
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// Must match second column of GCCRegAliases
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"$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", "$8", "$9", "$10",
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"$11", "$12", "$13", "$14", "$15", "$16", "$17", "$18", "$19", "$20",
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"$21", "$22", "$23", "$24", "$25", "$26", "$27", "$28", "$29", "$30",
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"$31",
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// Floating point register names
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"$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", "$f8", "$f9",
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"$f10", "$f11", "$f12", "$f13", "$f14", "$f15", "$f16", "$f17", "$f18",
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"$f19", "$f20", "$f21", "$f22", "$f23", "$f24", "$f25", "$f26", "$f27",
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"$f28", "$f29", "$f30", "$f31",
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// Hi/lo and condition register names
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"hi", "lo", "", "$fcc0", "$fcc1", "$fcc2", "$fcc3", "$fcc4", "$fcc5",
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"$fcc6", "$fcc7", "$ac1hi", "$ac1lo", "$ac2hi", "$ac2lo", "$ac3hi",
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"$ac3lo",
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// MSA register names
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"$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", "$w8", "$w9",
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"$w10", "$w11", "$w12", "$w13", "$w14", "$w15", "$w16", "$w17", "$w18",
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"$w19", "$w20", "$w21", "$w22", "$w23", "$w24", "$w25", "$w26", "$w27",
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"$w28", "$w29", "$w30", "$w31",
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// MSA control register names
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"$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify",
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"$msarequest", "$msamap", "$msaunmap"
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};
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return llvm::makeArrayRef(GCCRegNames);
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}
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bool validateAsmConstraint(const char *&Name,
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TargetInfo::ConstraintInfo &Info) const override {
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switch (*Name) {
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default:
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return false;
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case 'r': // CPU registers.
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case 'd': // Equivalent to "r" unless generating MIPS16 code.
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case 'y': // Equivalent to "r", backward compatibility only.
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case 'f': // floating-point registers.
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case 'c': // $25 for indirect jumps
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case 'l': // lo register
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case 'x': // hilo register pair
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Info.setAllowsRegister();
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return true;
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case 'I': // Signed 16-bit constant
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case 'J': // Integer 0
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case 'K': // Unsigned 16-bit constant
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case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui)
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case 'M': // Constants not loadable via lui, addiu, or ori
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case 'N': // Constant -1 to -65535
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case 'O': // A signed 15-bit constant
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case 'P': // A constant between 1 go 65535
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return true;
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case 'R': // An address that can be used in a non-macro load or store
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Info.setAllowsMemory();
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return true;
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case 'Z':
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if (Name[1] == 'C') { // An address usable by ll, and sc.
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Info.setAllowsMemory();
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Name++; // Skip over 'Z'.
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return true;
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}
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return false;
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}
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}
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std::string convertConstraint(const char *&Constraint) const override {
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std::string R;
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switch (*Constraint) {
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case 'Z': // Two-character constraint; add "^" hint for later parsing.
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if (Constraint[1] == 'C') {
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R = std::string("^") + std::string(Constraint, 2);
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Constraint++;
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return R;
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}
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break;
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}
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return TargetInfo::convertConstraint(Constraint);
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}
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const char *getClobbers() const override {
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// In GCC, $1 is not widely used in generated code (it's used only in a few
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// specific situations), so there is no real need for users to add it to
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// the clobbers list if they want to use it in their inline assembly code.
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//
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// In LLVM, $1 is treated as a normal GPR and is always allocatable during
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// code generation, so using it in inline assembly without adding it to the
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// clobbers list can cause conflicts between the inline assembly code and
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// the surrounding generated code.
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//
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// Another problem is that LLVM is allowed to choose $1 for inline assembly
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// operands, which will conflict with the ".set at" assembler option (which
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// we use only for inline assembly, in order to maintain compatibility with
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// GCC) and will also conflict with the user's usage of $1.
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//
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// The easiest way to avoid these conflicts and keep $1 as an allocatable
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// register for generated code is to automatically clobber $1 for all inline
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// assembly code.
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//
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// FIXME: We should automatically clobber $1 only for inline assembly code
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// which actually uses it. This would allow LLVM to use $1 for inline
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// assembly operands if the user's assembly code doesn't use it.
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return "~{$1}";
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}
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bool handleTargetFeatures(std::vector<std::string> &Features,
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DiagnosticsEngine &Diags) override {
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IsMips16 = false;
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IsMicromips = false;
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IsNan2008 = isIEEE754_2008Default();
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IsAbs2008 = isIEEE754_2008Default();
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IsSingleFloat = false;
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FloatABI = HardFloat;
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DspRev = NoDSP;
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HasFP64 = isFP64Default();
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for (const auto &Feature : Features) {
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if (Feature == "+single-float")
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IsSingleFloat = true;
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else if (Feature == "+soft-float")
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FloatABI = SoftFloat;
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else if (Feature == "+mips16")
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IsMips16 = true;
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else if (Feature == "+micromips")
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IsMicromips = true;
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else if (Feature == "+dsp")
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DspRev = std::max(DspRev, DSP1);
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else if (Feature == "+dspr2")
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DspRev = std::max(DspRev, DSP2);
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else if (Feature == "+msa")
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HasMSA = true;
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else if (Feature == "+nomadd4")
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DisableMadd4 = true;
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else if (Feature == "+fp64")
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HasFP64 = true;
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else if (Feature == "-fp64")
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HasFP64 = false;
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else if (Feature == "+nan2008")
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IsNan2008 = true;
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else if (Feature == "-nan2008")
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IsNan2008 = false;
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else if (Feature == "+abs2008")
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IsAbs2008 = true;
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else if (Feature == "-abs2008")
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IsAbs2008 = false;
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else if (Feature == "+noabicalls")
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IsNoABICalls = true;
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else if (Feature == "+use-indirect-jump-hazard")
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UseIndirectJumpHazard = true;
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}
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setDataLayout();
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return true;
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}
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int getEHDataRegisterNumber(unsigned RegNo) const override {
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if (RegNo == 0)
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return 4;
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if (RegNo == 1)
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return 5;
|
||
|
|
return -1;
|
||
|
|
}
|
||
|
|
|
||
|
|
bool isCLZForZeroUndef() const override { return false; }
|
||
|
|
|
||
|
|
ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
|
||
|
|
static const TargetInfo::GCCRegAlias O32RegAliases[] = {
|
||
|
|
{{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"},
|
||
|
|
{{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"},
|
||
|
|
{{"a3"}, "$7"}, {{"t0"}, "$8"}, {{"t1"}, "$9"},
|
||
|
|
{{"t2"}, "$10"}, {{"t3"}, "$11"}, {{"t4"}, "$12"},
|
||
|
|
{{"t5"}, "$13"}, {{"t6"}, "$14"}, {{"t7"}, "$15"},
|
||
|
|
{{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"},
|
||
|
|
{{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"},
|
||
|
|
{{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"},
|
||
|
|
{{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"},
|
||
|
|
{{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"},
|
||
|
|
{{"ra"}, "$31"}
|
||
|
|
};
|
||
|
|
static const TargetInfo::GCCRegAlias NewABIRegAliases[] = {
|
||
|
|
{{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"},
|
||
|
|
{{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"},
|
||
|
|
{{"a3"}, "$7"}, {{"a4"}, "$8"}, {{"a5"}, "$9"},
|
||
|
|
{{"a6"}, "$10"}, {{"a7"}, "$11"}, {{"t0"}, "$12"},
|
||
|
|
{{"t1"}, "$13"}, {{"t2"}, "$14"}, {{"t3"}, "$15"},
|
||
|
|
{{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"},
|
||
|
|
{{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"},
|
||
|
|
{{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"},
|
||
|
|
{{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"},
|
||
|
|
{{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"},
|
||
|
|
{{"ra"}, "$31"}
|
||
|
|
};
|
||
|
|
if (ABI == "o32")
|
||
|
|
return llvm::makeArrayRef(O32RegAliases);
|
||
|
|
return llvm::makeArrayRef(NewABIRegAliases);
|
||
|
|
}
|
||
|
|
|
||
|
|
bool hasInt128Type() const override { return ABI == "n32" || ABI == "n64"; }
|
||
|
|
|
||
|
|
bool validateTarget(DiagnosticsEngine &Diags) const override;
|
||
|
|
};
|
||
|
|
} // namespace targets
|
||
|
|
} // namespace clang
|
||
|
|
|
||
|
|
#endif // LLVM_CLANG_LIB_BASIC_TARGETS_MIPS_H
|