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2004-11-29-ShrCrash.ll
2004-11-30-shift-crash.ll
2004-11-30-shr-var-crash.ll
2004-12-12-ZeroSizeCommon.ll
2005-01-14-SetSelectCrash.ll
2005-01-14-UndefLong.ll
2005-08-12-rlwimi-crash.ll
2005-09-02-LegalizeDuplicatesCalls.ll
2005-10-08-ArithmeticRotate.ll
2005-11-30-vastart-crash.ll
2006-01-11-darwin-fp-argument.ll
2006-01-20-ShiftPartsCrash.ll
2006-04-01-FloatDoubleExtend.ll
2006-04-05-splat-ish.ll
2006-04-19-vmaddfp-crash.ll
2006-05-12-rlwimi-crash.ll
2006-07-07-ComputeMaskedBits.ll
2006-07-19-stwbrx-crash.ll
2006-08-11-RetVector.ll
2006-08-15-SelectionCrash.ll
2006-09-28-shift_64.ll
2006-10-13-Miscompile.ll
2006-10-17-brcc-miscompile.ll
2006-10-17-ppc64-alloca.ll
2006-11-10-DAGCombineMiscompile.ll
2006-11-29-AltivecFPSplat.ll
2006-12-07-LargeAlloca.ll
2006-12-07-SelectCrash.ll
2007-01-04-ArgExtension.ll
2007-01-15-AsmDialect.ll
2007-01-29-lbrx-asm.ll
2007-01-31-InlineAsmAddrMode.ll
2007-02-16-AlignPacked.ll
2007-02-16-InlineAsmNConstraint.ll
2007-02-23-lr-saved-twice.ll
2007-03-24-cntlzd.ll
2007-03-30-SpillerCrash.ll.REMOVED.git-id
2007-04-24-InlineAsm-I-Modifier.ll
2007-04-30-InlineAsmEarlyClobber.ll
2007-05-03-InlineAsm-S-Constraint.ll
2007-05-14-InlineAsmSelectCrash.ll
2007-05-22-tailmerge-3.ll
2007-05-30-dagcombine-miscomp.ll
2007-06-28-BCCISelBug.ll
2007-08-04-CoalescerAssert.ll
2007-09-04-AltivecDST.ll
2007-09-07-LoadStoreIdxForms.ll
2007-09-08-unaligned.ll
2007-09-11-RegCoalescerAssert.ll
2007-09-12-LiveIntervalsAssert.ll
2007-10-16-InlineAsmFrameOffset.ll
2007-10-18-PtrArithmetic.ll
2007-10-21-LocalRegAllocAssert.ll
2007-10-21-LocalRegAllocAssert2.ll
2007-11-04-CoalescerCrash.ll
2007-11-16-landingpad-split.ll
2007-11-19-VectorSplitting.ll
2008-02-05-LiveIntervalsAssert.ll
2008-02-09-LocalRegAllocAssert.ll
2008-03-05-RegScavengerAssert.ll
2008-03-17-RegScavengerCrash.ll
2008-03-18-RegScavengerAssert.ll
2008-03-24-AddressRegImm.ll
2008-03-24-CoalescerBug.ll
2008-03-26-CoalescerBug.ll
2008-04-10-LiveIntervalCrash.ll
2008-04-16-CoalescerBug.ll
2008-04-23-CoalescerCrash.ll
2008-05-01-ppc_fp128.ll
2008-06-19-LegalizerCrash.ll
2008-06-21-F128LoadStore.ll
2008-06-23-LiveVariablesCrash.ll
2008-07-10-SplatMiscompile.ll
2008-07-15-Bswap.ll
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2008-07-15-SignExtendInreg.ll
2008-07-17-Fneg.ll
2008-07-24-PPC64-CCBug.ll
2008-09-12-CoalescerBug.ll
2008-10-17-AsmMatchingOperands.ll
2008-10-28-UnprocessedNode.ll
2008-10-28-f128-i32.ll
2008-10-31-PPCF128Libcalls.ll
2008-12-02-LegalizeTypeAssert.ll
2009-01-16-DeclareISelBug.ll
2009-03-17-LSRBug.ll
2009-05-28-LegalizeBRCC.ll
2009-07-16-InlineAsm-M-Operand.ll
2009-08-17-inline-asm-addr-mode-breakage.ll
2009-09-18-carrybit.ll
2009-11-15-ProcImpDefsBug.ll
2009-11-25-ImpDefBug.ll
2010-02-04-EmptyGlobal.ll
2010-02-12-saveCR.ll
2010-03-09-indirect-call.ll
2010-04-01-MachineCSEBug.ll
2010-05-03-retaddr1.ll
2010-10-11-Fast-Varargs.ll
2010-12-18-PPCStackRefs.ll
2011-12-05-NoSpillDupCR.ll
2011-12-06-SpillAndRestoreCR.ll
2011-12-08-DemandedBitsMiscompile.ll
2012-09-16-TOC-entry-check.ll
2012-10-11-dynalloc.ll
2012-10-12-bitcast.ll
2012-11-16-mischedcall.ll
2013-05-15-preinc-fold.ll
2013-07-01-PHIElimBug.ll
2016-01-07-BranchWeightCrash.ll
2016-04-16-ADD8TLS.ll
2016-04-17-combine.ll
2016-04-28-setjmp.ll
Atomics-64.ll
BoolRetToIntTest-2.ll
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CompareEliminationSpillIssue.ll
DbgValueOtherTargets.test
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ctrloop-s000.ll
ctrloop-sh.ll
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ctrloops.ll
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dyn-alloca-aligned.ll
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e500-1.ll
early-ret.ll
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ec-input.ll
eh-dwarf-cfa.ll
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emptystruct.ll
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expand-isel-10.mir
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expand-isel-4.mir
expand-isel-5.mir
expand-isel-6.mir
expand-isel-7.mir
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expand-isel-9.mir
expand-isel.ll
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f32-to-i64.ll
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fcpsgn.ll
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floatPSA.ll
flt-preinc.ll
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fp-to-int-ext.ll
fp-to-int-to-fp.ll
fp128-bitcast-after-operation.ll
fp2int2fp-ppcfp128.ll
fp64-to-int16.ll
fp_to_uint.ll
fpcopy.ll
frame-size.ll
frameaddr.ll
frounds.ll
fsel.ll
fsl-e500mc.ll
fsl-e5500.ll
fsqrt.ll
func-addr-consts.ll
func-addr.ll
glob-comp-aa-crash.ll
gpr-vsr-spill.ll
hello-reloc.s
hello.ll
hidden-vis-2.ll
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htm.ll
i1-ext-fold.ll
i1-to-double.ll
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i32-to-float.ll
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i64_fp.ll
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ia-neg-const.ll
iabs.ll
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indexed-load.ll
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indirectbr.ll
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inlineasm-copy.ll
inlineasm-i64-reg.ll
int-fp-conv-0.ll
int-fp-conv-1.ll
inverted-bool-compares.ll
isel-rc-nox0.ll
isel.ll
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itofp128.ll
jaggedstructs.ll
lbz-from-ld-shift.ll
lbzux.ll
ld-st-upd.ll
ldtoc-inv.ll
lha.ll
licm-remat.ll
licm-tocReg.ll
lit.local.cfg
livephysregs.mir
load-constant-addr.ll
load-shift-combine.ll
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logic-ops-on-compares.ll
long-compare.ll
longcall.ll
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ppc32-lshrti3.ll
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pr12757.ll
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scavenging.mir
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testComparesilesc.ll
testComparesilesi.ll
testComparesilesll.ll
testComparesiless.ll
testComparesileuc.ll
testComparesileui.ll
testComparesileull.ll
testComparesileus.ll
testComparesiltsc.ll
testComparesiltsi.ll
testComparesiltsll.ll
testComparesiltss.ll
testComparesiltuc.ll
testComparesiltui.ll
testComparesiltus.ll
testComparesinesc.ll
testComparesinesi.ll
testComparesinesll.ll
testComparesiness.ll
testComparesineuc.ll
testComparesineui.ll
testComparesineull.ll
testComparesineus.ll
testCompareslleqsc.ll
testCompareslleqsi.ll
testCompareslleqsll.ll
testCompareslleqss.ll
testComparesllequc.ll
testComparesllequi.ll
testComparesllequll.ll
testComparesllequs.ll
testComparesllgesc.ll
testComparesllgesi.ll
testComparesllgesll.ll
testComparesllgess.ll
testComparesllgeuc.ll
testComparesllgeui.ll
testComparesllgeull.ll
testComparesllgeus.ll
testComparesllgtsll.ll
testComparesllgtuc.ll
testComparesllgtui.ll
testComparesllgtus.ll
testCompareslllesc.ll
testCompareslllesi.ll
testCompareslllesll.ll
testComparesllless.ll
testComparesllleuc.ll
testComparesllleui.ll
testComparesllleull.ll
testComparesllleus.ll
testComparesllltsll.ll
testComparesllltuc.ll
testComparesllltui.ll
testComparesllltus.ll
testComparesllnesll.ll
testComparesllneull.ll
thread-pointer.ll
tls-cse.ll
tls-pic.ll
tls-store2.ll
tls.ll
tls_get_addr_clobbers.ll
tls_get_addr_fence1.mir
tls_get_addr_fence2.mir
tls_get_addr_stackframe.ll
toc-load-sched-bug.ll
trampoline.ll
uint-to-ppcfp128-crash.ll
unal-altivec-wint.ll
unal-altivec.ll
unal-altivec2.ll
unal-vec-ldst.ll
unal-vec-negarith.ll
unal4-std.ll
unaligned.ll
unsafe-math.ll
unwind-dw2-g.ll
unwind-dw2.ll
vaddsplat.ll
varargs-struct-float.ll
varargs.ll
variable_elem_vec_extracts.ll
vcmp-fold.ll
vec-abi-align.ll
vec-asm-disabled.ll
vec_abs.ll
vec_absd.ll
vec_add_sub_doubleword.ll
vec_add_sub_quadword.ll
vec_auto_constant.ll
vec_br_cmp.ll
vec_buildvector_loadstore.ll
vec_call.ll
vec_clz.ll
vec_cmp.ll
vec_cmpd.ll
vec_constants.ll
vec_conv.ll
vec_extload.ll
vec_extract_p9.ll
vec_extract_p9_2.ll
vec_fmuladd.ll
vec_fneg.ll
vec_insert.ll
vec_int_ext.ll
vec_mergeow.ll
vec_minmax.ll
vec_misaligned.ll
vec_mul.ll
vec_mul_even_odd.ll
vec_perf_shuffle.ll
vec_popcnt.ll
vec_revb.ll
vec_rotate_shift.ll
vec_rounding.ll
vec_select.ll
vec_shift.ll
vec_shuffle.ll
vec_shuffle_le.ll
vec_shuffle_p8vector.ll
vec_shuffle_p8vector_le.ll
vec_sldwi.ll
vec_splat.ll
vec_splat_constant.ll
vec_sqrt.ll
vec_urem_const.ll
vec_veqv_vnand_vorc.ll
vec_vrsave.ll
vec_xxpermdi.ll
vec_zero.ll
vector-identity-shuffle.ll
vector-merge-store-fp-constants.ll
vector.ll
vperm-instcombine.ll
vperm-lowering.ll
vrsave-spill.ll
vrspill.ll
vsel-prom.ll
vselect-constants.ll
vsx-args.ll
vsx-div.ll
vsx-elementary-arith.ll
vsx-fma-m.ll
vsx-fma-mutate-trivial-copy.ll
vsx-fma-mutate-undef.ll
vsx-fma-sp.ll
vsx-infl-copy1.ll
vsx-infl-copy2.ll
vsx-ldst-builtin-le.ll
vsx-ldst.ll
vsx-minmax.ll
vsx-p8.ll
vsx-p9.ll
vsx-partword-int-loads-and-stores.ll
vsx-recip-est.ll
vsx-self-copy.ll
vsx-spill-norwstore.ll
vsx-spill.ll
vsx-vec-spill.ll
vsx-word-splats.ll
vsx.ll
vsxD-Form-spills.ll
vsx_insert_extract_le.ll
vsx_scalar_ld_st.ll
vsx_shuffle_le.ll
vtable-reloc.ll
weak_def_can_be_hidden.ll
xray-attribute-instrumentation.ll
xray-conditional-return.ll
xray-ret-is-terminator.ll
xray-tail-call-hidden.ll
xray-tail-call-sled.ll
xvcmpeqdp-v2f64.ll
xxleqv_xxlnand_xxlorc.ll
zero-not-run.ll
zext-and-cmp.ll
zext-bitperm.ll
zext-free.ll
RISCV
SPARC
SystemZ
Thumb
Thumb2
WebAssembly
WinEH
X86
XCore
DebugInfo
Examples
ExecutionEngine
Feature
FileCheck
Instrumentation
Integer
JitListener
LTO
Linker
MC
Object
ObjectYAML
Other
SafepointIRVerifier
SymbolRewriter
TableGen
ThinLTO
Transforms
Unit
Verifier
YAMLParser
tools
.clang-format
CMakeLists.txt
TestRunner.sh
lit.cfg.py
lit.site.cfg.py.in
tools
unittests
utils
.arcconfig
.clang-format
.clang-tidy
.gitattributes
.gitignore
CMakeLists.txt
CODE_OWNERS.TXT
CREDITS.TXT
LICENSE.TXT
LLVMBuild.txt
README.txt
RELEASE_TESTERS.TXT
configure
llvm.spec.in
version.txt.in
nuget
openmp
polly
Directory.Build.props
Directory.Build.targets
NuGet.config
azure-pipelines.yml
build.cmd
build.sh
dir.common.props
global.json
llvm.proj
mxe-Win64.cmake.in
nuget-buildtasks
nunit-lite
roslyn-binaries
rx
xunit-binaries
how-to-bump-roslyn-binaries.md
ikvm-native
llvm
m4
man
mcs
mono
msvc
netcore
po
runtime
samples
scripts
support
tools
COPYING.LIB
LICENSE
Makefile.am
Makefile.in
NEWS
README.md
acinclude.m4
aclocal.m4
autogen.sh
code_of_conduct.md
compile
config.guess
config.h.in
config.rpath
config.sub
configure.REMOVED.git-id
configure.ac.REMOVED.git-id
depcomp
install-sh
ltmain.sh.REMOVED.git-id
missing
mkinstalldirs
mono-uninstalled.pc.in
test-driver
winconfig.h
156 lines
10 KiB
LLVM
156 lines
10 KiB
LLVM
![]() |
; RUN: llc -verify-machineinstrs < %s | FileCheck %s
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; This test case used to fail both with and without -verify-machineinstrs
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; (-verify-machineinstrs would catch the problem right after instruction
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; scheduling because the live intervals would not be right for the registers
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; that were both inputs to the inline asm and also early-clobber outputs).
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target datalayout = "E-m:e-i64:64-n32:64"
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target triple = "powerpc64-bgq-linux"
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%struct._IO_FILE.119.8249.32639.195239.200117.211499.218003.221255.222881.224507.226133.240767.244019.245645.248897.260279.271661.281417.283043.302555.304181.325319.326945.344713 = type { i32, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, %struct._IO_marker.118.8248.32638.195238.200116.211498.218002.221254.222880.224506.226132.240766.244018.245644.248896.260278.271660.281416.283042.302554.304180.325318.326944.344712*, %struct._IO_FILE.119.8249.32639.195239.200117.211499.218003.221255.222881.224507.226133.240767.244019.245645.248897.260279.271661.281417.283043.302555.304181.325319.326945.344713*, i32, i32, i64, i16, i8, [1 x i8], i8*, i64, i8*, i8*, i8*, i8*, i64, i32, [20 x i8] }
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%struct._IO_marker.118.8248.32638.195238.200116.211498.218002.221254.222880.224506.226132.240766.244018.245644.248896.260278.271660.281416.283042.302554.304180.325318.326944.344712 = type { %struct._IO_marker.118.8248.32638.195238.200116.211498.218002.221254.222880.224506.226132.240766.244018.245644.248896.260278.271660.281416.283042.302554.304180.325318.326944.344712*, %struct._IO_FILE.119.8249.32639.195239.200117.211499.218003.221255.222881.224507.226133.240767.244019.245645.248897.260279.271661.281417.283043.302555.304181.325319.326945.344713*, i32 }
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@.str236 = external unnamed_addr constant [121 x i8], align 1
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@.str294 = external unnamed_addr constant [49 x i8], align 1
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; Function Attrs: nounwind
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declare void @fprintf(%struct._IO_FILE.119.8249.32639.195239.200117.211499.218003.221255.222881.224507.226133.240767.244019.245645.248897.260279.271661.281417.283043.302555.304181.325319.326945.344713* nocapture, i8* nocapture readonly, ...) #0
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; Function Attrs: inlinehint nounwind
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define void @_ZN4PAMI6Device2MU15ResourceManager46calculatePerCoreMUResourcesBasedOnAvailabilityEv(i32 %inp32, i64 %inp64) #1 align 2 {
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; CHECK-LABEL: @_ZN4PAMI6Device2MU15ResourceManager46calculatePerCoreMUResourcesBasedOnAvailabilityEv
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; CHECK: sc
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entry:
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%numFreeResourcesInSubgroup = alloca i32, align 4
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%0 = ptrtoint i32* %numFreeResourcesInSubgroup to i64
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br label %for.cond2.preheader
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for.cond2.preheader: ; preds = %if.end23.3, %entry
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%indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %if.end23.3 ]
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%group.098 = phi i32 [ 0, %entry ], [ %inc37, %if.end23.3 ]
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%minFreeBatIdsPerCore.097 = phi i64 [ 32, %entry ], [ %numFreeBatIdsInGroup.0.minFreeBatIdsPerCore.0, %if.end23.3 ]
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%minFreeRecFifosPerCore.096 = phi i64 [ 16, %entry ], [ %minFreeRecFifosPerCore.1, %if.end23.3 ]
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%minFreeInjFifosPerCore.095 = phi i64 [ 32, %entry ], [ %numFreeInjFifosInGroup.0.minFreeInjFifosPerCore.0, %if.end23.3 ]
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%cmp5 = icmp eq i32 %inp32, 0
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br i1 %cmp5, label %if.end, label %if.then
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if.then: ; preds = %if.end23.2, %if.end23.1, %if.end23, %for.cond2.preheader
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unreachable
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if.end: ; preds = %for.cond2.preheader
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%1 = load i32, i32* %numFreeResourcesInSubgroup, align 4
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%conv = zext i32 %1 to i64
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%2 = call { i64, i64, i64, i64 } asm sideeffect "sc", "=&{r0},=&{r3},=&{r4},=&{r5},{r0},{r3},{r4},{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{cr0},~{memory}"(i64 1034, i64 %indvars.iv, i64 %0, i64 %inp64) #2
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%cmp10 = icmp eq i32 0, 0
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br i1 %cmp10, label %if.end14, label %if.then11
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if.then11: ; preds = %if.end.3, %if.end.2, %if.end.1, %if.end
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unreachable
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if.end14: ; preds = %if.end
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%3 = load i32, i32* %numFreeResourcesInSubgroup, align 4
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%cmp19 = icmp eq i32 %inp32, 0
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br i1 %cmp19, label %if.end23, label %if.then20
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if.then20: ; preds = %if.end14.3, %if.end14.2, %if.end14.1, %if.end14
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%conv4.i65.lcssa = phi i32 [ %inp32, %if.end14 ], [ 0, %if.end14.1 ], [ %conv4.i65.2, %if.end14.2 ], [ %conv4.i65.3, %if.end14.3 ]
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call void (%struct._IO_FILE.119.8249.32639.195239.200117.211499.218003.221255.222881.224507.226133.240767.244019.245645.248897.260279.271661.281417.283043.302555.304181.325319.326945.344713*, i8*, ...) @fprintf(%struct._IO_FILE.119.8249.32639.195239.200117.211499.218003.221255.222881.224507.226133.240767.244019.245645.248897.260279.271661.281417.283043.302555.304181.325319.326945.344713* undef, i8* getelementptr inbounds ([121 x i8], [121 x i8]* @.str236, i64 0, i64 0), i32 signext 2503) #3
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call void (%struct._IO_FILE.119.8249.32639.195239.200117.211499.218003.221255.222881.224507.226133.240767.244019.245645.248897.260279.271661.281417.283043.302555.304181.325319.326945.344713*, i8*, ...) @fprintf(%struct._IO_FILE.119.8249.32639.195239.200117.211499.218003.221255.222881.224507.226133.240767.244019.245645.248897.260279.271661.281417.283043.302555.304181.325319.326945.344713* undef, i8* getelementptr inbounds ([49 x i8], [49 x i8]* @.str294, i64 0, i64 0), i32 signext %conv4.i65.lcssa) #3
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unreachable
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if.end23: ; preds = %if.end14
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%conv15 = zext i32 %3 to i64
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%4 = load i32, i32* %numFreeResourcesInSubgroup, align 4
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%conv24 = zext i32 %4 to i64
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%5 = call { i64, i64, i64, i64 } asm sideeffect "sc", "=&{r0},=&{r3},=&{r4},=&{r5},{r0},{r3},{r4},{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{cr0},~{memory}"(i64 1033, i64 0, i64 %0, i64 %inp64) #2
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%cmp5.1 = icmp eq i32 0, 0
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br i1 %cmp5.1, label %if.end.1, label %if.then
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for.end38: ; preds = %if.end23.3
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ret void
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if.end.1: ; preds = %if.end23
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%6 = load i32, i32* %numFreeResourcesInSubgroup, align 4
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%conv.1 = zext i32 %6 to i64
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%add.1 = add nuw nsw i64 %conv.1, %conv
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%7 = call { i64, i64, i64, i64 } asm sideeffect "sc", "=&{r0},=&{r3},=&{r4},=&{r5},{r0},{r3},{r4},{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{cr0},~{memory}"(i64 1034, i64 0, i64 %0, i64 %inp64) #2
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%cmp10.1 = icmp eq i32 %inp32, 0
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br i1 %cmp10.1, label %if.end14.1, label %if.then11
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if.end14.1: ; preds = %if.end.1
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%8 = load i32, i32* %numFreeResourcesInSubgroup, align 4
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%cmp19.1 = icmp eq i32 0, 0
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br i1 %cmp19.1, label %if.end23.1, label %if.then20
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if.end23.1: ; preds = %if.end14.1
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%conv15.1 = zext i32 %8 to i64
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%add16.1 = add nuw nsw i64 %conv15.1, %conv15
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%9 = load i32, i32* %numFreeResourcesInSubgroup, align 4
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%conv24.1 = zext i32 %9 to i64
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%add25.1 = add nuw nsw i64 %conv24.1, %conv24
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%cmp5.2 = icmp eq i32 %inp32, 0
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br i1 %cmp5.2, label %if.end.2, label %if.then
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if.end.2: ; preds = %if.end23.1
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%10 = load i32, i32* %numFreeResourcesInSubgroup, align 4
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%conv.2 = zext i32 %10 to i64
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%add.2 = add nuw nsw i64 %conv.2, %add.1
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%11 = call { i64, i64, i64, i64 } asm sideeffect "sc", "=&{r0},=&{r3},=&{r4},=&{r5},{r0},{r3},{r4},{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{cr0},~{memory}"(i64 1034, i64 %inp64, i64 %0, i64 %inp64) #2
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%cmp10.2 = icmp eq i32 0, 0
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br i1 %cmp10.2, label %if.end14.2, label %if.then11
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if.end14.2: ; preds = %if.end.2
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%12 = load i32, i32* %numFreeResourcesInSubgroup, align 4
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%13 = call { i64, i64, i64, i64 } asm sideeffect "sc", "=&{r0},=&{r3},=&{r4},=&{r5},{r0},{r3},{r4},{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{cr0},~{memory}"(i64 1035, i64 %inp64, i64 %0, i64 0) #2
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%asmresult1.i64.2 = extractvalue { i64, i64, i64, i64 } %13, 1
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%conv4.i65.2 = trunc i64 %asmresult1.i64.2 to i32
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%cmp19.2 = icmp eq i32 %conv4.i65.2, 0
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br i1 %cmp19.2, label %if.end23.2, label %if.then20
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if.end23.2: ; preds = %if.end14.2
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%conv15.2 = zext i32 %12 to i64
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%add16.2 = add nuw nsw i64 %conv15.2, %add16.1
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%14 = load i32, i32* %numFreeResourcesInSubgroup, align 4
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%conv24.2 = zext i32 %14 to i64
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%add25.2 = add nuw nsw i64 %conv24.2, %add25.1
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%cmp5.3 = icmp eq i32 0, 0
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br i1 %cmp5.3, label %if.end.3, label %if.then
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if.end.3: ; preds = %if.end23.2
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%15 = load i32, i32* %numFreeResourcesInSubgroup, align 4
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%conv.3 = zext i32 %15 to i64
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%add.3 = add nuw nsw i64 %conv.3, %add.2
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%cmp10.3 = icmp eq i32 %inp32, 0
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br i1 %cmp10.3, label %if.end14.3, label %if.then11
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if.end14.3: ; preds = %if.end.3
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%16 = load i32, i32* %numFreeResourcesInSubgroup, align 4
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%17 = call { i64, i64, i64, i64 } asm sideeffect "sc", "=&{r0},=&{r3},=&{r4},=&{r5},{r0},{r3},{r4},{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{cr0},~{memory}"(i64 1035, i64 0, i64 %0, i64 0) #2
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%asmresult1.i64.3 = extractvalue { i64, i64, i64, i64 } %17, 1
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%conv4.i65.3 = trunc i64 %asmresult1.i64.3 to i32
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%cmp19.3 = icmp eq i32 %conv4.i65.3, 0
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br i1 %cmp19.3, label %if.end23.3, label %if.then20
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if.end23.3: ; preds = %if.end14.3
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%conv15.3 = zext i32 %16 to i64
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%add16.3 = add nuw nsw i64 %conv15.3, %add16.2
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%add25.3 = add nuw nsw i64 0, %add25.2
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 4
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%cmp27 = icmp ult i64 %add.3, %minFreeInjFifosPerCore.095
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%numFreeInjFifosInGroup.0.minFreeInjFifosPerCore.0 = select i1 %cmp27, i64 %add.3, i64 %minFreeInjFifosPerCore.095
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%cmp30 = icmp ult i64 %add16.3, %minFreeRecFifosPerCore.096
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%minFreeRecFifosPerCore.1 = select i1 %cmp30, i64 %add16.3, i64 %minFreeRecFifosPerCore.096
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%cmp33 = icmp ult i64 %add25.3, %minFreeBatIdsPerCore.097
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%numFreeBatIdsInGroup.0.minFreeBatIdsPerCore.0 = select i1 %cmp33, i64 %add25.3, i64 %minFreeBatIdsPerCore.097
|
||
|
%inc37 = add nuw nsw i32 %group.098, 1
|
||
|
%cmp = icmp ult i32 %inc37, 16
|
||
|
br i1 %cmp, label %for.cond2.preheader, label %for.end38
|
||
|
}
|
||
|
|
||
|
attributes #0 = { nounwind "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "target-cpu"="a2q" }
|
||
|
attributes #1 = { inlinehint nounwind "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "target-cpu"="a2q" }
|
||
|
attributes #2 = { nounwind }
|
||
|
attributes #3 = { cold nounwind }
|
||
|
|