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197 lines
6.2 KiB
C
197 lines
6.2 KiB
C
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//===- CodeGenTarget.h - Target Class Wrapper -------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines wrappers for the Target class and related global
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// functionality. This makes it easier to access the data and provides a single
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// place that needs to check it for validity. All of these classes abort
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// on error conditions.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_UTILS_TABLEGEN_CODEGENTARGET_H
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#define LLVM_UTILS_TABLEGEN_CODEGENTARGET_H
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#include "CodeGenHwModes.h"
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#include "CodeGenInstruction.h"
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#include "CodeGenRegisters.h"
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#include "InfoByHwMode.h"
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#include "SDNodeProperties.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/TableGen/Record.h"
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#include <algorithm>
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namespace llvm {
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struct CodeGenRegister;
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class CodeGenSchedModels;
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class CodeGenTarget;
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/// getValueType - Return the MVT::SimpleValueType that the specified TableGen
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/// record corresponds to.
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MVT::SimpleValueType getValueType(Record *Rec);
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StringRef getName(MVT::SimpleValueType T);
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StringRef getEnumName(MVT::SimpleValueType T);
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/// getQualifiedName - Return the name of the specified record, with a
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/// namespace qualifier if the record contains one.
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std::string getQualifiedName(const Record *R);
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/// CodeGenTarget - This class corresponds to the Target class in the .td files.
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///
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class CodeGenTarget {
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RecordKeeper &Records;
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Record *TargetRec;
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mutable DenseMap<const Record*,
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std::unique_ptr<CodeGenInstruction>> Instructions;
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mutable std::unique_ptr<CodeGenRegBank> RegBank;
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mutable std::vector<Record*> RegAltNameIndices;
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mutable SmallVector<ValueTypeByHwMode, 8> LegalValueTypes;
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CodeGenHwModes CGH;
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void ReadRegAltNameIndices() const;
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void ReadInstructions() const;
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void ReadLegalValueTypes() const;
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mutable std::unique_ptr<CodeGenSchedModels> SchedModels;
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mutable std::vector<const CodeGenInstruction*> InstrsByEnum;
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public:
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CodeGenTarget(RecordKeeper &Records);
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~CodeGenTarget();
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Record *getTargetRecord() const { return TargetRec; }
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const StringRef getName() const;
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/// getInstNamespace - Return the target-specific instruction namespace.
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///
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StringRef getInstNamespace() const;
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/// getInstructionSet - Return the InstructionSet object.
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///
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Record *getInstructionSet() const;
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/// getAsmParser - Return the AssemblyParser definition for this target.
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///
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Record *getAsmParser() const;
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/// getAsmParserVariant - Return the AssmblyParserVariant definition for
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/// this target.
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///
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Record *getAsmParserVariant(unsigned i) const;
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/// getAsmParserVariantCount - Return the AssmblyParserVariant definition
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/// available for this target.
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///
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unsigned getAsmParserVariantCount() const;
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/// getAsmWriter - Return the AssemblyWriter definition for this target.
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///
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Record *getAsmWriter() const;
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/// getRegBank - Return the register bank description.
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CodeGenRegBank &getRegBank() const;
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/// getRegisterByName - If there is a register with the specific AsmName,
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/// return it.
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const CodeGenRegister *getRegisterByName(StringRef Name) const;
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const std::vector<Record*> &getRegAltNameIndices() const {
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if (RegAltNameIndices.empty()) ReadRegAltNameIndices();
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return RegAltNameIndices;
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}
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const CodeGenRegisterClass &getRegisterClass(Record *R) const {
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return *getRegBank().getRegClass(R);
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}
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/// getRegisterVTs - Find the union of all possible SimpleValueTypes for the
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/// specified physical register.
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std::vector<ValueTypeByHwMode> getRegisterVTs(Record *R) const;
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ArrayRef<ValueTypeByHwMode> getLegalValueTypes() const {
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if (LegalValueTypes.empty())
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ReadLegalValueTypes();
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return LegalValueTypes;
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}
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CodeGenSchedModels &getSchedModels() const;
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const CodeGenHwModes &getHwModes() const { return CGH; }
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private:
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DenseMap<const Record*, std::unique_ptr<CodeGenInstruction>> &
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getInstructions() const {
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if (Instructions.empty()) ReadInstructions();
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return Instructions;
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}
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public:
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CodeGenInstruction &getInstruction(const Record *InstRec) const {
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if (Instructions.empty()) ReadInstructions();
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auto I = Instructions.find(InstRec);
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assert(I != Instructions.end() && "Not an instruction");
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return *I->second;
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}
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/// getInstructionsByEnumValue - Return all of the instructions defined by the
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/// target, ordered by their enum value.
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ArrayRef<const CodeGenInstruction *>
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getInstructionsByEnumValue() const {
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if (InstrsByEnum.empty()) ComputeInstrsByEnum();
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return InstrsByEnum;
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}
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typedef ArrayRef<const CodeGenInstruction *>::const_iterator inst_iterator;
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inst_iterator inst_begin() const{return getInstructionsByEnumValue().begin();}
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inst_iterator inst_end() const { return getInstructionsByEnumValue().end(); }
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/// isLittleEndianEncoding - are instruction bit patterns defined as [0..n]?
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///
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bool isLittleEndianEncoding() const;
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/// reverseBitsForLittleEndianEncoding - For little-endian instruction bit
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/// encodings, reverse the bit order of all instructions.
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void reverseBitsForLittleEndianEncoding();
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/// guessInstructionProperties - should we just guess unset instruction
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/// properties?
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bool guessInstructionProperties() const;
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private:
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void ComputeInstrsByEnum() const;
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};
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/// ComplexPattern - ComplexPattern info, corresponding to the ComplexPattern
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/// tablegen class in TargetSelectionDAG.td
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class ComplexPattern {
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MVT::SimpleValueType Ty;
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unsigned NumOperands;
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std::string SelectFunc;
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std::vector<Record*> RootNodes;
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unsigned Properties; // Node properties
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unsigned Complexity;
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public:
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ComplexPattern(Record *R);
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MVT::SimpleValueType getValueType() const { return Ty; }
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unsigned getNumOperands() const { return NumOperands; }
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const std::string &getSelectFunc() const { return SelectFunc; }
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const std::vector<Record*> &getRootNodes() const {
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return RootNodes;
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}
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bool hasProperty(enum SDNP Prop) const { return Properties & (1 << Prop); }
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unsigned getComplexity() const { return Complexity; }
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};
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} // End llvm namespace
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#endif
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