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DAGCombine_trunc_extract.ll
DAGCombiner_illegal_BUILD_VECTOR.ll
DAGCombiner_isAlias.ll
RAbasic-invalid-LR-update.mir
addr-01.ll
addr-02.ll
addr-03.ll
alias-01.ll
alloca-01.ll
alloca-02.ll
alloca-03.ll
alloca-04.ll
and-01.ll
and-02.ll
and-03.ll
and-04.ll
and-05.ll
and-06.ll
and-07.ll
and-08.ll
and-xor-01.ll
args-01.ll
args-02.ll
args-03.ll
args-04.ll
args-05.ll
args-06.ll
args-07.ll
args-08.ll
args-09.ll
args-10.ll
asm-01.ll
asm-02.ll
asm-03.ll
asm-04.ll
asm-05.ll
asm-06.ll
asm-07.ll
asm-08.ll
asm-09.ll
asm-10.ll
asm-11.ll
asm-12.ll
asm-13.ll
asm-14.ll
asm-15.ll
asm-16.ll
asm-17.ll
asm-18.ll
atomic-fence-01.ll
atomic-fence-02.ll
atomic-load-01.ll
atomic-load-02.ll
atomic-load-03.ll
atomic-load-04.ll
atomic-load-05.ll
atomic-store-01.ll
atomic-store-02.ll
atomic-store-03.ll
atomic-store-04.ll
atomic-store-05.ll
atomicrmw-add-01.ll
atomicrmw-add-02.ll
atomicrmw-add-03.ll
atomicrmw-add-04.ll
atomicrmw-add-05.ll
atomicrmw-add-06.ll
atomicrmw-and-01.ll
atomicrmw-and-02.ll
atomicrmw-and-03.ll
atomicrmw-and-04.ll
atomicrmw-and-05.ll
atomicrmw-and-06.ll
atomicrmw-minmax-01.ll
atomicrmw-minmax-02.ll
atomicrmw-minmax-03.ll
atomicrmw-minmax-04.ll
atomicrmw-nand-01.ll
atomicrmw-nand-02.ll
atomicrmw-nand-03.ll
atomicrmw-nand-04.ll
atomicrmw-or-01.ll
atomicrmw-or-02.ll
atomicrmw-or-03.ll
atomicrmw-or-04.ll
atomicrmw-or-05.ll
atomicrmw-or-06.ll
atomicrmw-sub-01.ll
atomicrmw-sub-02.ll
atomicrmw-sub-03.ll
atomicrmw-sub-04.ll
atomicrmw-sub-05.ll
atomicrmw-sub-06.ll
atomicrmw-xchg-01.ll
atomicrmw-xchg-02.ll
atomicrmw-xchg-03.ll
atomicrmw-xchg-04.ll
atomicrmw-xor-01.ll
atomicrmw-xor-02.ll
atomicrmw-xor-03.ll
atomicrmw-xor-04.ll
atomicrmw-xor-05.ll
atomicrmw-xor-06.ll
backchain.ll
branch-01.ll
branch-02.ll
branch-03.ll
branch-04.ll
branch-05.ll
branch-06.ll
branch-07.ll
branch-08.ll
branch-09.ll
branch-10.ll
branch-11.ll
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builtins.ll
call-01.ll
call-02.ll
call-03.ll
call-04.ll
call-05.ll
clear-liverange-spillreg.mir
cmpxchg-01.ll
cmpxchg-02.ll
cmpxchg-03.ll
cmpxchg-04.ll
cmpxchg-05.ll
cmpxchg-06.ll
cond-load-01.ll
cond-load-02.ll
cond-load-03.ll
cond-move-01.ll
cond-move-02.ll
cond-move-03.ll
cond-move-04.mir
cond-move-05.mir
cond-store-01.ll
cond-store-02.ll
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cond-store-06.ll
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cond-store-08.ll
cond-store-09.ll
copy-physreg-128.ll
ctpop-01.ll
dag-combine-01.ll
dag-combine-02.ll
dyn-alloca-offset.ll
expand-zext-pseudo.ll
extract-vector-elt-zEC12.ll
fold-memory-op-impl.ll
fp-abs-01.ll
fp-abs-02.ll
fp-abs-03.ll
fp-abs-04.ll
fp-add-01.ll
fp-add-02.ll
fp-add-03.ll
fp-add-04.ll
fp-cmp-01.ll
fp-cmp-02.ll
fp-cmp-03.ll
fp-cmp-04.ll
fp-cmp-05.ll
fp-cmp-06.ll
fp-cmp-07.mir
fp-const-01.ll
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fp-conv-01.ll
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fp-conv-10.ll
fp-conv-11.ll
fp-conv-12.ll
fp-conv-13.ll
fp-conv-14.ll
fp-conv-15.ll
fp-conv-16.ll
fp-conv-17.mir
fp-copysign-01.ll
fp-copysign-02.ll
fp-div-01.ll
fp-div-02.ll
fp-div-03.ll
fp-div-04.ll
fp-libcall.ll
fp-move-01.ll
fp-move-02.ll
fp-move-03.ll
fp-move-04.ll
fp-move-05.ll
fp-move-06.ll
fp-move-07.ll
fp-move-08.ll
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fp-mul-01.ll
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fp-mul-03.ll
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fp-mul-05.ll
fp-mul-06.ll
fp-mul-07.ll
fp-mul-08.ll
fp-mul-09.ll
fp-mul-10.ll
fp-mul-11.ll
fp-mul-12.ll
fp-neg-01.ll
fp-neg-02.ll
fp-round-01.ll
fp-round-02.ll
fp-round-03.ll
fp-sincos-01.ll
fp-sqrt-01.ll
fp-sqrt-02.ll
fp-sqrt-03.ll
fp-sqrt-04.ll
fp-sub-01.ll
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fp-sub-03.ll
fp-sub-04.ll
fpc-intrinsics.ll
frame-01.ll
frame-02.ll
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frameaddr-01.ll
htm-intrinsics.ll
insert-01.ll
insert-02.ll
insert-03.ll
insert-04.ll
insert-05.ll
insert-06.ll
int-abs-01.ll
int-add-01.ll
int-add-02.ll
int-add-03.ll
int-add-04.ll
int-add-05.ll
int-add-06.ll
int-add-07.ll
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int-add-15.ll
int-add-16.ll
int-add-17.ll
int-cmp-01.ll
int-cmp-02.ll
int-cmp-03.ll
int-cmp-04.ll
int-cmp-05.ll
int-cmp-06.ll
int-cmp-07.ll
int-cmp-08.ll
int-cmp-09.ll
int-cmp-10.ll
int-cmp-11.ll
int-cmp-12.ll
int-cmp-13.ll
int-cmp-14.ll
int-cmp-15.ll
int-cmp-16.ll
int-cmp-17.ll
int-cmp-18.ll
int-cmp-19.ll
int-cmp-20.ll
int-cmp-21.ll
int-cmp-22.ll
int-cmp-23.ll
int-cmp-24.ll
int-cmp-25.ll
int-cmp-26.ll
int-cmp-27.ll
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int-cmp-29.ll
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int-cmp-32.ll
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int-cmp-36.ll
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int-cmp-38.ll
int-cmp-39.ll
int-cmp-40.ll
int-cmp-41.ll
int-cmp-42.ll
int-cmp-43.ll
int-cmp-44.ll
int-cmp-45.ll
int-cmp-46.ll
int-cmp-47.ll
int-cmp-48.ll
int-cmp-49.ll
int-cmp-50.ll
int-cmp-51.ll
int-cmp-52.ll
int-cmp-53.ll
int-cmp-54.ll
int-const-01.ll
int-const-02.ll
int-const-03.ll
int-const-04.ll
int-const-05.ll
int-const-06.ll
int-conv-01.ll
int-conv-02.ll
int-conv-03.ll
int-conv-04.ll
int-conv-05.ll
int-conv-06.ll
int-conv-07.ll
int-conv-08.ll
int-conv-09.ll
int-conv-10.ll
int-conv-11.ll
int-conv-12.ll
int-conv-13.ll
int-div-01.ll
int-div-02.ll
int-div-03.ll
int-div-04.ll
int-div-05.ll
int-div-06.ll
int-move-01.ll
int-move-02.ll
int-move-03.ll
int-move-04.ll
int-move-05.ll
int-move-06.ll
int-move-07.ll
int-move-08.ll
int-move-09.ll
int-mul-01.ll
int-mul-02.ll
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int-mul-04.ll
int-mul-05.ll
int-mul-06.ll
int-mul-07.ll
int-mul-08.ll
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int-mul-10.ll
int-mul-11.ll
int-neg-01.ll
int-neg-02.ll
int-sub-01.ll
int-sub-02.ll
int-sub-03.ll
int-sub-04.ll
int-sub-05.ll
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int-sub-09.ll
int-sub-10.ll
la-01.ll
la-02.ll
la-03.ll
la-04.ll
list-ilp-crash.ll
lit.local.cfg
locr-legal-regclass.ll
loop-01.ll
loop-02.ll
loop-03.ll
lower-copy-undef-src.mir
mature-mc-support.ll
memchr-01.ll
memchr-nobuiltin.ll
memcmp-01.ll
memcmp-nobuiltin.ll
memcpy-01.ll
memcpy-02.ll
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pie.ll
pr31710.ll
pr32372.ll
pr32505.ll
prefetch-01.ll
regalloc-GR128.ll
regalloc-fast-invalid-kill-flag.mir
ret-addr-01.ll
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shift-12.ll
spill-01.ll
splitMove_undefReg_mverifier.ll
splitMove_undefReg_mverifier_2.ll
stack-guard.ll
strcmp-01.ll
strcmp-nobuiltin.ll
strcpy-01.ll
strcpy-nobuiltin.ll
strlen-01.ll
strlen-nobuiltin.ll
swift-return.ll
swifterror.ll
swiftself.ll
tail-call-mem-intrinsics.ll
tdc-01.ll
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vec-cmp-cmp-logic-select.ll
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vec-extract-01.ll
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vec-intrinsics-01.ll.REMOVED.git-id
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201 lines
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201 lines
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LLVM
![]() |
; Test vector merge high.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s
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; Test a canonical v16i8 merge high.
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define <16 x i8> @f1(<16 x i8> %val1, <16 x i8> %val2) {
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; CHECK-LABEL: f1:
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; CHECK: vmrhb %v24, %v24, %v26
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; CHECK: br %r14
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%ret = shufflevector <16 x i8> %val1, <16 x i8> %val2,
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<16 x i32> <i32 0, i32 16, i32 1, i32 17,
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i32 2, i32 18, i32 3, i32 19,
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i32 4, i32 20, i32 5, i32 21,
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i32 6, i32 22, i32 7, i32 23>
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ret <16 x i8> %ret
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}
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; Test a reversed v16i8 merge high.
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define <16 x i8> @f2(<16 x i8> %val1, <16 x i8> %val2) {
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; CHECK-LABEL: f2:
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; CHECK: vmrhb %v24, %v26, %v24
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; CHECK: br %r14
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%ret = shufflevector <16 x i8> %val1, <16 x i8> %val2,
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<16 x i32> <i32 16, i32 0, i32 17, i32 1,
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i32 18, i32 2, i32 19, i32 3,
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i32 20, i32 4, i32 21, i32 5,
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i32 22, i32 6, i32 23, i32 7>
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ret <16 x i8> %ret
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}
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; Test a v16i8 merge high with only the first operand being used.
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define <16 x i8> @f3(<16 x i8> %val1, <16 x i8> %val2) {
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; CHECK-LABEL: f3:
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; CHECK: vmrhb %v24, %v24, %v24
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; CHECK: br %r14
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%ret = shufflevector <16 x i8> %val1, <16 x i8> %val2,
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<16 x i32> <i32 0, i32 0, i32 1, i32 1,
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i32 2, i32 2, i32 3, i32 3,
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i32 4, i32 4, i32 5, i32 5,
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i32 6, i32 6, i32 7, i32 7>
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ret <16 x i8> %ret
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}
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; Test a v16i8 merge high with only the second operand being used.
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; This is converted into @f3 by target-independent code.
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define <16 x i8> @f4(<16 x i8> %val1, <16 x i8> %val2) {
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; CHECK-LABEL: f4:
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; CHECK: vmrhb %v24, %v26, %v26
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; CHECK: br %r14
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%ret = shufflevector <16 x i8> %val1, <16 x i8> %val2,
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<16 x i32> <i32 16, i32 16, i32 17, i32 17,
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i32 18, i32 18, i32 19, i32 19,
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i32 20, i32 20, i32 21, i32 21,
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i32 22, i32 22, i32 23, i32 23>
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ret <16 x i8> %ret
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}
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; Test a v16i8 merge with both operands being the same. This too is
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; converted into @f3 by target-independent code.
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define <16 x i8> @f5(<16 x i8> %val) {
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|
; CHECK-LABEL: f5:
|
||
|
; CHECK: vmrhb %v24, %v24, %v24
|
||
|
; CHECK: br %r14
|
||
|
%ret = shufflevector <16 x i8> %val, <16 x i8> %val,
|
||
|
<16 x i32> <i32 0, i32 16, i32 17, i32 17,
|
||
|
i32 18, i32 2, i32 3, i32 3,
|
||
|
i32 20, i32 20, i32 5, i32 5,
|
||
|
i32 6, i32 22, i32 23, i32 7>
|
||
|
ret <16 x i8> %ret
|
||
|
}
|
||
|
|
||
|
; Test a v16i8 merge in which some of the indices are don't care.
|
||
|
define <16 x i8> @f6(<16 x i8> %val1, <16 x i8> %val2) {
|
||
|
; CHECK-LABEL: f6:
|
||
|
; CHECK: vmrhb %v24, %v24, %v26
|
||
|
; CHECK: br %r14
|
||
|
%ret = shufflevector <16 x i8> %val1, <16 x i8> %val2,
|
||
|
<16 x i32> <i32 0, i32 undef, i32 1, i32 17,
|
||
|
i32 undef, i32 18, i32 undef, i32 undef,
|
||
|
i32 undef, i32 20, i32 5, i32 21,
|
||
|
i32 undef, i32 22, i32 7, i32 undef>
|
||
|
ret <16 x i8> %ret
|
||
|
}
|
||
|
|
||
|
; Test a v16i8 merge in which one of the operands is undefined and where
|
||
|
; indices for that operand are "don't care". Target-independent code
|
||
|
; converts the indices themselves into "undef"s.
|
||
|
define <16 x i8> @f7(<16 x i8> %val) {
|
||
|
; CHECK-LABEL: f7:
|
||
|
; CHECK: vmrhb %v24, %v24, %v24
|
||
|
; CHECK: br %r14
|
||
|
%ret = shufflevector <16 x i8> undef, <16 x i8> %val,
|
||
|
<16 x i32> <i32 11, i32 16, i32 17, i32 5,
|
||
|
i32 18, i32 10, i32 19, i32 19,
|
||
|
i32 20, i32 20, i32 21, i32 3,
|
||
|
i32 2, i32 22, i32 9, i32 23>
|
||
|
ret <16 x i8> %ret
|
||
|
}
|
||
|
|
||
|
; Test a canonical v8i16 merge high.
|
||
|
define <8 x i16> @f8(<8 x i16> %val1, <8 x i16> %val2) {
|
||
|
; CHECK-LABEL: f8:
|
||
|
; CHECK: vmrhh %v24, %v24, %v26
|
||
|
; CHECK: br %r14
|
||
|
%ret = shufflevector <8 x i16> %val1, <8 x i16> %val2,
|
||
|
<8 x i32> <i32 0, i32 8, i32 1, i32 9,
|
||
|
i32 2, i32 10, i32 3, i32 11>
|
||
|
ret <8 x i16> %ret
|
||
|
}
|
||
|
|
||
|
; Test a reversed v8i16 merge high.
|
||
|
define <8 x i16> @f9(<8 x i16> %val1, <8 x i16> %val2) {
|
||
|
; CHECK-LABEL: f9:
|
||
|
; CHECK: vmrhh %v24, %v26, %v24
|
||
|
; CHECK: br %r14
|
||
|
%ret = shufflevector <8 x i16> %val1, <8 x i16> %val2,
|
||
|
<8 x i32> <i32 8, i32 0, i32 9, i32 1,
|
||
|
i32 10, i32 2, i32 11, i32 3>
|
||
|
ret <8 x i16> %ret
|
||
|
}
|
||
|
|
||
|
; Test a canonical v4i32 merge high.
|
||
|
define <4 x i32> @f10(<4 x i32> %val1, <4 x i32> %val2) {
|
||
|
; CHECK-LABEL: f10:
|
||
|
; CHECK: vmrhf %v24, %v24, %v26
|
||
|
; CHECK: br %r14
|
||
|
%ret = shufflevector <4 x i32> %val1, <4 x i32> %val2,
|
||
|
<4 x i32> <i32 0, i32 4, i32 1, i32 5>
|
||
|
ret <4 x i32> %ret
|
||
|
}
|
||
|
|
||
|
; Test a reversed v4i32 merge high.
|
||
|
define <4 x i32> @f11(<4 x i32> %val1, <4 x i32> %val2) {
|
||
|
; CHECK-LABEL: f11:
|
||
|
; CHECK: vmrhf %v24, %v26, %v24
|
||
|
; CHECK: br %r14
|
||
|
%ret = shufflevector <4 x i32> %val1, <4 x i32> %val2,
|
||
|
<4 x i32> <i32 4, i32 0, i32 5, i32 1>
|
||
|
ret <4 x i32> %ret
|
||
|
}
|
||
|
|
||
|
; Test a canonical v2i64 merge high.
|
||
|
define <2 x i64> @f12(<2 x i64> %val1, <2 x i64> %val2) {
|
||
|
; CHECK-LABEL: f12:
|
||
|
; CHECK: vmrhg %v24, %v24, %v26
|
||
|
; CHECK: br %r14
|
||
|
%ret = shufflevector <2 x i64> %val1, <2 x i64> %val2,
|
||
|
<2 x i32> <i32 0, i32 2>
|
||
|
ret <2 x i64> %ret
|
||
|
}
|
||
|
|
||
|
; Test a reversed v2i64 merge high.
|
||
|
define <2 x i64> @f13(<2 x i64> %val1, <2 x i64> %val2) {
|
||
|
; CHECK-LABEL: f13:
|
||
|
; CHECK: vmrhg %v24, %v26, %v24
|
||
|
; CHECK: br %r14
|
||
|
%ret = shufflevector <2 x i64> %val1, <2 x i64> %val2,
|
||
|
<2 x i32> <i32 2, i32 0>
|
||
|
ret <2 x i64> %ret
|
||
|
}
|
||
|
|
||
|
; Test a canonical v4f32 merge high.
|
||
|
define <4 x float> @f14(<4 x float> %val1, <4 x float> %val2) {
|
||
|
; CHECK-LABEL: f14:
|
||
|
; CHECK: vmrhf %v24, %v24, %v26
|
||
|
; CHECK: br %r14
|
||
|
%ret = shufflevector <4 x float> %val1, <4 x float> %val2,
|
||
|
<4 x i32> <i32 0, i32 4, i32 1, i32 5>
|
||
|
ret <4 x float> %ret
|
||
|
}
|
||
|
|
||
|
; Test a reversed v4f32 merge high.
|
||
|
define <4 x float> @f15(<4 x float> %val1, <4 x float> %val2) {
|
||
|
; CHECK-LABEL: f15:
|
||
|
; CHECK: vmrhf %v24, %v26, %v24
|
||
|
; CHECK: br %r14
|
||
|
%ret = shufflevector <4 x float> %val1, <4 x float> %val2,
|
||
|
<4 x i32> <i32 4, i32 0, i32 5, i32 1>
|
||
|
ret <4 x float> %ret
|
||
|
}
|
||
|
|
||
|
; Test a canonical v2f64 merge high.
|
||
|
define <2 x double> @f16(<2 x double> %val1, <2 x double> %val2) {
|
||
|
; CHECK-LABEL: f16:
|
||
|
; CHECK: vmrhg %v24, %v24, %v26
|
||
|
; CHECK: br %r14
|
||
|
%ret = shufflevector <2 x double> %val1, <2 x double> %val2,
|
||
|
<2 x i32> <i32 0, i32 2>
|
||
|
ret <2 x double> %ret
|
||
|
}
|
||
|
|
||
|
; Test a reversed v2f64 merge high.
|
||
|
define <2 x double> @f17(<2 x double> %val1, <2 x double> %val2) {
|
||
|
; CHECK-LABEL: f17:
|
||
|
; CHECK: vmrhg %v24, %v26, %v24
|
||
|
; CHECK: br %r14
|
||
|
%ret = shufflevector <2 x double> %val1, <2 x double> %val2,
|
||
|
<2 x i32> <i32 2, i32 0>
|
||
|
ret <2 x double> %ret
|
||
|
}
|