Files
acceptance-tests
data
debian
docs
external
Newtonsoft.Json
api-doc-tools
api-snapshot
aspnetwebstack
bdwgc
binary-reference-assemblies
bockbuild
boringssl
cecil
cecil-legacy
corefx
corert
helix-binaries
ikdasm
ikvm
illinker-test-assets
linker
llvm-project
clang
clang-tools-extra
compiler-rt
libcxx
libcxxabi
libunwind
lld
lldb
llvm
bindings
cmake
docs
examples
include
lib
projects
resources
runtimes
scripts
test
Analysis
Assembler
Bindings
Bitcode
BugPoint
CodeGen
AArch64
AMDGPU
ARC
ARM
AVR
BPF
Generic
Hexagon
Inputs
Lanai
MIR
MSP430
Mips
NVPTX
Nios2
PowerPC
2004-11-29-ShrCrash.ll
2004-11-30-shift-crash.ll
2004-11-30-shr-var-crash.ll
2004-12-12-ZeroSizeCommon.ll
2005-01-14-SetSelectCrash.ll
2005-01-14-UndefLong.ll
2005-08-12-rlwimi-crash.ll
2005-09-02-LegalizeDuplicatesCalls.ll
2005-10-08-ArithmeticRotate.ll
2005-11-30-vastart-crash.ll
2006-01-11-darwin-fp-argument.ll
2006-01-20-ShiftPartsCrash.ll
2006-04-01-FloatDoubleExtend.ll
2006-04-05-splat-ish.ll
2006-04-19-vmaddfp-crash.ll
2006-05-12-rlwimi-crash.ll
2006-07-07-ComputeMaskedBits.ll
2006-07-19-stwbrx-crash.ll
2006-08-11-RetVector.ll
2006-08-15-SelectionCrash.ll
2006-09-28-shift_64.ll
2006-10-13-Miscompile.ll
2006-10-17-brcc-miscompile.ll
2006-10-17-ppc64-alloca.ll
2006-11-10-DAGCombineMiscompile.ll
2006-11-29-AltivecFPSplat.ll
2006-12-07-LargeAlloca.ll
2006-12-07-SelectCrash.ll
2007-01-04-ArgExtension.ll
2007-01-15-AsmDialect.ll
2007-01-29-lbrx-asm.ll
2007-01-31-InlineAsmAddrMode.ll
2007-02-16-AlignPacked.ll
2007-02-16-InlineAsmNConstraint.ll
2007-02-23-lr-saved-twice.ll
2007-03-24-cntlzd.ll
2007-03-30-SpillerCrash.ll.REMOVED.git-id
2007-04-24-InlineAsm-I-Modifier.ll
2007-04-30-InlineAsmEarlyClobber.ll
2007-05-03-InlineAsm-S-Constraint.ll
2007-05-14-InlineAsmSelectCrash.ll
2007-05-22-tailmerge-3.ll
2007-05-30-dagcombine-miscomp.ll
2007-06-28-BCCISelBug.ll
2007-08-04-CoalescerAssert.ll
2007-09-04-AltivecDST.ll
2007-09-07-LoadStoreIdxForms.ll
2007-09-08-unaligned.ll
2007-09-11-RegCoalescerAssert.ll
2007-09-12-LiveIntervalsAssert.ll
2007-10-16-InlineAsmFrameOffset.ll
2007-10-18-PtrArithmetic.ll
2007-10-21-LocalRegAllocAssert.ll
2007-10-21-LocalRegAllocAssert2.ll
2007-11-04-CoalescerCrash.ll
2007-11-16-landingpad-split.ll
2007-11-19-VectorSplitting.ll
2008-02-05-LiveIntervalsAssert.ll
2008-02-09-LocalRegAllocAssert.ll
2008-03-05-RegScavengerAssert.ll
2008-03-17-RegScavengerCrash.ll
2008-03-18-RegScavengerAssert.ll
2008-03-24-AddressRegImm.ll
2008-03-24-CoalescerBug.ll
2008-03-26-CoalescerBug.ll
2008-04-10-LiveIntervalCrash.ll
2008-04-16-CoalescerBug.ll
2008-04-23-CoalescerCrash.ll
2008-05-01-ppc_fp128.ll
2008-06-19-LegalizerCrash.ll
2008-06-21-F128LoadStore.ll
2008-06-23-LiveVariablesCrash.ll
2008-07-10-SplatMiscompile.ll
2008-07-15-Bswap.ll
2008-07-15-Fabs.ll
2008-07-15-SignExtendInreg.ll
2008-07-17-Fneg.ll
2008-07-24-PPC64-CCBug.ll
2008-09-12-CoalescerBug.ll
2008-10-17-AsmMatchingOperands.ll
2008-10-28-UnprocessedNode.ll
2008-10-28-f128-i32.ll
2008-10-31-PPCF128Libcalls.ll
2008-12-02-LegalizeTypeAssert.ll
2009-01-16-DeclareISelBug.ll
2009-03-17-LSRBug.ll
2009-05-28-LegalizeBRCC.ll
2009-07-16-InlineAsm-M-Operand.ll
2009-08-17-inline-asm-addr-mode-breakage.ll
2009-09-18-carrybit.ll
2009-11-15-ProcImpDefsBug.ll
2009-11-25-ImpDefBug.ll
2010-02-04-EmptyGlobal.ll
2010-02-12-saveCR.ll
2010-03-09-indirect-call.ll
2010-04-01-MachineCSEBug.ll
2010-05-03-retaddr1.ll
2010-10-11-Fast-Varargs.ll
2010-12-18-PPCStackRefs.ll
2011-12-05-NoSpillDupCR.ll
2011-12-06-SpillAndRestoreCR.ll
2011-12-08-DemandedBitsMiscompile.ll
2012-09-16-TOC-entry-check.ll
2012-10-11-dynalloc.ll
2012-10-12-bitcast.ll
2012-11-16-mischedcall.ll
2013-05-15-preinc-fold.ll
2013-07-01-PHIElimBug.ll
2016-01-07-BranchWeightCrash.ll
2016-04-16-ADD8TLS.ll
2016-04-17-combine.ll
2016-04-28-setjmp.ll
Atomics-64.ll
BoolRetToIntTest-2.ll
BoolRetToIntTest.ll
BreakableToken-reduced.ll
CompareEliminationSpillIssue.ll
DbgValueOtherTargets.test
Frames-alloca.ll
Frames-large.ll
Frames-leaf.ll
Frames-small.ll
LargeAbsoluteAddr.ll
MCSE-caller-preserved-reg.ll
MMO-flags-assertion.ll
MergeConsecutiveStores.ll
PR33636.ll
PR33671.ll
PR3488.ll
PR35812-neg-cmpxchg.ll
VSX-DForm-Scalars.ll
VSX-XForm-Scalars.ll
a2-fp-basic.ll
a2q-stackalign.ll
a2q.ll
aa-tbaa.ll
aantidep-def-ec.mir
aantidep-inline-asm-use.ll
add-fi.ll
addc.ll
addegluecrash.ll
addi-licm.ll
addi-offset-fold.ll
addi-reassoc.ll
addisdtprelha-nonr3.mir
addrfuncstr.ll
aggressive-anti-dep-breaker-subreg.ll
alias.ll
align.ll
allocate-r0.ll
altivec-ord.ll
and-branch.ll
and-elim.ll
and-imm.ll
and_add.ll
and_sext.ll
and_sra.ll
andc.ll
anon_aggr.ll
anyext_srl.ll
arr-fp-arg-no-copy.ll
ashr-neg1.ll
asm-Zy.ll
asm-constraints.ll
asm-dialect.ll
asm-printer-topological-order.ll
asym-regclass-copy.ll
atomic-1.ll
atomic-2.ll
atomic-minmax.ll
atomics-constant.ll
atomics-fences.ll
atomics-indexed.ll
atomics-regression.ll.REMOVED.git-id
atomics.ll
available-externally.ll
bdzlr.ll
big-endian-actual-args.ll
big-endian-call-result.ll
big-endian-formal-args.ll
bitcasts-direct-move.ll
blockaddress.ll
bperm.ll
branch-hint.ll
branch-opt.ll
branch_coalesce.ll
bswap-load-store.ll
bswap64.ll
build-vector-tests.ll.REMOVED.git-id
buildvec_canonicalize.ll
builtins-ppc-elf2-abi.ll
builtins-ppc-p8vector.ll
bv-pres-v8i1.ll
bv-widen-undef.ll
byval-agg-info.ll
byval-aliased.ll
calls.ll
can-lower-ret.ll
cannonicalize-vector-shifts.ll
cc.ll
change-no-infs.ll
cmp-cmp.ll
cmp_elimination.ll
cmpb-ppc32.ll
cmpb.ll
coal-sections.ll
coalesce-ext.ll
code-align.ll
combine-to-pre-index-store-crash.ll
combine_loads_from_build_pair.ll
compare-duplicate.ll
compare-simm.ll
complex-return.ll
constants-i64.ll
constants.ll
convert-rr-to-ri-instrs-R0-special-handling.mir
convert-rr-to-ri-instrs-out-of-range.mir
convert-rr-to-ri-instrs.mir.REMOVED.git-id
copysignl.ll
cr-spills.ll
cr1eq-no-extra-moves.ll
cr1eq.ll
cr_spilling.ll
crash.ll
crbit-asm-disabled.ll
crbit-asm.ll
crbits.ll
crsave.ll
crypto_bifs.ll
ctr-cleanup.ll
ctr-loop-tls-const.ll
ctr-minmaxnum.ll
ctrloop-asm.ll
ctrloop-cpsgn.ll
ctrloop-fp64.ll
ctrloop-i128.ll
ctrloop-i64.ll
ctrloop-intrin.ll
ctrloop-large-ec.ll
ctrloop-le.ll
ctrloop-lt.ll
ctrloop-ne.ll
ctrloop-reg.ll
ctrloop-s000.ll
ctrloop-sh.ll
ctrloop-shortLoops.ll
ctrloop-sums.ll
ctrloop-udivti3.ll
ctrloops-softfloat.ll
ctrloops.ll
cttz.ll
cxx_tlscc64.ll
darwin-labels.ll
dbg.ll
dcbt-sched.ll
debuginfo-split-int.ll
debuginfo-stackarg.ll
delete-node.ll
direct-move-profit.ll
div-2.ll
div-e-32.ll
div-e-all.ll
duplicate-returns-for-tailcall.ll
dyn-alloca-aligned.ll
dyn-alloca-offset.ll
e500-1.ll
early-ret.ll
early-ret2.ll
ec-input.ll
eh-dwarf-cfa.ll
empty-functions.ll
emptystruct.ll
emutls_generic.ll
eqv-andc-orc-nor.ll
expand-contiguous-isel.ll
expand-foldable-isel.ll
expand-isel-1.mir
expand-isel-10.mir
expand-isel-2.mir
expand-isel-3.mir
expand-isel-4.mir
expand-isel-5.mir
expand-isel-6.mir
expand-isel-7.mir
expand-isel-8.mir
expand-isel-9.mir
expand-isel.ll
ext-bool-trunc-repl.ll
extra-toc-reg-deps.ll
extsh.ll
f32-to-i64.ll
fabs.ll
fast-isel-GEP-coalesce.ll
fast-isel-binary.ll
fast-isel-br-const.ll
fast-isel-call.ll
fast-isel-cmp-imm.ll
fast-isel-const.ll
fast-isel-conversion-p5.ll
fast-isel-conversion.ll
fast-isel-crash.ll
fast-isel-ext.ll
fast-isel-fcmp-nan.ll
fast-isel-fold.ll
fast-isel-fpconv.ll
fast-isel-i64offset.ll
fast-isel-icmp-split.ll
fast-isel-indirectbr.ll
fast-isel-load-store-vsx.ll
fast-isel-load-store.ll
fast-isel-redefinition.ll
fast-isel-ret.ll
fast-isel-shifter.ll
fastisel-gep-promote-before-add.ll
fcpsgn.ll
fdiv-combine.ll
float-asmprint.ll
float-to-int.ll
floatPSA.ll
flt-preinc.ll
fma-aggr-FMF.ll
fma-assoc.ll
fma-ext.ll
fma-mutate-duplicate-vreg.ll
fma-mutate-register-constraint.ll
fma-mutate.ll
fma.ll
fmaxnum.ll
fminnum.ll
fnabs.ll
fneg.ll
fold-li.ll
fold-zero.ll
fp-branch.ll
fp-int-conversions-direct-moves.ll
fp-int-fp.ll
fp-splat.ll
fp-to-int-ext.ll
fp-to-int-to-fp.ll
fp128-bitcast-after-operation.ll
fp2int2fp-ppcfp128.ll
fp64-to-int16.ll
fp_to_uint.ll
fpcopy.ll
frame-size.ll
frameaddr.ll
frounds.ll
fsel.ll
fsl-e500mc.ll
fsl-e5500.ll
fsqrt.ll
func-addr-consts.ll
func-addr.ll
glob-comp-aa-crash.ll
gpr-vsr-spill.ll
hello-reloc.s
hello.ll
hidden-vis-2.ll
hidden-vis.ll
htm.ll
i1-ext-fold.ll
i1-to-double.ll
i128-and-beyond.ll
i32-to-float.ll
i64-to-float.ll
i64_fp.ll
i64_fp_round.ll
ia-mem-r0.ll
ia-neg-const.ll
iabs.ll
ifcvt-forked-bug-2016-08-08.ll
ifcvt.ll
illegal-element-type.ll
in-asm-f64-reg.ll
indexed-load.ll
indirect-hidden.ll
indirectbr.ll
inline-asm-s-modifier.ll
inline-asm-scalar-to-vector-error.ll
inlineasm-copy.ll
inlineasm-i64-reg.ll
int-fp-conv-0.ll
int-fp-conv-1.ll
inverted-bool-compares.ll
isel-rc-nox0.ll
isel.ll
ispositive.ll
itofp128.ll
jaggedstructs.ll
lbz-from-ld-shift.ll
lbzux.ll
ld-st-upd.ll
ldtoc-inv.ll
lha.ll
licm-remat.ll
licm-tocReg.ll
lit.local.cfg
livephysregs.mir
load-constant-addr.ll
load-shift-combine.ll
load-two-flts.ll
load-v4i8-improved.ll
logic-ops-on-compares.ll
long-compare.ll
longcall.ll
longdbl-truncate.ll
loop-data-prefetch-inner.ll
loop-data-prefetch.ll
loop-prep-all.ll
lsa.ll
lsr-postinc-pos.ll
lxv-aligned-stack-slots.ll
lxvw4x-bug.ll
machine-combiner.ll
mask64.ll
mature-mc-support.ll
mc-instrlat.ll
mcm-1.ll
mcm-10.ll
mcm-11.ll
mcm-12.ll
mcm-13.ll
mcm-2.ll
mcm-3.ll
mcm-4.ll
mcm-5.ll
mcm-6.ll
mcm-7.ll
mcm-8.ll
mcm-9.ll
mcm-default.ll
mcm-obj-2.ll
mcm-obj.ll
mcount-insertion.ll
mem-rr-addr-mode.ll
memCmpUsedInZeroEqualityComparison.ll
mem_update.ll
memcmp.ll
memcmpIR.ll
memcpy-vec.ll
memcpy_dereferenceable.ll
memset-nc-le.ll
memset-nc.ll
merge-st-chain-op.ll
merge_stores_dereferenceable.ll
mftb.ll
misched-inorder-latency.ll
misched.ll
mtvsrdd.ll
mul-neg-power-2.ll
mul-with-overflow.ll
mulhs.ll
mulli64.ll
mult-alt-generic-powerpc.ll
mult-alt-generic-powerpc64.ll
multi-return.ll
named-reg-alloc-r0.ll
named-reg-alloc-r1-64.ll
named-reg-alloc-r1.ll
named-reg-alloc-r13-64.ll
named-reg-alloc-r13.ll
named-reg-alloc-r2-64.ll
named-reg-alloc-r2.ll
neg.ll
negate-i1.ll
negctr.ll
no-dead-strip.ll
no-dup-of-bdnz.ll
no-dup-spill-fp.ll
no-ext-with-count-zeros.ll
no-extra-fp-conv-ldst.ll
no-pref-jumps.ll
no-rlwimi-trivial-commute.mir
novrsave.ll
opt-cmp-inst-cr0-live.ll
opt-li-add-to-addi.ll
opt-sub-inst-cr0-live.mir
optcmp.ll
optnone-crbits-i1-ret.ll
or-addressing-mode.ll
ori_imm32.ll
p8-isel-sched.ll
p8-scalar_vector_conversions.ll
p8altivec-shuffles-pred.ll
p9-vector-compares-and-counts.ll
p9-vinsert-vextract.ll
p9-xxinsertw-xxextractuw.ll
peephole-align.ll
pie.ll
pip-inner.ll
popcnt.ll
post-ra-ec.ll
power9-moves-and-splats.ll
ppc-crbits-onoff.ll
ppc-ctr-dead-code.ll
ppc-empty-fs.ll
ppc-prologue.ll
ppc-redzone-alignment-bug.ll
ppc-shrink-wrapping.ll
ppc-vaarg-agg.ll
ppc32-align-long-double-sf.ll
ppc32-constant-BE-ppcf128.ll
ppc32-cyclecounter.ll
ppc32-i1-vaarg.ll
ppc32-lshrti3.ll
ppc32-nest.ll
ppc32-pic-large.ll
ppc32-pic.ll
ppc32-skip-regs.ll
ppc32-vacopy.ll
ppc440-fp-basic.ll
ppc440-msync.ll
ppc64-32bit-addic.ll
ppc64-P9-mod.ll
ppc64-P9-vabsd.ll
ppc64-abi-extend.ll
ppc64-align-long-double.ll
ppc64-altivec-abi.ll
ppc64-anyregcc-crash.ll
ppc64-anyregcc.ll
ppc64-blnop.ll
ppc64-byval-align.ll
ppc64-calls.ll
ppc64-crash.ll
ppc64-cyclecounter.ll
ppc64-elf-abi.ll
ppc64-fastcc-fast-isel.ll
ppc64-fastcc.ll
ppc64-func-desc-hoist.ll
ppc64-gep-opt.ll
ppc64-get-cache-line-size.ll
ppc64-i128-abi.ll
ppc64-icbt-pwr7.ll
ppc64-icbt-pwr8.ll
ppc64-linux-func-size.ll
ppc64-nest.ll
ppc64-nonfunc-calls.ll
ppc64-patchpoint.ll
ppc64-pre-inc-no-extra-phi.ll
ppc64-prefetch.ll
ppc64-r2-alloc.ll
ppc64-sibcall-shrinkwrap.ll
ppc64-sibcall.ll
ppc64-smallarg.ll
ppc64-stackmap-nops.ll
ppc64-stackmap.ll
ppc64-toc.ll
ppc64-vaarg-int.ll
ppc64-zext.ll
ppc64le-aggregates.ll
ppc64le-calls.ll
ppc64le-crsave.ll
ppc64le-localentry-large.ll
ppc64le-localentry.ll
ppc64le-smallarg.ll
ppcf128-1-opt.ll
ppcf128-1.ll
ppcf128-2.ll
ppcf128-3.ll
ppcf128-4.ll
ppcf128-endian.ll
ppcf128sf.ll
ppcsoftops.ll
pr12757.ll
pr13641.ll
pr13891.ll
pr15031.ll
pr15359.ll
pr15630.ll
pr15632.ll
pr16556-2.ll
pr16556.ll
pr16573.ll
pr17168.ll
pr17354.ll
pr18663-2.ll
pr18663.ll
pr20442.ll
pr22711.ll
pr24216.ll
pr24546.ll
pr24636.ll
pr25157-peephole.ll
pr25157.ll
pr26180.ll
pr26193.ll
pr26356.ll
pr26378.ll
pr26381.ll
pr26617.ll
pr26690.ll
pr27078.ll
pr27350.ll
pr28130.ll
pr28630.ll
pr30451.ll
pr30640.ll
pr30663.ll
pr30715.ll
pr31144.ll
pr32063.ll
pr32140.ll
pr33093.ll
pr35402.ll
pr35688.ll
pr36292.ll
pr3711_widen_bit.ll
preemption.ll
preinc-ld-sel-crash.ll
preincprep-invoke.ll
preincprep-nontrans-crash.ll
private.ll
pwr3-6x.ll
pwr7-gt-nop.ll
pzero-fp-xored.ll
qpx-bv-sint.ll
qpx-bv.ll
qpx-func-clobber.ll
qpx-load-splat.ll
qpx-load.ll
qpx-recipest.ll
qpx-rounding-ops.ll
qpx-s-load.ll
qpx-s-sel.ll
qpx-s-store.ll
qpx-sel.ll
qpx-split-vsetcc.ll
qpx-store.ll
qpx-unal-cons-lds.ll
qpx-unalperm.ll
quadint-return.ll
r31.ll
recipest.ll
reg-coalesce-simple.ll
reg-names.ll
reloc-align.ll
remap-crash.ll
remat-imm.ll
remove-redundant-moves.ll
remove-redundant-toc-saves.ll
resolvefi-basereg.ll
resolvefi-disp.ll
restore-r30.ll
retaddr.ll
retaddr2.ll
return-val-i128.ll
rlwimi-and-or-bits.ll
rlwimi-and.ll
rlwimi-commute.ll
rlwimi-dyn-and.ll
rlwimi-keep-rsh.ll
rlwimi.ll
rlwimi2.ll
rlwimi3.ll
rlwinm-zero-ext.ll
rlwinm.ll
rlwinm2.ll
rm-zext.ll
rotl-2.ll
rotl-64.ll
rotl-rotr-crash.ll
rotl.ll
rounding-ops.ll
rs-undef-use.ll
s000-alias-misched.ll
save-bp.ll
save-cr-ppc32svr4.ll
save-crbp-ppc32svr4.ll
scavenging.mir
sdag-ppcf128.ll
sdiv-pow2.ll
sections.ll
select-addrRegRegOnly.ll
select-cc.ll
select-i1-vs-i1.ll
select_const.ll
select_lt0.ll
selectiondag-extload-computeknownbits.ll
selectiondag-sextload.ll
set0-v8i16.ll
setcc-logic.ll
setcc-to-sub.ll
setcc_no_zext.ll
setcclike-or-comb.ll
seteq-0.ll
shift-cmp.ll
shift128.ll
shift_mask.ll
shl_elim.ll
shl_sext.ll
sign_ext_inreg1.ll
simplifyConstCmpToISEL.ll
sj-ctr-loop.ll
sjlj.ll
sjlj_no0x.ll
small-arguments.ll
spill-nor0.ll
splat-bug.ll
splat-larger-types-as-v16i8.ll
split-index-tc.ll
srl-mask.ll
stack-no-redzone.ll
stack-protector.ll
stack-realign.ll
stackmap-frame-setup.ll
stacksize.ll
std-unal-fi.ll
stdux-constuse.ll
stfiwx-2.ll
stfiwx.ll
store-constant.ll
store-load-fwd.ll
store-update.ll
structsinmem.ll
structsinregs.ll
stubs.ll
stwu-gta.ll
stwu8.ll
stwux.ll
sub-bv-types.ll
subc.ll
subreg-postra-2.ll
subreg-postra.ll
subtract_from_imm.ll
svr4-redzone.ll
swaps-le-1.ll
swaps-le-2.ll
swaps-le-3.ll
swaps-le-4.ll
swaps-le-5.ll
swaps-le-6.ll
swaps-le-7.ll
tail-dup-analyzable-fallthrough.ll
tail-dup-branch-to-fallthrough.ll
tail-dup-break-cfg.ll
tail-dup-layout.ll
tailcall-string-rvo.ll
tailcall1-64.ll
tailcall1.ll
tailcallpic1.ll
testBitReverse.ll
testComparesi32gtu.ll
testComparesi32leu.ll
testComparesi32ltu.ll
testComparesieqsc.ll
testComparesieqsi.ll
testComparesieqsll.ll
testComparesieqss.ll
testComparesiequc.ll
testComparesiequi.ll
testComparesiequll.ll
testComparesiequs.ll
testComparesigesc.ll
testComparesigesi.ll
testComparesigesll.ll
testComparesigess.ll
testComparesigeuc.ll
testComparesigeui.ll
testComparesigeull.ll
testComparesigeus.ll
testComparesigtsc.ll
testComparesigtsi.ll
testComparesigtsll.ll
testComparesigtss.ll
testComparesigtuc.ll
testComparesigtui.ll
testComparesigtus.ll
testComparesilesc.ll
testComparesilesi.ll
testComparesilesll.ll
testComparesiless.ll
testComparesileuc.ll
testComparesileui.ll
testComparesileull.ll
testComparesileus.ll
testComparesiltsc.ll
testComparesiltsi.ll
testComparesiltsll.ll
testComparesiltss.ll
testComparesiltuc.ll
testComparesiltui.ll
testComparesiltus.ll
testComparesinesc.ll
testComparesinesi.ll
testComparesinesll.ll
testComparesiness.ll
testComparesineuc.ll
testComparesineui.ll
testComparesineull.ll
testComparesineus.ll
testCompareslleqsc.ll
testCompareslleqsi.ll
testCompareslleqsll.ll
testCompareslleqss.ll
testComparesllequc.ll
testComparesllequi.ll
testComparesllequll.ll
testComparesllequs.ll
testComparesllgesc.ll
testComparesllgesi.ll
testComparesllgesll.ll
testComparesllgess.ll
testComparesllgeuc.ll
testComparesllgeui.ll
testComparesllgeull.ll
testComparesllgeus.ll
testComparesllgtsll.ll
testComparesllgtuc.ll
testComparesllgtui.ll
testComparesllgtus.ll
testCompareslllesc.ll
testCompareslllesi.ll
testCompareslllesll.ll
testComparesllless.ll
testComparesllleuc.ll
testComparesllleui.ll
testComparesllleull.ll
testComparesllleus.ll
testComparesllltsll.ll
testComparesllltuc.ll
testComparesllltui.ll
testComparesllltus.ll
testComparesllnesll.ll
testComparesllneull.ll
thread-pointer.ll
tls-cse.ll
tls-pic.ll
tls-store2.ll
tls.ll
tls_get_addr_clobbers.ll
tls_get_addr_fence1.mir
tls_get_addr_fence2.mir
tls_get_addr_stackframe.ll
toc-load-sched-bug.ll
trampoline.ll
uint-to-ppcfp128-crash.ll
unal-altivec-wint.ll
unal-altivec.ll
unal-altivec2.ll
unal-vec-ldst.ll
unal-vec-negarith.ll
unal4-std.ll
unaligned.ll
unsafe-math.ll
unwind-dw2-g.ll
unwind-dw2.ll
vaddsplat.ll
varargs-struct-float.ll
varargs.ll
variable_elem_vec_extracts.ll
vcmp-fold.ll
vec-abi-align.ll
vec-asm-disabled.ll
vec_abs.ll
vec_absd.ll
vec_add_sub_doubleword.ll
vec_add_sub_quadword.ll
vec_auto_constant.ll
vec_br_cmp.ll
vec_buildvector_loadstore.ll
vec_call.ll
vec_clz.ll
vec_cmp.ll
vec_cmpd.ll
vec_constants.ll
vec_conv.ll
vec_extload.ll
vec_extract_p9.ll
vec_extract_p9_2.ll
vec_fmuladd.ll
vec_fneg.ll
vec_insert.ll
vec_int_ext.ll
vec_mergeow.ll
vec_minmax.ll
vec_misaligned.ll
vec_mul.ll
vec_mul_even_odd.ll
vec_perf_shuffle.ll
vec_popcnt.ll
vec_revb.ll
vec_rotate_shift.ll
vec_rounding.ll
vec_select.ll
vec_shift.ll
vec_shuffle.ll
vec_shuffle_le.ll
vec_shuffle_p8vector.ll
vec_shuffle_p8vector_le.ll
vec_sldwi.ll
vec_splat.ll
vec_splat_constant.ll
vec_sqrt.ll
vec_urem_const.ll
vec_veqv_vnand_vorc.ll
vec_vrsave.ll
vec_xxpermdi.ll
vec_zero.ll
vector-identity-shuffle.ll
vector-merge-store-fp-constants.ll
vector.ll
vperm-instcombine.ll
vperm-lowering.ll
vrsave-spill.ll
vrspill.ll
vsel-prom.ll
vselect-constants.ll
vsx-args.ll
vsx-div.ll
vsx-elementary-arith.ll
vsx-fma-m.ll
vsx-fma-mutate-trivial-copy.ll
vsx-fma-mutate-undef.ll
vsx-fma-sp.ll
vsx-infl-copy1.ll
vsx-infl-copy2.ll
vsx-ldst-builtin-le.ll
vsx-ldst.ll
vsx-minmax.ll
vsx-p8.ll
vsx-p9.ll
vsx-partword-int-loads-and-stores.ll
vsx-recip-est.ll
vsx-self-copy.ll
vsx-spill-norwstore.ll
vsx-spill.ll
vsx-vec-spill.ll
vsx-word-splats.ll
vsx.ll
vsxD-Form-spills.ll
vsx_insert_extract_le.ll
vsx_scalar_ld_st.ll
vsx_shuffle_le.ll
vtable-reloc.ll
weak_def_can_be_hidden.ll
xray-attribute-instrumentation.ll
xray-conditional-return.ll
xray-ret-is-terminator.ll
xray-tail-call-hidden.ll
xray-tail-call-sled.ll
xvcmpeqdp-v2f64.ll
xxleqv_xxlnand_xxlorc.ll
zero-not-run.ll
zext-and-cmp.ll
zext-bitperm.ll
zext-free.ll
RISCV
SPARC
SystemZ
Thumb
Thumb2
WebAssembly
WinEH
X86
XCore
DebugInfo
Examples
ExecutionEngine
Feature
FileCheck
Instrumentation
Integer
JitListener
LTO
Linker
MC
Object
ObjectYAML
Other
SafepointIRVerifier
SymbolRewriter
TableGen
ThinLTO
Transforms
Unit
Verifier
YAMLParser
tools
.clang-format
CMakeLists.txt
TestRunner.sh
lit.cfg.py
lit.site.cfg.py.in
tools
unittests
utils
.arcconfig
.clang-format
.clang-tidy
.gitattributes
.gitignore
CMakeLists.txt
CODE_OWNERS.TXT
CREDITS.TXT
LICENSE.TXT
LLVMBuild.txt
README.txt
RELEASE_TESTERS.TXT
configure
llvm.spec.in
openmp
polly
nuget-buildtasks
nunit-lite
roslyn-binaries
rx
xunit-binaries
how-to-bump-roslyn-binaries.md
ikvm-native
llvm
m4
man
mcs
mk
mono
msvc
netcore
po
runtime
samples
scripts
support
tools
COPYING.LIB
LICENSE
Makefile.am
Makefile.in
NEWS
README.md
acinclude.m4
aclocal.m4
autogen.sh
code_of_conduct.md
compile
config.guess
config.h.in
config.rpath
config.sub
configure.REMOVED.git-id
configure.ac.REMOVED.git-id
depcomp
install-sh
ltmain.sh.REMOVED.git-id
missing
mkinstalldirs
mono-uninstalled.pc.in
test-driver
winconfig.h
linux-packaging-mono/external/llvm-project/llvm/test/CodeGen/PowerPC/vec_shuffle_le.ll

210 lines
8.4 KiB
LLVM
Raw Normal View History

; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu -mattr=+altivec -mattr=-vsx -mcpu=pwr7 | FileCheck %s
define void @VPKUHUM_xy(<16 x i8>* %A, <16 x i8>* %B) {
entry:
; CHECK: VPKUHUM_xy:
%tmp = load <16 x i8>, <16 x i8>* %A
%tmp2 = load <16 x i8>, <16 x i8>* %B
%tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
; CHECK: lvx [[REG1:[0-9]+]]
; CHECK: lvx [[REG2:[0-9]+]]
; CHECK: vpkuhum [[REG3:[0-9]+]], [[REG2]], [[REG1]]
store <16 x i8> %tmp3, <16 x i8>* %A
ret void
}
define void @VPKUHUM_xx(<16 x i8>* %A) {
entry:
; CHECK: VPKUHUM_xx:
%tmp = load <16 x i8>, <16 x i8>* %A
%tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
; CHECK: vpkuhum
store <16 x i8> %tmp2, <16 x i8>* %A
ret void
}
define void @VPKUWUM_xy(<16 x i8>* %A, <16 x i8>* %B) {
entry:
; CHECK: VPKUWUM_xy:
%tmp = load <16 x i8>, <16 x i8>* %A
%tmp2 = load <16 x i8>, <16 x i8>* %B
%tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 1, i32 4, i32 5, i32 8, i32 9, i32 12, i32 13, i32 16, i32 17, i32 20, i32 21, i32 24, i32 25, i32 28, i32 29>
; CHECK: lvx [[REG1:[0-9]+]]
; CHECK: lvx [[REG2:[0-9]+]]
; CHECK: vpkuwum [[REG3:[0-9]+]], [[REG2]], [[REG1]]
store <16 x i8> %tmp3, <16 x i8>* %A
ret void
}
define void @VPKUWUM_xx(<16 x i8>* %A) {
entry:
; CHECK: VPKUWUM_xx:
%tmp = load <16 x i8>, <16 x i8>* %A
%tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 0, i32 1, i32 4, i32 5, i32 8, i32 9, i32 12, i32 13, i32 0, i32 1, i32 4, i32 5, i32 8, i32 9, i32 12, i32 13>
; CHECK: vpkuwum
store <16 x i8> %tmp2, <16 x i8>* %A
ret void
}
define void @VMRGLB_xy(<16 x i8>* %A, <16 x i8>* %B) {
entry:
; CHECK: VMRGLB_xy:
%tmp = load <16 x i8>, <16 x i8>* %A
%tmp2 = load <16 x i8>, <16 x i8>* %B
%tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 16, i32 1, i32 17, i32 2, i32 18, i32 3, i32 19, i32 4, i32 20, i32 5, i32 21, i32 6, i32 22, i32 7, i32 23>
; CHECK: lvx [[REG1:[0-9]+]]
; CHECK: lvx [[REG2:[0-9]+]]
; CHECK: vmrglb [[REG3:[0-9]+]], [[REG2]], [[REG1]]
store <16 x i8> %tmp3, <16 x i8>* %A
ret void
}
define void @VMRGLB_xx(<16 x i8>* %A) {
entry:
; CHECK: VMRGLB_xx:
%tmp = load <16 x i8>, <16 x i8>* %A
%tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 0, i32 0, i32 1, i32 1, i32 2, i32 2, i32 3, i32 3, i32 4, i32 4, i32 5, i32 5, i32 6, i32 6, i32 7, i32 7>
; CHECK: vmrglb
store <16 x i8> %tmp2, <16 x i8>* %A
ret void
}
define void @VMRGHB_xy(<16 x i8>* %A, <16 x i8>* %B) {
entry:
; CHECK: VMRGHB_xy:
%tmp = load <16 x i8>, <16 x i8>* %A
%tmp2 = load <16 x i8>, <16 x i8>* %B
%tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 8, i32 24, i32 9, i32 25, i32 10, i32 26, i32 11, i32 27, i32 12, i32 28, i32 13, i32 29, i32 14, i32 30, i32 15, i32 31>
; CHECK: lvx [[REG1:[0-9]+]]
; CHECK: lvx [[REG2:[0-9]+]]
; CHECK: vmrghb [[REG3:[0-9]+]], [[REG2]], [[REG1]]
store <16 x i8> %tmp3, <16 x i8>* %A
ret void
}
define void @VMRGHB_xx(<16 x i8>* %A) {
entry:
; CHECK: VMRGHB_xx:
%tmp = load <16 x i8>, <16 x i8>* %A
%tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 8, i32 8, i32 9, i32 9, i32 10, i32 10, i32 11, i32 11, i32 12, i32 12, i32 13, i32 13, i32 14, i32 14, i32 15, i32 15>
; CHECK: vmrghb
store <16 x i8> %tmp2, <16 x i8>* %A
ret void
}
define void @VMRGLH_xy(<16 x i8>* %A, <16 x i8>* %B) {
entry:
; CHECK: VMRGLH_xy:
%tmp = load <16 x i8>, <16 x i8>* %A
%tmp2 = load <16 x i8>, <16 x i8>* %B
%tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 1, i32 16, i32 17, i32 2, i32 3, i32 18, i32 19, i32 4, i32 5, i32 20, i32 21, i32 6, i32 7, i32 22, i32 23>
; CHECK: lvx [[REG1:[0-9]+]]
; CHECK: lvx [[REG2:[0-9]+]]
; CHECK: vmrglh [[REG3:[0-9]+]], [[REG2]], [[REG1]]
store <16 x i8> %tmp3, <16 x i8>* %A
ret void
}
define void @VMRGLH_xx(<16 x i8>* %A) {
entry:
; CHECK: VMRGLH_xx:
%tmp = load <16 x i8>, <16 x i8>* %A
%tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 0, i32 1, i32 0, i32 1, i32 2, i32 3, i32 2, i32 3, i32 4, i32 5, i32 4, i32 5, i32 6, i32 7, i32 6, i32 7>
; CHECK: vmrglh
store <16 x i8> %tmp2, <16 x i8>* %A
ret void
}
define void @VMRGHH_xy(<16 x i8>* %A, <16 x i8>* %B) {
entry:
; CHECK: VMRGHH_xy:
%tmp = load <16 x i8>, <16 x i8>* %A
%tmp2 = load <16 x i8>, <16 x i8>* %B
%tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 8, i32 9, i32 24, i32 25, i32 10, i32 11, i32 26, i32 27, i32 12, i32 13, i32 28, i32 29, i32 14, i32 15, i32 30, i32 31>
; CHECK: lvx [[REG1:[0-9]+]]
; CHECK: lvx [[REG2:[0-9]+]]
; CHECK: vmrghh [[REG3:[0-9]+]], [[REG2]], [[REG1]]
store <16 x i8> %tmp3, <16 x i8>* %A
ret void
}
define void @VMRGHH_xx(<16 x i8>* %A) {
entry:
; CHECK: VMRGHH_xx:
%tmp = load <16 x i8>, <16 x i8>* %A
%tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 8, i32 9, i32 8, i32 9, i32 10, i32 11, i32 10, i32 11, i32 12, i32 13, i32 12, i32 13, i32 14, i32 15, i32 14, i32 15>
; CHECK: vmrghh
store <16 x i8> %tmp2, <16 x i8>* %A
ret void
}
define void @VMRGLW_xy(<16 x i8>* %A, <16 x i8>* %B) {
entry:
; CHECK: VMRGLW_xy:
%tmp = load <16 x i8>, <16 x i8>* %A
%tmp2 = load <16 x i8>, <16 x i8>* %B
%tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 16, i32 17, i32 18, i32 19, i32 4, i32 5, i32 6, i32 7, i32 20, i32 21, i32 22, i32 23>
; CHECK: lvx [[REG1:[0-9]+]]
; CHECK: lvx [[REG2:[0-9]+]]
; CHECK: vmrglw [[REG3:[0-9]+]], [[REG2]], [[REG1]]
store <16 x i8> %tmp3, <16 x i8>* %A
ret void
}
define void @VMRGLW_xx(<16 x i8>* %A) {
entry:
; CHECK: VMRGLW_xx:
%tmp = load <16 x i8>, <16 x i8>* %A
%tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7>
; CHECK: vmrglw
store <16 x i8> %tmp2, <16 x i8>* %A
ret void
}
define void @VMRGHW_xy(<16 x i8>* %A, <16 x i8>* %B) {
entry:
; CHECK: VMRGHW_xy:
%tmp = load <16 x i8>, <16 x i8>* %A
%tmp2 = load <16 x i8>, <16 x i8>* %B
%tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 24, i32 25, i32 26, i32 27, i32 12, i32 13, i32 14, i32 15, i32 28, i32 29, i32 30, i32 31>
; CHECK: lvx [[REG1:[0-9]+]]
; CHECK: lvx [[REG2:[0-9]+]]
; CHECK: vmrghw [[REG3:[0-9]+]], [[REG2]], [[REG1]]
store <16 x i8> %tmp3, <16 x i8>* %A
ret void
}
define void @VMRGHW_xx(<16 x i8>* %A) {
entry:
; CHECK: VMRGHW_xx:
%tmp = load <16 x i8>, <16 x i8>* %A
%tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 8, i32 9, i32 10, i32 11, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 12, i32 13, i32 14, i32 15>
; CHECK: vmrghw
store <16 x i8> %tmp2, <16 x i8>* %A
ret void
}
define void @VSLDOI_xy(<16 x i8>* %A, <16 x i8>* %B) {
entry:
; CHECK: VSLDOI_xy:
%tmp = load <16 x i8>, <16 x i8>* %A
%tmp2 = load <16 x i8>, <16 x i8>* %B
%tmp3 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp2, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27>
; CHECK: lvx [[REG1:[0-9]+]]
; CHECK: lvx [[REG2:[0-9]+]]
; CHECK: vsldoi [[REG3:[0-9]+]], [[REG2]], [[REG1]], 4
store <16 x i8> %tmp3, <16 x i8>* %A
ret void
}
define void @VSLDOI_xx(<16 x i8>* %A) {
entry:
; CHECK: VSLDOI_xx:
%tmp = load <16 x i8>, <16 x i8>* %A
%tmp2 = shufflevector <16 x i8> %tmp, <16 x i8> %tmp, <16 x i32> <i32 12, i32 13, i32 14, i32 15, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11>
; CHECK: vsldoi {{[0-9]+}}, [[REG1:[0-9]+]], [[REG1]], 4
store <16 x i8> %tmp2, <16 x i8>* %A
ret void
}