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15 lines
453 B
LLVM
15 lines
453 B
LLVM
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; RUN: not llc -march=mipsel -mcpu=mips32r2 -mattr=+fp64 \
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; RUN: -O0 -relocation-model=pic -fast-isel-abort=3 < %s
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; Check that FastISel aborts when we have 64bit FPU registers. FastISel currently
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; supports AFGR64 only, which uses paired 32 bit registers.
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define zeroext i1 @f(double %value) {
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entry:
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; CHECK-LABEL: f:
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; CHECK: sdc1
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%value.addr = alloca double, align 8
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store double %value, double* %value.addr, align 8
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ret i1 false
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}
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