20 lines
671 B
ArmAsm
20 lines
671 B
ArmAsm
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve 2>&1 < %s| FileCheck %s
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// Register z32 does not exist.
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sub z3.h, z26.h, z32.h
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
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// CHECK-NEXT: sub z3.h, z26.h, z32.h
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// Invalid element kind.
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sub z4.h, z27.h, z31.x
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid sve vector kind qualifier
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// CHECK-NEXT: sub z4.h, z27.h, z31.x
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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// Element size specifiers should match.
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sub z0.h, z8.h, z8.b
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// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
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// CHECK-NEXT: sub z0.h, z8.h, z8.b
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// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
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