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			70 lines
		
	
	
		
			2.8 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
|   | //===-- ARMSelectionDAGInfo.h - ARM SelectionDAG Info -----------*- C++ -*-===//
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|  | //
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|  | //                     The LLVM Compiler Infrastructure
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|  | //
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|  | // This file is distributed under the University of Illinois Open Source
 | ||
|  | // License. See LICENSE.TXT for details.
 | ||
|  | //
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|  | //===----------------------------------------------------------------------===//
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|  | //
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|  | // This file defines the ARM subclass for SelectionDAGTargetInfo.
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|  | //
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|  | //===----------------------------------------------------------------------===//
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|  | 
 | ||
|  | #ifndef LLVM_LIB_TARGET_ARM_ARMSELECTIONDAGINFO_H
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|  | #define LLVM_LIB_TARGET_ARM_ARMSELECTIONDAGINFO_H
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|  | 
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|  | #include "MCTargetDesc/ARMAddressingModes.h"
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|  | #include "llvm/CodeGen/RuntimeLibcalls.h"
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|  | #include "llvm/CodeGen/SelectionDAGTargetInfo.h"
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|  | 
 | ||
|  | namespace llvm { | ||
|  | 
 | ||
|  | namespace ARM_AM { | ||
|  |   static inline ShiftOpc getShiftOpcForNode(unsigned Opcode) { | ||
|  |     switch (Opcode) { | ||
|  |     default:          return ARM_AM::no_shift; | ||
|  |     case ISD::SHL:    return ARM_AM::lsl; | ||
|  |     case ISD::SRL:    return ARM_AM::lsr; | ||
|  |     case ISD::SRA:    return ARM_AM::asr; | ||
|  |     case ISD::ROTR:   return ARM_AM::ror; | ||
|  |     //case ISD::ROTL:  // Only if imm -> turn into ROTR.
 | ||
|  |     // Can't handle RRX here, because it would require folding a flag into
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|  |     // the addressing mode.  :(  This causes us to miss certain things.
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|  |     //case ARMISD::RRX: return ARM_AM::rrx;
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|  |     } | ||
|  |   } | ||
|  | }  // end namespace ARM_AM
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|  | 
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|  | class ARMSelectionDAGInfo : public SelectionDAGTargetInfo { | ||
|  | public: | ||
|  |   SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl, | ||
|  |                                   SDValue Chain, SDValue Dst, SDValue Src, | ||
|  |                                   SDValue Size, unsigned Align, bool isVolatile, | ||
|  |                                   bool AlwaysInline, | ||
|  |                                   MachinePointerInfo DstPtrInfo, | ||
|  |                                   MachinePointerInfo SrcPtrInfo) const override; | ||
|  | 
 | ||
|  |   SDValue | ||
|  |   EmitTargetCodeForMemmove(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, | ||
|  |                            SDValue Dst, SDValue Src, SDValue Size, | ||
|  |                            unsigned Align, bool isVolatile, | ||
|  |                            MachinePointerInfo DstPtrInfo, | ||
|  |                            MachinePointerInfo SrcPtrInfo) const override; | ||
|  | 
 | ||
|  |   // Adjust parameters for memset, see RTABI section 4.3.4
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|  |   SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, const SDLoc &dl, | ||
|  |                                   SDValue Chain, SDValue Op1, SDValue Op2, | ||
|  |                                   SDValue Op3, unsigned Align, bool isVolatile, | ||
|  |                                   MachinePointerInfo DstPtrInfo) const override; | ||
|  | 
 | ||
|  |   SDValue EmitSpecializedLibcall(SelectionDAG &DAG, const SDLoc &dl, | ||
|  |                                  SDValue Chain, SDValue Dst, SDValue Src, | ||
|  |                                  SDValue Size, unsigned Align, | ||
|  |                                  RTLIB::Libcall LC) const; | ||
|  | }; | ||
|  | 
 | ||
|  | } | ||
|  | 
 | ||
|  | #endif
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