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52 lines
2.9 KiB
LLVM
52 lines
2.9 KiB
LLVM
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; RUN: llc -march=hexagon -O2 -mcpu=hexagonv60 < %s | FileCheck %s
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; CHECK: q{{[0-3]}} = v{{[0-9]*}}and(v{{[0-9]*}},r{{[0-9]*}})
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target datalayout = "e-m:e-p:32:32:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f64:64:64-f32:32:32-v64:64:64-v32:32:32-a:0-n16:32"
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target triple = "hexagon"
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@K = global i64 0, align 8
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@src = global i8 -1, align 1
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@vecpreds = common global [15 x <16 x i32>] zeroinitializer, align 64
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@Q6VecPredResult = common global <16 x i32> zeroinitializer, align 64
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@vectors = common global [15 x <16 x i32>] zeroinitializer, align 64
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@VectorResult = common global <16 x i32> zeroinitializer, align 64
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@vector_pairs = common global [15 x <32 x i32>] zeroinitializer, align 128
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@VectorPairResult = common global <32 x i32> zeroinitializer, align 128
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@dst_addresses = common global [15 x i8] zeroinitializer, align 8
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@ptr_addresses = common global [15 x i8*] zeroinitializer, align 8
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@src_addresses = common global [15 x i8*] zeroinitializer, align 8
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@dst = common global i8 0, align 1
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@ptr = common global [32768 x i8] zeroinitializer, align 8
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; Function Attrs: nounwind
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define i32 @main() #0 {
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entry:
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%retval = alloca i32, align 4
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store i32 0, i32* %retval, align 4
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%0 = load volatile <16 x i32>, <16 x i32>* getelementptr inbounds ([15 x <16 x i32>], [15 x <16 x i32>]* @vecpreds, i32 0, i32 0), align 64
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%1 = bitcast <16 x i32> %0 to <512 x i1>
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%2 = load volatile <16 x i32>, <16 x i32>* getelementptr inbounds ([15 x <16 x i32>], [15 x <16 x i32>]* @vecpreds, i32 0, i32 1), align 64
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%3 = bitcast <16 x i32> %2 to <512 x i1>
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%4 = call <512 x i1> @llvm.hexagon.V6.pred.and(<512 x i1> %1, <512 x i1> %3)
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%5 = bitcast <512 x i1> %4 to <16 x i32>
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store volatile <16 x i32> %5, <16 x i32>* @Q6VecPredResult, align 64
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%6 = load volatile <16 x i32>, <16 x i32>* getelementptr inbounds ([15 x <16 x i32>], [15 x <16 x i32>]* @vecpreds, i32 0, i32 0), align 64
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%7 = bitcast <16 x i32> %6 to <512 x i1>
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%8 = load volatile <16 x i32>, <16 x i32>* getelementptr inbounds ([15 x <16 x i32>], [15 x <16 x i32>]* @vecpreds, i32 0, i32 1), align 64
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%9 = bitcast <16 x i32> %8 to <512 x i1>
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%10 = call <512 x i1> @llvm.hexagon.V6.pred.and.n(<512 x i1> %7, <512 x i1> %9)
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%11 = bitcast <512 x i1> %10 to <16 x i32>
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store volatile <16 x i32> %11, <16 x i32>* @Q6VecPredResult, align 64
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ret i32 0
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}
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; Function Attrs: nounwind readnone
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declare <512 x i1> @llvm.hexagon.V6.pred.and(<512 x i1>, <512 x i1>) #1
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; Function Attrs: nounwind readnone
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declare <512 x i1> @llvm.hexagon.V6.pred.and.n(<512 x i1>, <512 x i1>) #1
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attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" "unsafe-fp-math"="false" "use-soft-float"="false" }
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attributes #1 = { nounwind readnone }
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