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Analysis
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AArch64
AMDGPU
GlobalISel
32-bit-local-address-space.ll
InlineAsmCrash.ll
README
add-debug.ll
add.i16.ll
add.ll
add.v2i16.ll
add_i128.ll
add_i64.ll
addrspacecast-captured.ll
addrspacecast-constantexpr.ll
addrspacecast.ll
adjust-writemask-invalid-copy.ll
alignbit-pat.ll
always-uniform.ll
amdgcn.bitcast.ll
amdgcn.private-memory.ll
amdgpu-alias-analysis.ll
amdgpu-codegenprepare-fdiv.ll
amdgpu-codegenprepare-i16-to-i32.ll
amdgpu-inline.ll
amdgpu-shader-calling-convention.ll
amdgpu.private-memory.ll
amdgpu.work-item-intrinsics.deprecated.ll
amdpal-cs.ll
amdpal-es.ll
amdpal-gs.ll
amdpal-hs.ll
amdpal-ls.ll
amdpal-ps.ll
amdpal-psenable.ll
amdpal-vs.ll
amdpal.ll
and-gcn.ll
and.ll
annotate-kernel-features-hsa-call.ll
annotate-kernel-features-hsa.ll
annotate-kernel-features.ll
anonymous-gv.ll
any_extend_vector_inreg.ll
anyext.ll
array-ptr-calc-i32.ll
array-ptr-calc-i64.ll
ashr.v2i16.ll
atomic_cmp_swap_local.ll
atomic_load_add.ll
atomic_load_sub.ll
attr-amdgpu-flat-work-group-size.ll
attr-amdgpu-num-sgpr.ll
attr-amdgpu-num-vgpr.ll
attr-amdgpu-waves-per-eu.ll
attr-unparseable.ll
barrier-elimination.ll
basic-branch.ll
basic-call-return.ll
basic-loop.ll
bfe-combine.ll
bfe-patterns.ll
bfe_uint.ll
bfi_int.ll
bfm.ll
big_alu.ll
bitcast-vector-extract.ll
bitreverse-inline-immediates.ll
bitreverse.ll
br_cc.f16.ll
branch-condition-and.ll
branch-relax-bundle.ll
branch-relax-spill.ll
branch-relaxation.ll
branch-uniformity.ll
break-smem-soft-clauses.mir
break-vmem-soft-clauses.mir
bswap.ll
bug-vopc-commute.ll
build_vector.ll
byval-frame-setup.ll
call-argument-types.ll
call-encoding.ll
call-graph-register-usage.ll
call-preserved-registers.ll
call-return-types.ll
call_fs.ll
callee-frame-setup.ll
callee-special-input-sgprs.ll
callee-special-input-vgprs.ll
calling-conventions.ll
captured-frame-index.ll
cayman-loop-bug.ll
cf-loop-on-constant.ll
cf-stack-bug.ll
cf_end.ll
cgp-addressing-modes-flat.ll
cgp-addressing-modes.ll
cgp-bitfield-extract.ll
clamp-modifier.ll
clamp-omod-special-case.mir
clamp.ll
cluster-flat-loads-postra.mir
cluster-flat-loads.mir
cndmask-no-def-vcc.ll
coalescer-subrange-crash.ll
coalescer-subreg-join.mir
coalescer_distribute.ll
coalescer_remat.ll
codegen-prepare-addrmode-sext.ll
collapse-endcf.ll
combine-and-sext-bool.ll
combine-cond-add-sub.ll
combine-ftrunc.ll
combine_vloads.ll
commute-compares.ll
commute-shifts.ll
commute_modifiers.ll
complex-folding.ll
concat_vectors.ll
constant-fold-imm-immreg.mir
constant-fold-mi-operands.ll
control-flow-fastregalloc.ll
control-flow-optnone.ll
convergent-inlineasm.ll
copy-illegal-type.ll
copy-to-reg.ll
ctlz.ll
ctlz_zero_undef.ll
ctpop.ll
ctpop16.ll
ctpop64.ll
cttz_zero_undef.ll
cube.ll
cvt_f32_ubyte.ll
cvt_flr_i32_f32.ll
cvt_rpi_i32_f32.ll
dagcomb-shuffle-vecextend-non2.ll
dagcombine-reassociate-bug.ll
dagcombiner-bug-illegal-vec4-int-to-fp.ll
dead_copy.mir
debug-value.ll
debug.ll
debugger-emit-prologue.ll
debugger-insert-nops.ll
debugger-reserve-regs.ll
default-fp-mode.ll
detect-dead-lanes.mir
disconnected-predset-break-bug.ll
drop-mem-operand-move-smrd.ll
ds-combine-large-stride.ll
ds-negative-offset-addressing-mode-loop.ll
ds-sub-offset.ll
ds_read2.ll
ds_read2_offset_order.ll
ds_read2_superreg.ll
ds_read2st64.ll
ds_write2.ll
ds_write2st64.ll
dynamic_stackalloc.ll
early-if-convert-cost.ll
early-if-convert.ll
early-inline-alias.ll
early-inline.ll
elf-header.ll
elf-notes.ll
elf.ll
elf.r600.ll
else.ll
empty-function.ll
enable-no-signed-zeros-fp-math.ll
endcf-loop-header.ll
endpgm-dce.mir
enqueue-kernel.ll
env-amdgiz.ll
env-amdgizcl.ll
exceed-max-sgprs.ll
extend-bit-ops-i16.ll
extload-align.ll
extload-private.ll
extload.ll
extract-vector-elt-build-vector-combine.ll
extract_vector_elt-f16.ll
extract_vector_elt-f64.ll
extract_vector_elt-i16.ll
extract_vector_elt-i64.ll
extract_vector_elt-i8.ll
extractelt-to-trunc.ll
fabs.f16.ll
fabs.f64.ll
fabs.ll
fadd-fma-fmul-combine.ll
fadd.f16.ll
fadd.ll
fadd64.ll
fcanonicalize-elimination.ll
fcanonicalize.f16.ll
fcanonicalize.ll
fceil.ll
fceil64.ll
fcmp-cnd.ll
fcmp-cnde-int-args.ll
fcmp.f16.ll
fcmp.ll
fcmp64.ll
fconst64.ll
fcopysign.f16.ll
fcopysign.f32.ll
fcopysign.f64.ll
fdiv.f16.ll
fdiv.f64.ll
fdiv.ll
fence-amdgiz.ll
fence-barrier.ll
fetch-limits.r600.ll
fetch-limits.r700+.ll
ffloor.f64.ll
ffloor.ll
fix-vgpr-copies.mir
fix-wwm-liveness.mir
flat-address-space.ll
flat-for-global-subtarget-feature.ll
flat-load-clustering.mir
flat-scratch-reg.ll
flat_atomics.ll
flat_atomics_i64.ll
floor.ll
fma-combine.ll
fma.f64.ll
fma.ll
fmad.ll
fmax.ll
fmax3.f64.ll
fmax3.ll
fmax_legacy.f64.ll
fmax_legacy.ll
fmaxnum.f64.ll
fmaxnum.ll
fmed3.ll
fmin.ll
fmin3.ll
fmin_fmax_legacy.amdgcn.ll
fmin_legacy.f64.ll
fmin_legacy.ll
fminnum.f64.ll
fminnum.ll
fmul-2-combine-multi-use.ll
fmul.f16.ll
fmul.ll
fmul64.ll
fmuladd.f16.ll
fmuladd.f32.ll
fmuladd.f64.ll
fmuladd.v2f16.ll
fnearbyint.ll
fneg-combines.ll.REMOVED.git-id
fneg-fabs.f16.ll
fneg-fabs.f64.ll
fneg-fabs.ll
fneg.f16.ll
fneg.f64.ll
fneg.ll
fold-cndmask.mir
fold-fmul-to-neg-abs.ll
fold-immediate-output-mods.mir
fold-operands-order.mir
fp-classify.ll
fp16_to_fp32.ll
fp16_to_fp64.ll
fp32_to_fp16.ll
fp_to_sint.f64.ll
fp_to_sint.ll
fp_to_uint.f64.ll
fp_to_uint.ll
fpext-free.ll
fpext.f16.ll
fpext.ll
fptosi.f16.ll
fptoui.f16.ll
fptrunc.f16.ll
fptrunc.ll
fract.f64.ll
fract.ll
frame-index-amdgiz.ll
frame-index-elimination.ll
frem.ll
fsqrt.f64.ll
fsqrt.ll
fsub.f16.ll
fsub.ll
fsub64.ll
ftrunc.f64.ll
ftrunc.ll
function-args.ll
function-returns.ll
gep-address-space.ll
global-constant.ll
global-directive.ll
global-extload-i16.ll
global-smrd-unknown.ll
global-variable-relocs.ll
global_atomics.ll
global_atomics_i64.ll
global_smrd.ll
global_smrd_cfg.ll
gv-const-addrspace.ll
gv-offset-folding.ll
half.ll
hazard-inlineasm.mir
hazard.mir
hoist-cond.ll
hsa-default-device.ll
hsa-fp-mode.ll
hsa-func-align.ll
hsa-func.ll
hsa-globals.ll
hsa-group-segment.ll
hsa-metadata-deduce-ro-arg.ll
hsa-metadata-enqueu-kernel.ll
hsa-metadata-from-llvm-ir-full.ll
hsa-metadata-images.ll
hsa-metadata-invalid-ocl-version-1.ll
hsa-metadata-invalid-ocl-version-2.ll
hsa-metadata-invalid-ocl-version-3.ll
hsa-metadata-kernel-code-props.ll
hsa-metadata-kernel-debug-props.ll
hsa-note-no-func.ll
hsa.ll
huge-private-buffer.ll
i1-copy-implicit-def.ll
i1-copy-phi.ll
i8-to-double-to-float.ll
icmp-select-sete-reverse-args.ll
icmp.i16.ll
icmp64.ll
illegal-sgpr-to-vgpr-copy.ll
image-attributes.ll
image-resource-id.ll
imm.ll
imm16.ll
immv216.ll
indirect-addressing-si-noopt.ll
indirect-addressing-si.ll
indirect-private-64.ll
infer-addrpace-pipeline.ll
infinite-loop-evergreen.ll
infinite-loop.ll
inline-asm.ll
inline-attr.ll
inline-calls.ll
inline-constraints.ll
inlineasm-16.ll
inlineasm-illegal-type.ll
inlineasm-packed.ll
input-mods.ll
insert-skips-kill-uncond.mir
insert-waits-callee.mir
insert-waits-exp.mir
insert_subreg.ll
insert_vector_elt.ll
insert_vector_elt.v2i16.ll
inserted-wait-states.mir
internalize.ll
invalid-addrspacecast.ll
invariant-load-no-alias-store.ll
invert-br-undef-vcc.mir
ipra.ll
jump-address.ll
kcache-fold.ll
kernarg-stack-alignment.ll
kernel-args.ll
knownbits-recursion.ll
large-alloca-compute.ll
large-alloca-graphics.ll
large-constant-initializer.ll
large-work-group-promote-alloca.ll
lds-alignment.ll
lds-initializer.ll
lds-m0-init-in-loop.ll
lds-oqap-crash.ll
lds-output-queue.ll
lds-size.ll
lds-zero-initializer.ll
legalizedag-bug-expand-setcc.ll
limit-coalesce.mir
lit.local.cfg
literals.ll
liveness.mir
llvm.AMDGPU.kill.ll
llvm.SI.load.dword.ll
llvm.SI.tbuffer.store.ll
llvm.amdgcn.alignb.ll
llvm.amdgcn.atomic.dec.ll
llvm.amdgcn.atomic.inc.ll
llvm.amdgcn.buffer.atomic.ll
llvm.amdgcn.buffer.load.format.ll
llvm.amdgcn.buffer.load.ll
llvm.amdgcn.buffer.store.format.ll
llvm.amdgcn.buffer.store.ll
llvm.amdgcn.buffer.wbinvl1.ll
llvm.amdgcn.buffer.wbinvl1.sc.ll
llvm.amdgcn.buffer.wbinvl1.vol.ll
llvm.amdgcn.class.f16.ll
llvm.amdgcn.class.ll
llvm.amdgcn.cos.f16.ll
llvm.amdgcn.cos.ll
llvm.amdgcn.cubeid.ll
llvm.amdgcn.cubema.ll
llvm.amdgcn.cubesc.ll
llvm.amdgcn.cubetc.ll
llvm.amdgcn.cvt.pk.i16.ll
llvm.amdgcn.cvt.pk.u16.ll
llvm.amdgcn.cvt.pknorm.i16.ll
llvm.amdgcn.cvt.pknorm.u16.ll
llvm.amdgcn.cvt.pkrtz.ll
llvm.amdgcn.dispatch.id.ll
llvm.amdgcn.dispatch.ptr.ll
llvm.amdgcn.div.fixup.f16.ll
llvm.amdgcn.div.fixup.ll
llvm.amdgcn.div.fmas.ll
llvm.amdgcn.div.scale.ll
llvm.amdgcn.ds.bpermute.ll
llvm.amdgcn.ds.permute.ll
llvm.amdgcn.ds.swizzle.ll
llvm.amdgcn.exp.compr.ll
llvm.amdgcn.exp.ll
llvm.amdgcn.fcmp.ll
llvm.amdgcn.fdiv.fast.ll
llvm.amdgcn.fmed3.f16.ll
llvm.amdgcn.fmed3.ll
llvm.amdgcn.fmul.legacy.ll
llvm.amdgcn.fract.f16.ll
llvm.amdgcn.fract.ll
llvm.amdgcn.frexp.exp.f16.ll
llvm.amdgcn.frexp.exp.ll
llvm.amdgcn.frexp.mant.f16.ll
llvm.amdgcn.frexp.mant.ll
llvm.amdgcn.groupstaticsize.ll
llvm.amdgcn.icmp.ll
llvm.amdgcn.image.atomic.ll
llvm.amdgcn.image.gather4.ll
llvm.amdgcn.image.getlod.ll
llvm.amdgcn.image.ll
llvm.amdgcn.image.sample.ll
llvm.amdgcn.image.sample.o.ll
llvm.amdgcn.implicit.buffer.ptr.hsa.ll
llvm.amdgcn.implicit.buffer.ptr.ll
llvm.amdgcn.implicitarg.ptr.ll
llvm.amdgcn.init.exec.ll
llvm.amdgcn.interp.ll
llvm.amdgcn.kernarg.segment.ptr.ll
llvm.amdgcn.kill.ll
llvm.amdgcn.ldexp.f16.ll
llvm.amdgcn.ldexp.ll
llvm.amdgcn.lerp.ll
llvm.amdgcn.log.clamp.ll
llvm.amdgcn.mbcnt.ll
llvm.amdgcn.mov.dpp.ll
llvm.amdgcn.mqsad.pk.u16.u8.ll
llvm.amdgcn.mqsad.u32.u8.ll
llvm.amdgcn.msad.u8.ll
llvm.amdgcn.ps.live.ll
llvm.amdgcn.qsad.pk.u16.u8.ll
llvm.amdgcn.queue.ptr.ll
llvm.amdgcn.rcp.f16.ll
llvm.amdgcn.rcp.legacy.ll
llvm.amdgcn.rcp.ll
llvm.amdgcn.readfirstlane.ll
llvm.amdgcn.readlane.ll
llvm.amdgcn.rsq.clamp.ll
llvm.amdgcn.rsq.f16.ll
llvm.amdgcn.rsq.legacy.ll
llvm.amdgcn.rsq.ll
llvm.amdgcn.s.barrier.ll
llvm.amdgcn.s.dcache.inv.ll
llvm.amdgcn.s.dcache.inv.vol.ll
llvm.amdgcn.s.dcache.wb.ll
llvm.amdgcn.s.dcache.wb.vol.ll
llvm.amdgcn.s.decperflevel.ll
llvm.amdgcn.s.getpc.ll
llvm.amdgcn.s.getreg.ll
llvm.amdgcn.s.incperflevel.ll
llvm.amdgcn.s.memrealtime.ll
llvm.amdgcn.s.memtime.ll
llvm.amdgcn.s.sleep.ll
llvm.amdgcn.s.waitcnt.ll
llvm.amdgcn.sad.hi.u8.ll
llvm.amdgcn.sad.u16.ll
llvm.amdgcn.sad.u8.ll
llvm.amdgcn.sbfe.ll
llvm.amdgcn.sendmsg.ll
llvm.amdgcn.set.inactive.ll
llvm.amdgcn.sffbh.ll
llvm.amdgcn.sin.f16.ll
llvm.amdgcn.sin.ll
llvm.amdgcn.tbuffer.load.ll
llvm.amdgcn.tbuffer.store.ll
llvm.amdgcn.trig.preop.ll
llvm.amdgcn.ubfe.ll
llvm.amdgcn.unreachable.ll
llvm.amdgcn.update.dpp.ll
llvm.amdgcn.wave.barrier.ll
llvm.amdgcn.workgroup.id.ll
llvm.amdgcn.workitem.id.ll
llvm.amdgcn.wqm.vote.ll
llvm.amdgpu.kilp.ll
llvm.ceil.f16.ll
llvm.cos.f16.ll
llvm.cos.ll
llvm.dbg.value.ll
llvm.exp2.f16.ll
llvm.exp2.ll
llvm.floor.f16.ll
llvm.fma.f16.ll
llvm.fmuladd.f16.ll
llvm.log.f16.ll
llvm.log.ll
llvm.log10.f16.ll
llvm.log10.ll
llvm.log2.f16.ll
llvm.log2.ll
llvm.maxnum.f16.ll
llvm.memcpy.ll
llvm.minnum.f16.ll
llvm.pow.ll
llvm.r600.cube.ll
llvm.r600.dot4.ll
llvm.r600.group.barrier.ll
llvm.r600.read.local.size.ll
llvm.r600.recipsqrt.clamped.ll
llvm.r600.recipsqrt.ieee.ll
llvm.r600.tex.ll
llvm.rint.f16.ll
llvm.rint.f64.ll
llvm.rint.ll
llvm.round.f64.ll
llvm.round.ll
llvm.sin.f16.ll
llvm.sin.ll
llvm.sqrt.f16.ll
llvm.trunc.f16.ll
load-constant-f64.ll
load-constant-i1.ll
load-constant-i16.ll
load-constant-i32.ll
load-constant-i64.ll
load-constant-i8.ll
load-global-f32.ll
load-global-f64.ll
load-global-i1.ll
load-global-i16.ll
load-global-i32.ll
load-global-i64.ll
load-global-i8.ll
load-hi16.ll
load-input-fold.ll
load-lo16.ll
load-local-f32.ll
load-local-f64.ll
load-local-i1.ll
load-local-i16.ll
load-local-i32.ll
load-local-i64.ll
load-local-i8.ll
load-private-double16-amdgiz.ll
load-weird-sizes.ll
local-64.ll
local-atomics.ll
local-atomics64.ll
local-memory.amdgcn.ll
local-memory.ll
local-memory.r600.ll
local-stack-slot-offset.ll
loop-address.ll
loop-idiom.ll
loop_break.ll
lower-mem-intrinsics.ll
lower-range-metadata-intrinsic-call.ll
lshl64-to-32.ll
lshr.v2i16.ll
macro-fusion-cluster-vcc-uses.mir
mad-combine.ll
mad-mix-hi.ll
mad-mix-lo.ll
mad-mix.ll
mad24-get-global-id.ll
mad_64_32.ll
mad_int24.ll
mad_uint24.ll
madak.ll
madmk.ll
max-literals.ll
max.i16.ll
max.ll
max3.ll
mem-builtins.ll
memory-legalizer-atomic-cmpxchg.ll
memory-legalizer-atomic-fence.ll
memory-legalizer-atomic-rmw.ll
memory-legalizer-invalid-syncscope.ll
memory-legalizer-load.ll
memory-legalizer-store-infinite-loop.ll
memory-legalizer-store.ll
merge-load-store.mir
merge-m0.mir
merge-store-crash.ll
merge-store-usedef.ll
merge-stores.ll
mesa_regression.ll
min.ll
min3.ll
misched-killflags.mir
missing-store.ll
move-addr64-rsrc-dead-subreg-writes.ll
move-to-valu-atomicrmw.ll
move-to-valu-worklist.ll
movreld-bug.ll
movrels-bug.mir
mubuf-offset-private.ll
mubuf-shader-vgpr.ll
mubuf.ll
mul.ll
mul_int24.ll
mul_uint24-amdgcn.ll
mul_uint24-r600.ll
multi-divergent-exit-region.ll
multilevel-break.ll
nested-calls.ll
nested-loop-conditions.ll
no-hsa-graphics-shaders.ll
no-initializer-constant-addrspace.ll
no-shrink-extloads.ll
nop-data.ll
not-scalarize-volatile-load.ll
nullptr.ll
omod.ll
opencl-image-metadata.ll
operand-folding.ll
operand-spacing.ll
opt-sgpr-to-vgpr-copy.mir
optimize-if-exec-masking.mir
or.ll
over-max-lds-size.ll
pack.v2f16.ll
pack.v2i16.ll
packed-op-sel.ll
packetizer.ll
parallelandifcollapse.ll
parallelorifcollapse.ll
partial-sgpr-to-vgpr-spills.ll
partially-dead-super-register-immediate.ll
predicate-dp4.ll
predicates.ll
private-access-no-objects.ll
private-element-size.ll
private-memory-atomics.ll
private-memory-r600.ll
promote-alloca-addrspacecast.ll
promote-alloca-array-aggregate.ll
promote-alloca-array-allocation.ll
promote-alloca-bitcast-function.ll
promote-alloca-calling-conv.ll
promote-alloca-globals.ll
promote-alloca-invariant-markers.ll
promote-alloca-lifetime.ll
promote-alloca-mem-intrinsics.ll
promote-alloca-no-opts.ll
promote-alloca-padding-size-estimate.ll
promote-alloca-stored-pointer-value.ll
promote-alloca-to-lds-icmp.ll
promote-alloca-to-lds-phi.ll
promote-alloca-to-lds-select.ll
promote-alloca-unhandled-intrinsic.ll
promote-alloca-volatile.ll
pv-packing.ll
pv.ll
r600-constant-array-fixup.ll
r600-encoding.ll
r600-export-fix.ll
r600-infinite-loop-bug-while-reorganizing-vector.ll
r600-legalize-umax-bug.ll
r600.alu-limits.ll
r600.amdgpu-alias-analysis.ll
r600.bitcast.ll
r600.global_atomics.ll
r600.private-memory.ll
r600.work-item-intrinsics.ll
r600cfg.ll
rcp-pattern.ll
read-register-invalid-subtarget.ll
read-register-invalid-type-i32.ll
read-register-invalid-type-i64.ll
read_register.ll
readcyclecounter.ll
readlane_exec0.mir
reduce-load-width-alignment.ll
reduce-saveexec.mir
reduce-store-width-alignment.ll
reg-coalescer-sched-crash.ll
regcoal-subrange-join.mir
regcoalesce-dbg.mir
regcoalesce-prune.mir
register-count-comments.ll
rename-disconnected-bug.ll
rename-independent-subregs-mac-operands.mir
rename-independent-subregs.mir
reorder-stores.ll
ret.ll
ret_jump.ll
rewrite-out-arguments-address-space.ll
rewrite-out-arguments.ll
rotl.i64.ll
rotl.ll
rotr.i64.ll
rotr.ll
rsq.ll
rv7x0_count3.ll
s_addk_i32.ll
s_movk_i32.ll
s_mulk_i32.ll
sad.ll
saddo.ll
salu-to-valu.ll
sampler-resource-id.ll
scalar-store-cache-flush.mir
scalar_to_vector.ll
sched-crash-dbg-value.mir
schedule-fs-loop-nested-if.ll
schedule-fs-loop-nested.ll
schedule-fs-loop.ll
schedule-global-loads.ll
schedule-if-2.ll
schedule-if.ll
schedule-ilp.ll
schedule-kernel-arg-loads.ll
schedule-regpressure-limit.ll
schedule-regpressure-limit2.ll
schedule-regpressure.mir
schedule-vs-if-nested-loop-failure.ll
schedule-vs-if-nested-loop.ll
scheduler-subrange-crash.ll
scratch-buffer.ll
scratch-simple.ll
sdiv.ll
sdivrem24.ll
sdivrem64.ll
sdwa-gfx9.mir
sdwa-peephole-instr.mir
sdwa-peephole.ll
sdwa-preserve.mir
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; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}test_concat_v1i32:
; 0x80f000 is the high 32 bits of the resource descriptor used by MUBUF
; instructions that access scratch memory. Bit 23, which is the add_tid_enable
; bit, is only set for scratch access, so we can check for the absence of this
; value if we want to ensure scratch memory is not being used.
; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
; SI-NOT: movrel
define amdgpu_kernel void @test_concat_v1i32(<2 x i32> addrspace(1)* %out, <1 x i32> %a, <1 x i32> %b) nounwind {
%concat = shufflevector <1 x i32> %a, <1 x i32> %b, <2 x i32> <i32 0, i32 1>
store <2 x i32> %concat, <2 x i32> addrspace(1)* %out, align 8
ret void
}
; FUNC-LABEL: {{^}}test_concat_v2i32:
; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
; SI-NOT: movrel
define amdgpu_kernel void @test_concat_v2i32(<4 x i32> addrspace(1)* %out, <2 x i32> %a, <2 x i32> %b) nounwind {
%concat = shufflevector <2 x i32> %a, <2 x i32> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
store <4 x i32> %concat, <4 x i32> addrspace(1)* %out, align 16
ret void
}
; FUNC-LABEL: {{^}}test_concat_v4i32:
; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
; SI-NOT: movrel
define amdgpu_kernel void @test_concat_v4i32(<8 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32> %b) nounwind {
%concat = shufflevector <4 x i32> %a, <4 x i32> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
store <8 x i32> %concat, <8 x i32> addrspace(1)* %out, align 32
ret void
}
; FUNC-LABEL: {{^}}test_concat_v8i32:
; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
; SI-NOT: movrel
define amdgpu_kernel void @test_concat_v8i32(<16 x i32> addrspace(1)* %out, <8 x i32> %a, <8 x i32> %b) nounwind {
%concat = shufflevector <8 x i32> %a, <8 x i32> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
store <16 x i32> %concat, <16 x i32> addrspace(1)* %out, align 64
ret void
}
; FUNC-LABEL: {{^}}test_concat_v16i32:
; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
; SI-NOT: movrel
define amdgpu_kernel void @test_concat_v16i32(<32 x i32> addrspace(1)* %out, <16 x i32> %a, <16 x i32> %b) nounwind {
%concat = shufflevector <16 x i32> %a, <16 x i32> %b, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
store <32 x i32> %concat, <32 x i32> addrspace(1)* %out, align 128
ret void
}
; FUNC-LABEL: {{^}}test_concat_v1f32:
; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
; SI-NOT: movrel
define amdgpu_kernel void @test_concat_v1f32(<2 x float> addrspace(1)* %out, <1 x float> %a, <1 x float> %b) nounwind {
%concat = shufflevector <1 x float> %a, <1 x float> %b, <2 x i32> <i32 0, i32 1>
store <2 x float> %concat, <2 x float> addrspace(1)* %out, align 8
ret void
}
; FUNC-LABEL: {{^}}test_concat_v2f32:
; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
; SI-NOT: movrel
define amdgpu_kernel void @test_concat_v2f32(<4 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) nounwind {
%concat = shufflevector <2 x float> %a, <2 x float> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
store <4 x float> %concat, <4 x float> addrspace(1)* %out, align 16
ret void
}
; FUNC-LABEL: {{^}}test_concat_v4f32:
; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
; SI-NOT: movrel
define amdgpu_kernel void @test_concat_v4f32(<8 x float> addrspace(1)* %out, <4 x float> %a, <4 x float> %b) nounwind {
%concat = shufflevector <4 x float> %a, <4 x float> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
store <8 x float> %concat, <8 x float> addrspace(1)* %out, align 32
ret void
}
; FUNC-LABEL: {{^}}test_concat_v8f32:
; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
; SI-NOT: movrel
define amdgpu_kernel void @test_concat_v8f32(<16 x float> addrspace(1)* %out, <8 x float> %a, <8 x float> %b) nounwind {
%concat = shufflevector <8 x float> %a, <8 x float> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
store <16 x float> %concat, <16 x float> addrspace(1)* %out, align 64
ret void
}
; FUNC-LABEL: {{^}}test_concat_v16f32:
; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
; SI-NOT: movrel
define amdgpu_kernel void @test_concat_v16f32(<32 x float> addrspace(1)* %out, <16 x float> %a, <16 x float> %b) nounwind {
%concat = shufflevector <16 x float> %a, <16 x float> %b, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
store <32 x float> %concat, <32 x float> addrspace(1)* %out, align 128
ret void
}
; FUNC-LABEL: {{^}}test_concat_v1i64:
; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
; SI-NOT: movrel
define amdgpu_kernel void @test_concat_v1i64(<2 x double> addrspace(1)* %out, <1 x double> %a, <1 x double> %b) nounwind {
%concat = shufflevector <1 x double> %a, <1 x double> %b, <2 x i32> <i32 0, i32 1>
store <2 x double> %concat, <2 x double> addrspace(1)* %out, align 16
ret void
}
; FUNC-LABEL: {{^}}test_concat_v2i64:
; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
; SI-NOT: movrel
define amdgpu_kernel void @test_concat_v2i64(<4 x double> addrspace(1)* %out, <2 x double> %a, <2 x double> %b) nounwind {
%concat = shufflevector <2 x double> %a, <2 x double> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
store <4 x double> %concat, <4 x double> addrspace(1)* %out, align 32
ret void
}
; FUNC-LABEL: {{^}}test_concat_v4i64:
; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
; SI-NOT: movrel
define amdgpu_kernel void @test_concat_v4i64(<8 x double> addrspace(1)* %out, <4 x double> %a, <4 x double> %b) nounwind {
%concat = shufflevector <4 x double> %a, <4 x double> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
store <8 x double> %concat, <8 x double> addrspace(1)* %out, align 64
ret void
}
; FUNC-LABEL: {{^}}test_concat_v8i64:
; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
; SI-NOT: movrel
define amdgpu_kernel void @test_concat_v8i64(<16 x double> addrspace(1)* %out, <8 x double> %a, <8 x double> %b) nounwind {
%concat = shufflevector <8 x double> %a, <8 x double> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
store <16 x double> %concat, <16 x double> addrspace(1)* %out, align 128
ret void
}
; FUNC-LABEL: {{^}}test_concat_v16i64:
; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
; SI-NOT: movrel
define amdgpu_kernel void @test_concat_v16i64(<32 x double> addrspace(1)* %out, <16 x double> %a, <16 x double> %b) nounwind {
%concat = shufflevector <16 x double> %a, <16 x double> %b, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
store <32 x double> %concat, <32 x double> addrspace(1)* %out, align 256
ret void
}
; FUNC-LABEL: {{^}}test_concat_v1f64:
; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
; SI-NOT: movrel
define amdgpu_kernel void @test_concat_v1f64(<2 x double> addrspace(1)* %out, <1 x double> %a, <1 x double> %b) nounwind {
%concat = shufflevector <1 x double> %a, <1 x double> %b, <2 x i32> <i32 0, i32 1>
store <2 x double> %concat, <2 x double> addrspace(1)* %out, align 16
ret void
}
; FUNC-LABEL: {{^}}test_concat_v2f64:
; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
; SI-NOT: movrel
define amdgpu_kernel void @test_concat_v2f64(<4 x double> addrspace(1)* %out, <2 x double> %a, <2 x double> %b) nounwind {
%concat = shufflevector <2 x double> %a, <2 x double> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
store <4 x double> %concat, <4 x double> addrspace(1)* %out, align 32
ret void
}
; FUNC-LABEL: {{^}}test_concat_v4f64:
; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
; SI-NOT: movrel
define amdgpu_kernel void @test_concat_v4f64(<8 x double> addrspace(1)* %out, <4 x double> %a, <4 x double> %b) nounwind {
%concat = shufflevector <4 x double> %a, <4 x double> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
store <8 x double> %concat, <8 x double> addrspace(1)* %out, align 64
ret void
}
; FUNC-LABEL: {{^}}test_concat_v8f64:
; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
; SI-NOT: movrel
define amdgpu_kernel void @test_concat_v8f64(<16 x double> addrspace(1)* %out, <8 x double> %a, <8 x double> %b) nounwind {
%concat = shufflevector <8 x double> %a, <8 x double> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
store <16 x double> %concat, <16 x double> addrspace(1)* %out, align 128
ret void
}
; FUNC-LABEL: {{^}}test_concat_v16f64:
; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
; SI-NOT: movrel
define amdgpu_kernel void @test_concat_v16f64(<32 x double> addrspace(1)* %out, <16 x double> %a, <16 x double> %b) nounwind {
%concat = shufflevector <16 x double> %a, <16 x double> %b, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
store <32 x double> %concat, <32 x double> addrspace(1)* %out, align 256
ret void
}
; FUNC-LABEL: {{^}}test_concat_v1i1:
; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
; SI-NOT: movrel
define amdgpu_kernel void @test_concat_v1i1(<2 x i1> addrspace(1)* %out, <1 x i1> %a, <1 x i1> %b) nounwind {
%concat = shufflevector <1 x i1> %a, <1 x i1> %b, <2 x i32> <i32 0, i32 1>
store <2 x i1> %concat, <2 x i1> addrspace(1)* %out
ret void
}
; FUNC-LABEL: {{^}}test_concat_v2i1:
; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
; SI-NOT: movrel
define amdgpu_kernel void @test_concat_v2i1(<4 x i1> addrspace(1)* %out, <2 x i1> %a, <2 x i1> %b) nounwind {
%concat = shufflevector <2 x i1> %a, <2 x i1> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
store <4 x i1> %concat, <4 x i1> addrspace(1)* %out
ret void
}
; FUNC-LABEL: {{^}}test_concat_v4i1:
; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
; SI-NOT: movrel
define amdgpu_kernel void @test_concat_v4i1(<8 x i1> addrspace(1)* %out, <4 x i1> %a, <4 x i1> %b) nounwind {
%concat = shufflevector <4 x i1> %a, <4 x i1> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
store <8 x i1> %concat, <8 x i1> addrspace(1)* %out
ret void
}
; FUNC-LABEL: {{^}}test_concat_v8i1:
; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
; SI-NOT: movrel
define amdgpu_kernel void @test_concat_v8i1(<16 x i1> addrspace(1)* %out, <8 x i1> %a, <8 x i1> %b) nounwind {
%concat = shufflevector <8 x i1> %a, <8 x i1> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
store <16 x i1> %concat, <16 x i1> addrspace(1)* %out
ret void
}
; FUNC-LABEL: {{^}}test_concat_v16i1:
; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
; SI-NOT: movrel
define amdgpu_kernel void @test_concat_v16i1(<32 x i1> addrspace(1)* %out, <16 x i1> %a, <16 x i1> %b) nounwind {
%concat = shufflevector <16 x i1> %a, <16 x i1> %b, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
store <32 x i1> %concat, <32 x i1> addrspace(1)* %out
ret void
}
; FUNC-LABEL: {{^}}test_concat_v32i1:
; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
; SI-NOT: movrel
define amdgpu_kernel void @test_concat_v32i1(<64 x i1> addrspace(1)* %out, <32 x i1> %a, <32 x i1> %b) nounwind {
%concat = shufflevector <32 x i1> %a, <32 x i1> %b, <64 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 32, i32 33, i32 34, i32 35, i32 36, i32 37, i32 38, i32 39, i32 40, i32 41, i32 42, i32 43, i32 44, i32 45, i32 46, i32 47, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63>
store <64 x i1> %concat, <64 x i1> addrspace(1)* %out
ret void
}
; FUNC-LABEL: {{^}}test_concat_v1i16:
; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
; SI-NOT: movrel
define amdgpu_kernel void @test_concat_v1i16(<2 x i16> addrspace(1)* %out, <1 x i16> %a, <1 x i16> %b) nounwind {
%concat = shufflevector <1 x i16> %a, <1 x i16> %b, <2 x i32> <i32 0, i32 1>
store <2 x i16> %concat, <2 x i16> addrspace(1)* %out, align 4
ret void
}
; FUNC-LABEL: {{^}}test_concat_v2i16:
; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
; SI-NOT: movrel
define amdgpu_kernel void @test_concat_v2i16(<4 x i16> addrspace(1)* %out, <2 x i16> %a, <2 x i16> %b) nounwind {
%concat = shufflevector <2 x i16> %a, <2 x i16> %b, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
store <4 x i16> %concat, <4 x i16> addrspace(1)* %out, align 8
ret void
}
; FUNC-LABEL: {{^}}test_concat_v4i16:
; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
; SI-NOT: movrel
define amdgpu_kernel void @test_concat_v4i16(<8 x i16> addrspace(1)* %out, <4 x i16> %a, <4 x i16> %b) nounwind {
%concat = shufflevector <4 x i16> %a, <4 x i16> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
store <8 x i16> %concat, <8 x i16> addrspace(1)* %out, align 16
ret void
}
; FUNC-LABEL: {{^}}test_concat_v8i16:
; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
; SI-NOT: movrel
define amdgpu_kernel void @test_concat_v8i16(<16 x i16> addrspace(1)* %out, <8 x i16> %a, <8 x i16> %b) nounwind {
%concat = shufflevector <8 x i16> %a, <8 x i16> %b, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
store <16 x i16> %concat, <16 x i16> addrspace(1)* %out, align 32
ret void
}
; FUNC-LABEL: {{^}}test_concat_v16i16:
; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
; SI-NOT: movrel
define amdgpu_kernel void @test_concat_v16i16(<32 x i16> addrspace(1)* %out, <16 x i16> %a, <16 x i16> %b) nounwind {
%concat = shufflevector <16 x i16> %a, <16 x i16> %b, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
store <32 x i16> %concat, <32 x i16> addrspace(1)* %out, align 64
ret void
}
; FUNC-LABEL: {{^}}concat_vector_crash:
; SI: s_endpgm
define amdgpu_kernel void @concat_vector_crash(<8 x float> addrspace(1)* %out, <2 x float> addrspace(1)* %in) {
bb:
%tmp = load <2 x float>, <2 x float> addrspace(1)* %in, align 4
%tmp1 = shufflevector <2 x float> %tmp, <2 x float> undef, <8 x i32> <i32 0, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
%tmp2 = shufflevector <8 x float> undef, <8 x float> %tmp1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 8, i32 9>
store <8 x float> %tmp2, <8 x float> addrspace(1)* %out, align 32
ret void
}