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609 lines
35 KiB
TableGen
609 lines
35 KiB
TableGen
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//===-- PPCSchedule440.td - PPC 440 Scheduling Definitions -*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// Primary reference:
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// PowerPC 440x6 Embedded Processor Core User's Manual.
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// IBM (as updated in) 2010.
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// The basic PPC 440 does not include a floating-point unit; the pipeline
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// timings here are constructed to match the FP2 unit shipped with the
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// PPC-440- and PPC-450-based Blue Gene (L and P) supercomputers.
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// References:
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// S. Chatterjee, et al. Design and exploitation of a high-performance
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// SIMD floating-point unit for Blue Gene/L.
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// IBM J. Res. & Dev. 49 (2/3) March/May 2005.
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// also:
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// Carlos Sosa and Brant Knudson. IBM System Blue Gene Solution:
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// Blue Gene/P Application Development.
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// IBM (as updated in) 2009.
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//===----------------------------------------------------------------------===//
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// Functional units on the PowerPC 440/450 chip sets
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//
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def P440_DISS1 : FuncUnit; // Issue unit 1
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def P440_DISS2 : FuncUnit; // Issue unit 2
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def P440_LRACC : FuncUnit; // Register access and dispatch for
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// the simple integer (J-pipe) and
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// load/store (L-pipe) pipelines
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def P440_IRACC : FuncUnit; // Register access and dispatch for
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// the complex integer (I-pipe) pipeline
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def P440_FRACC : FuncUnit; // Register access and dispatch for
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// the floating-point execution (F-pipe) pipeline
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def P440_IEXE1 : FuncUnit; // Execution stage 1 for the I pipeline
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def P440_IEXE2 : FuncUnit; // Execution stage 2 for the I pipeline
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def P440_IWB : FuncUnit; // Write-back unit for the I pipeline
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def P440_JEXE1 : FuncUnit; // Execution stage 1 for the J pipeline
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def P440_JEXE2 : FuncUnit; // Execution stage 2 for the J pipeline
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def P440_JWB : FuncUnit; // Write-back unit for the J pipeline
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def P440_AGEN : FuncUnit; // Address generation for the L pipeline
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def P440_CRD : FuncUnit; // D-cache access for the L pipeline
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def P440_LWB : FuncUnit; // Write-back unit for the L pipeline
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def P440_FEXE1 : FuncUnit; // Execution stage 1 for the F pipeline
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def P440_FEXE2 : FuncUnit; // Execution stage 2 for the F pipeline
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def P440_FEXE3 : FuncUnit; // Execution stage 3 for the F pipeline
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def P440_FEXE4 : FuncUnit; // Execution stage 4 for the F pipeline
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def P440_FEXE5 : FuncUnit; // Execution stage 5 for the F pipeline
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def P440_FEXE6 : FuncUnit; // Execution stage 6 for the F pipeline
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def P440_FWB : FuncUnit; // Write-back unit for the F pipeline
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def P440_LWARX_Hold : FuncUnit; // This is a pseudo-unit which is used
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// to make sure that no lwarx/stwcx.
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// instructions are issued while another
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// lwarx/stwcx. is in the L pipe.
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def P440_GPR_Bypass : Bypass; // The bypass for general-purpose regs.
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def P440_FPR_Bypass : Bypass; // The bypass for floating-point regs.
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// Notes:
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// Instructions are held in the FRACC, LRACC and IRACC pipeline
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// stages until their source operands become ready. Exceptions:
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// - Store instructions will hold in the AGEN stage
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// - The integer multiply-accumulate instruction will hold in
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// the IEXE1 stage
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//
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// For most I-pipe operations, the result is available at the end of
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// the IEXE1 stage. Operations such as multiply and divide must
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// continue to execute in IEXE2 and IWB. Divide resides in IWB for
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// 33 cycles (multiply also calculates its result in IWB). For all
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// J-pipe instructions, the result is available
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// at the end of the JEXE1 stage. Loads have a 3-cycle latency
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// (data is not available until after the LWB stage).
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//
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// The L1 cache hit latency is four cycles for floating point loads
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// and three cycles for integer loads.
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//
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// The stwcx. instruction requires both the LRACC and the IRACC
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// dispatch stages. It must be issued from DISS0.
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//
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// All lwarx/stwcx. instructions hold in LRACC if another
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// uncommitted lwarx/stwcx. is in AGEN, CRD, or LWB.
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//
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// msync (a.k.a. sync) and mbar will hold in LWB until all load/store
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// resources are empty. AGEN and CRD are held empty until the msync/mbar
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// commits.
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//
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// Most floating-point instructions, computational and move,
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// have a 5-cycle latency. Divide takes longer (30 cycles). Instructions that
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// update the CR take 2 cycles. Stores take 3 cycles and, as mentioned above,
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// loads take 4 cycles (for L1 hit).
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//
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// This file defines the itinerary class data for the PPC 440 processor.
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//
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//===----------------------------------------------------------------------===//
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def PPC440Itineraries : ProcessorItineraries<
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[P440_DISS1, P440_DISS2, P440_FRACC, P440_IRACC, P440_IEXE1, P440_IEXE2,
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P440_IWB, P440_LRACC, P440_JEXE1, P440_JEXE2, P440_JWB, P440_AGEN, P440_CRD,
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P440_LWB, P440_FEXE1, P440_FEXE2, P440_FEXE3, P440_FEXE4, P440_FEXE5,
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P440_FEXE6, P440_FWB, P440_LWARX_Hold],
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[P440_GPR_Bypass, P440_FPR_Bypass], [
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InstrItinData<IIC_IntSimple, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
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InstrStage<1, [P440_IRACC, P440_LRACC]>,
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InstrStage<1, [P440_IEXE1, P440_JEXE1]>,
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InstrStage<1, [P440_IEXE2, P440_JEXE2]>,
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InstrStage<1, [P440_IWB, P440_JWB]>],
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[2, 0, 0],
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[P440_GPR_Bypass,
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P440_GPR_Bypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_IntGeneral, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
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InstrStage<1, [P440_IRACC, P440_LRACC]>,
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InstrStage<1, [P440_IEXE1, P440_JEXE1]>,
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InstrStage<1, [P440_IEXE2, P440_JEXE2]>,
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InstrStage<1, [P440_IWB, P440_JWB]>],
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[2, 0, 0],
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[P440_GPR_Bypass,
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P440_GPR_Bypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_IntISEL, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
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InstrStage<1, [P440_IRACC, P440_LRACC]>,
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InstrStage<1, [P440_IEXE1, P440_JEXE1]>,
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InstrStage<1, [P440_IEXE2, P440_JEXE2]>,
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InstrStage<1, [P440_IWB, P440_JWB]>],
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[2, 0, 0, 0],
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[P440_GPR_Bypass,
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P440_GPR_Bypass, P440_GPR_Bypass, NoBypass]>,
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InstrItinData<IIC_IntCompare, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
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InstrStage<1, [P440_IRACC, P440_LRACC]>,
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InstrStage<1, [P440_IEXE1, P440_JEXE1]>,
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InstrStage<1, [P440_IEXE2, P440_JEXE2]>,
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InstrStage<1, [P440_IWB, P440_JWB]>],
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[2, 0, 0],
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[NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_IntDivW, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
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InstrStage<1, [P440_IRACC]>,
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InstrStage<1, [P440_IEXE1]>,
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InstrStage<1, [P440_IEXE2]>,
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InstrStage<33, [P440_IWB]>],
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[36, 0, 0],
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[NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_IntMFFS, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
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InstrStage<1, [P440_IRACC]>,
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InstrStage<1, [P440_IEXE1]>,
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InstrStage<1, [P440_IEXE2]>,
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InstrStage<1, [P440_IWB]>],
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[3, 0, 0],
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[P440_GPR_Bypass,
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P440_GPR_Bypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_IntMTFSB0, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
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InstrStage<1, [P440_IRACC]>,
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InstrStage<1, [P440_IEXE1]>,
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InstrStage<1, [P440_IEXE2]>,
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InstrStage<1, [P440_IWB]>],
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[3, 0, 0],
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[P440_GPR_Bypass,
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P440_GPR_Bypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_IntMulHW, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
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InstrStage<1, [P440_IRACC]>,
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InstrStage<1, [P440_IEXE1]>,
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InstrStage<1, [P440_IEXE2]>,
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InstrStage<1, [P440_IWB]>],
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[4, 0, 0],
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[NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_IntMulHWU, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
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InstrStage<1, [P440_IRACC]>,
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InstrStage<1, [P440_IEXE1]>,
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InstrStage<1, [P440_IEXE2]>,
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InstrStage<1, [P440_IWB]>],
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[4, 0, 0],
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[NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_IntMulLI, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
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InstrStage<1, [P440_IRACC]>,
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InstrStage<1, [P440_IEXE1]>,
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InstrStage<1, [P440_IEXE2]>,
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InstrStage<1, [P440_IWB]>],
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[4, 0, 0],
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[NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_IntRotate, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
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InstrStage<1, [P440_IRACC, P440_LRACC]>,
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InstrStage<1, [P440_IEXE1, P440_JEXE1]>,
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InstrStage<1, [P440_IEXE2, P440_JEXE2]>,
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InstrStage<1, [P440_IWB, P440_JWB]>],
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[2, 0, 0],
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[P440_GPR_Bypass,
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P440_GPR_Bypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_IntShift, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
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InstrStage<1, [P440_IRACC, P440_LRACC]>,
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InstrStage<1, [P440_IEXE1, P440_JEXE1]>,
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InstrStage<1, [P440_IEXE2, P440_JEXE2]>,
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InstrStage<1, [P440_IWB, P440_JWB]>],
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[2, 0, 0],
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[P440_GPR_Bypass,
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P440_GPR_Bypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_IntTrapW, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
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InstrStage<1, [P440_IRACC]>,
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InstrStage<1, [P440_IEXE1]>,
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InstrStage<1, [P440_IEXE2]>,
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InstrStage<1, [P440_IWB]>],
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[2, 0],
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[P440_GPR_Bypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_BrB, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
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InstrStage<1, [P440_IRACC]>,
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InstrStage<1, [P440_IEXE1]>,
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InstrStage<1, [P440_IEXE2]>,
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InstrStage<1, [P440_IWB]>],
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[4, 0],
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[NoBypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_BrCR, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
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InstrStage<1, [P440_IRACC]>,
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InstrStage<1, [P440_IEXE1]>,
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InstrStage<1, [P440_IEXE2]>,
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InstrStage<1, [P440_IWB]>],
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[4, 0, 0],
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[NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_BrMCR, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
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InstrStage<1, [P440_IRACC]>,
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InstrStage<1, [P440_IEXE1]>,
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InstrStage<1, [P440_IEXE2]>,
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InstrStage<1, [P440_IWB]>],
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[4, 0, 0],
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[NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_BrMCRX, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
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InstrStage<1, [P440_IRACC]>,
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InstrStage<1, [P440_IEXE1]>,
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InstrStage<1, [P440_IEXE2]>,
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InstrStage<1, [P440_IWB]>],
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[4, 0, 0],
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[NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_LdStDCBA, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
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InstrStage<1, [P440_LRACC]>,
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InstrStage<1, [P440_AGEN]>,
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InstrStage<1, [P440_CRD]>,
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InstrStage<1, [P440_LWB]>],
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[1, 1],
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[NoBypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_LdStDCBF, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
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InstrStage<1, [P440_LRACC]>,
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InstrStage<1, [P440_AGEN]>,
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InstrStage<1, [P440_CRD]>,
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InstrStage<1, [P440_LWB]>],
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[1, 1],
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[NoBypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_LdStDCBI, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
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InstrStage<1, [P440_LRACC]>,
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InstrStage<1, [P440_AGEN]>,
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InstrStage<1, [P440_CRD]>,
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InstrStage<1, [P440_LWB]>],
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[1, 1],
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[NoBypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_LdStLoad, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
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InstrStage<1, [P440_LRACC]>,
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InstrStage<1, [P440_AGEN]>,
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InstrStage<1, [P440_CRD]>,
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InstrStage<2, [P440_LWB]>],
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[5, 1, 1],
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[P440_GPR_Bypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_LdStLoadUpd,[InstrStage<1, [P440_DISS1, P440_DISS2]>,
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InstrStage<1, [P440_LRACC]>,
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InstrStage<1, [P440_AGEN]>,
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InstrStage<1, [P440_CRD]>,
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InstrStage<2, [P440_LWB]>],
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[5, 2, 1, 1],
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[P440_GPR_Bypass, P440_GPR_Bypass]>,
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InstrItinData<IIC_LdStLoadUpdX,[InstrStage<1, [P440_DISS1, P440_DISS2]>,
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InstrStage<1, [P440_LRACC]>,
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InstrStage<1, [P440_AGEN]>,
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InstrStage<1, [P440_CRD]>,
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||
|
|
InstrStage<2, [P440_LWB]>],
|
||
|
|
[5, 2, 1, 1],
|
||
|
|
[P440_GPR_Bypass, P440_GPR_Bypass]>,
|
||
|
|
InstrItinData<IIC_LdStStore, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
|
||
|
|
InstrStage<1, [P440_LRACC]>,
|
||
|
|
InstrStage<1, [P440_AGEN]>,
|
||
|
|
InstrStage<1, [P440_CRD]>,
|
||
|
|
InstrStage<2, [P440_LWB]>],
|
||
|
|
[1, 1, 1],
|
||
|
|
[NoBypass, P440_GPR_Bypass]>,
|
||
|
|
InstrItinData<IIC_LdStStoreUpd,[InstrStage<1, [P440_DISS1, P440_DISS2]>,
|
||
|
|
InstrStage<1, [P440_LRACC]>,
|
||
|
|
InstrStage<1, [P440_AGEN]>,
|
||
|
|
InstrStage<1, [P440_CRD]>,
|
||
|
|
InstrStage<2, [P440_LWB]>],
|
||
|
|
[2, 1, 1, 1],
|
||
|
|
[NoBypass, P440_GPR_Bypass]>,
|
||
|
|
InstrItinData<IIC_LdStICBI, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
|
||
|
|
InstrStage<1, [P440_LRACC]>,
|
||
|
|
InstrStage<1, [P440_AGEN]>,
|
||
|
|
InstrStage<1, [P440_CRD]>,
|
||
|
|
InstrStage<1, [P440_LWB]>],
|
||
|
|
[4, 1, 1],
|
||
|
|
[NoBypass, P440_GPR_Bypass]>,
|
||
|
|
InstrItinData<IIC_LdStSTFD, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
|
||
|
|
InstrStage<1, [P440_LRACC]>,
|
||
|
|
InstrStage<1, [P440_AGEN]>,
|
||
|
|
InstrStage<1, [P440_CRD]>,
|
||
|
|
InstrStage<1, [P440_LWB]>],
|
||
|
|
[1, 1, 1],
|
||
|
|
[NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
|
||
|
|
InstrItinData<IIC_LdStSTFDU, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
|
||
|
|
InstrStage<1, [P440_LRACC]>,
|
||
|
|
InstrStage<1, [P440_AGEN]>,
|
||
|
|
InstrStage<1, [P440_CRD]>,
|
||
|
|
InstrStage<1, [P440_LWB]>],
|
||
|
|
[2, 1, 1, 1],
|
||
|
|
[NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
|
||
|
|
InstrItinData<IIC_LdStLFD, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
|
||
|
|
InstrStage<1, [P440_LRACC]>,
|
||
|
|
InstrStage<1, [P440_AGEN]>,
|
||
|
|
InstrStage<1, [P440_CRD]>,
|
||
|
|
InstrStage<2, [P440_LWB]>],
|
||
|
|
[5, 1, 1],
|
||
|
|
[NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
|
||
|
|
InstrItinData<IIC_LdStLFDU, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
|
||
|
|
InstrStage<1, [P440_LRACC]>,
|
||
|
|
InstrStage<1, [P440_AGEN]>,
|
||
|
|
InstrStage<1, [P440_CRD]>,
|
||
|
|
InstrStage<1, [P440_LWB]>],
|
||
|
|
[5, 2, 1, 1],
|
||
|
|
[NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
|
||
|
|
InstrItinData<IIC_LdStLFDUX, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
|
||
|
|
InstrStage<1, [P440_LRACC]>,
|
||
|
|
InstrStage<1, [P440_AGEN]>,
|
||
|
|
InstrStage<1, [P440_CRD]>,
|
||
|
|
InstrStage<1, [P440_LWB]>],
|
||
|
|
[5, 2, 1, 1],
|
||
|
|
[NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
|
||
|
|
InstrItinData<IIC_LdStLHA, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
|
||
|
|
InstrStage<1, [P440_LRACC]>,
|
||
|
|
InstrStage<1, [P440_AGEN]>,
|
||
|
|
InstrStage<1, [P440_CRD]>,
|
||
|
|
InstrStage<1, [P440_LWB]>],
|
||
|
|
[4, 1, 1],
|
||
|
|
[NoBypass, P440_GPR_Bypass]>,
|
||
|
|
InstrItinData<IIC_LdStLHAU, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
|
||
|
|
InstrStage<1, [P440_LRACC]>,
|
||
|
|
InstrStage<1, [P440_AGEN]>,
|
||
|
|
InstrStage<1, [P440_CRD]>,
|
||
|
|
InstrStage<1, [P440_LWB]>],
|
||
|
|
[4, 1, 1],
|
||
|
|
[NoBypass, P440_GPR_Bypass]>,
|
||
|
|
InstrItinData<IIC_LdStLHAUX, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
|
||
|
|
InstrStage<1, [P440_LRACC]>,
|
||
|
|
InstrStage<1, [P440_AGEN]>,
|
||
|
|
InstrStage<1, [P440_CRD]>,
|
||
|
|
InstrStage<1, [P440_LWB]>],
|
||
|
|
[4, 1, 1],
|
||
|
|
[NoBypass, P440_GPR_Bypass]>,
|
||
|
|
InstrItinData<IIC_LdStLMW, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
|
||
|
|
InstrStage<1, [P440_LRACC]>,
|
||
|
|
InstrStage<1, [P440_AGEN]>,
|
||
|
|
InstrStage<1, [P440_CRD]>,
|
||
|
|
InstrStage<1, [P440_LWB]>],
|
||
|
|
[4, 1, 1],
|
||
|
|
[NoBypass, P440_GPR_Bypass]>,
|
||
|
|
InstrItinData<IIC_LdStLWARX, [InstrStage<1, [P440_DISS1]>,
|
||
|
|
InstrStage<1, [P440_IRACC], 0>,
|
||
|
|
InstrStage<4, [P440_LWARX_Hold], 0>,
|
||
|
|
InstrStage<1, [P440_LRACC]>,
|
||
|
|
InstrStage<1, [P440_AGEN]>,
|
||
|
|
InstrStage<1, [P440_CRD]>,
|
||
|
|
InstrStage<1, [P440_LWB]>],
|
||
|
|
[4, 1, 1],
|
||
|
|
[NoBypass, P440_GPR_Bypass]>,
|
||
|
|
InstrItinData<IIC_LdStSTD, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
|
||
|
|
InstrStage<1, [P440_LRACC]>,
|
||
|
|
InstrStage<1, [P440_AGEN]>,
|
||
|
|
InstrStage<1, [P440_CRD]>,
|
||
|
|
InstrStage<2, [P440_LWB]>],
|
||
|
|
[4, 1, 1],
|
||
|
|
[NoBypass, P440_GPR_Bypass]>,
|
||
|
|
InstrItinData<IIC_LdStSTDU, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
|
||
|
|
InstrStage<1, [P440_LRACC]>,
|
||
|
|
InstrStage<1, [P440_AGEN]>,
|
||
|
|
InstrStage<1, [P440_CRD]>,
|
||
|
|
InstrStage<2, [P440_LWB]>],
|
||
|
|
[2, 1, 1, 1],
|
||
|
|
[NoBypass, P440_GPR_Bypass]>,
|
||
|
|
InstrItinData<IIC_LdStSTDUX, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
|
||
|
|
InstrStage<1, [P440_LRACC]>,
|
||
|
|
InstrStage<1, [P440_AGEN]>,
|
||
|
|
InstrStage<1, [P440_CRD]>,
|
||
|
|
InstrStage<2, [P440_LWB]>],
|
||
|
|
[2, 1, 1, 1],
|
||
|
|
[NoBypass, P440_GPR_Bypass]>,
|
||
|
|
InstrItinData<IIC_LdStSTDCX, [InstrStage<1, [P440_DISS1]>,
|
||
|
|
InstrStage<1, [P440_IRACC], 0>,
|
||
|
|
InstrStage<4, [P440_LWARX_Hold], 0>,
|
||
|
|
InstrStage<1, [P440_LRACC]>,
|
||
|
|
InstrStage<1, [P440_AGEN]>,
|
||
|
|
InstrStage<1, [P440_CRD]>,
|
||
|
|
InstrStage<1, [P440_LWB]>],
|
||
|
|
[4, 1, 1],
|
||
|
|
[NoBypass, P440_GPR_Bypass]>,
|
||
|
|
InstrItinData<IIC_LdStSTWCX, [InstrStage<1, [P440_DISS1]>,
|
||
|
|
InstrStage<1, [P440_IRACC], 0>,
|
||
|
|
InstrStage<4, [P440_LWARX_Hold], 0>,
|
||
|
|
InstrStage<1, [P440_LRACC]>,
|
||
|
|
InstrStage<1, [P440_AGEN]>,
|
||
|
|
InstrStage<1, [P440_CRD]>,
|
||
|
|
InstrStage<1, [P440_LWB]>],
|
||
|
|
[4, 1, 1],
|
||
|
|
[NoBypass, P440_GPR_Bypass]>,
|
||
|
|
InstrItinData<IIC_LdStSync, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
|
||
|
|
InstrStage<1, [P440_LRACC]>,
|
||
|
|
InstrStage<3, [P440_AGEN], 1>,
|
||
|
|
InstrStage<2, [P440_CRD], 1>,
|
||
|
|
InstrStage<1, [P440_LWB]>]>,
|
||
|
|
InstrItinData<IIC_SprISYNC, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
|
||
|
|
InstrStage<1, [P440_FRACC], 0>,
|
||
|
|
InstrStage<1, [P440_LRACC], 0>,
|
||
|
|
InstrStage<1, [P440_IRACC]>,
|
||
|
|
InstrStage<1, [P440_FEXE1], 0>,
|
||
|
|
InstrStage<1, [P440_AGEN], 0>,
|
||
|
|
InstrStage<1, [P440_JEXE1], 0>,
|
||
|
|
InstrStage<1, [P440_IEXE1]>,
|
||
|
|
InstrStage<1, [P440_FEXE2], 0>,
|
||
|
|
InstrStage<1, [P440_CRD], 0>,
|
||
|
|
InstrStage<1, [P440_JEXE2], 0>,
|
||
|
|
InstrStage<1, [P440_IEXE2]>,
|
||
|
|
InstrStage<6, [P440_FEXE3], 0>,
|
||
|
|
InstrStage<6, [P440_LWB], 0>,
|
||
|
|
InstrStage<6, [P440_JWB], 0>,
|
||
|
|
InstrStage<6, [P440_IWB]>]>,
|
||
|
|
InstrItinData<IIC_SprMFSR, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
|
||
|
|
InstrStage<1, [P440_IRACC]>,
|
||
|
|
InstrStage<1, [P440_IEXE1]>,
|
||
|
|
InstrStage<1, [P440_IEXE2]>,
|
||
|
|
InstrStage<1, [P440_IWB]>],
|
||
|
|
[2, 0],
|
||
|
|
[P440_GPR_Bypass, P440_GPR_Bypass]>,
|
||
|
|
InstrItinData<IIC_SprMTMSR, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
|
||
|
|
InstrStage<1, [P440_IRACC]>,
|
||
|
|
InstrStage<1, [P440_IEXE1]>,
|
||
|
|
InstrStage<1, [P440_IEXE2]>,
|
||
|
|
InstrStage<1, [P440_IWB]>],
|
||
|
|
[2, 0],
|
||
|
|
[P440_GPR_Bypass, P440_GPR_Bypass]>,
|
||
|
|
InstrItinData<IIC_SprMTSR, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
|
||
|
|
InstrStage<1, [P440_IRACC]>,
|
||
|
|
InstrStage<1, [P440_IEXE1]>,
|
||
|
|
InstrStage<1, [P440_IEXE2]>,
|
||
|
|
InstrStage<3, [P440_IWB]>],
|
||
|
|
[5, 0],
|
||
|
|
[NoBypass, P440_GPR_Bypass]>,
|
||
|
|
InstrItinData<IIC_SprTLBSYNC, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
|
||
|
|
InstrStage<1, [P440_IRACC]>,
|
||
|
|
InstrStage<1, [P440_IEXE1]>,
|
||
|
|
InstrStage<1, [P440_IEXE2]>,
|
||
|
|
InstrStage<1, [P440_IWB]>]>,
|
||
|
|
InstrItinData<IIC_SprMFCR, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
|
||
|
|
InstrStage<1, [P440_IRACC]>,
|
||
|
|
InstrStage<1, [P440_IEXE1]>,
|
||
|
|
InstrStage<1, [P440_IEXE2]>,
|
||
|
|
InstrStage<1, [P440_IWB]>],
|
||
|
|
[4, 0],
|
||
|
|
[NoBypass, P440_GPR_Bypass]>,
|
||
|
|
InstrItinData<IIC_SprMFMSR, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
|
||
|
|
InstrStage<1, [P440_IRACC]>,
|
||
|
|
InstrStage<1, [P440_IEXE1]>,
|
||
|
|
InstrStage<1, [P440_IEXE2]>,
|
||
|
|
InstrStage<1, [P440_IWB]>],
|
||
|
|
[3, 0],
|
||
|
|
[P440_GPR_Bypass, P440_GPR_Bypass]>,
|
||
|
|
InstrItinData<IIC_SprMFSPR, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
|
||
|
|
InstrStage<1, [P440_IRACC]>,
|
||
|
|
InstrStage<1, [P440_IEXE1]>,
|
||
|
|
InstrStage<1, [P440_IEXE2]>,
|
||
|
|
InstrStage<3, [P440_IWB]>],
|
||
|
|
[6, 0],
|
||
|
|
[NoBypass, P440_GPR_Bypass]>,
|
||
|
|
InstrItinData<IIC_SprMFTB, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
|
||
|
|
InstrStage<1, [P440_IRACC]>,
|
||
|
|
InstrStage<1, [P440_IEXE1]>,
|
||
|
|
InstrStage<1, [P440_IEXE2]>,
|
||
|
|
InstrStage<3, [P440_IWB]>],
|
||
|
|
[6, 0],
|
||
|
|
[NoBypass, P440_GPR_Bypass]>,
|
||
|
|
InstrItinData<IIC_SprMTSPR, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
|
||
|
|
InstrStage<1, [P440_IRACC]>,
|
||
|
|
InstrStage<1, [P440_IEXE1]>,
|
||
|
|
InstrStage<1, [P440_IEXE2]>,
|
||
|
|
InstrStage<3, [P440_IWB]>],
|
||
|
|
[6, 0],
|
||
|
|
[NoBypass, P440_GPR_Bypass]>,
|
||
|
|
InstrItinData<IIC_SprMTSRIN, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
|
||
|
|
InstrStage<1, [P440_IRACC]>,
|
||
|
|
InstrStage<1, [P440_IEXE1]>,
|
||
|
|
InstrStage<1, [P440_IEXE2]>,
|
||
|
|
InstrStage<3, [P440_IWB]>],
|
||
|
|
[6, 0],
|
||
|
|
[NoBypass, P440_GPR_Bypass]>,
|
||
|
|
InstrItinData<IIC_SprRFI, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
|
||
|
|
InstrStage<1, [P440_IRACC]>,
|
||
|
|
InstrStage<1, [P440_IEXE1]>,
|
||
|
|
InstrStage<1, [P440_IEXE2]>,
|
||
|
|
InstrStage<1, [P440_IWB]>],
|
||
|
|
[4, 0],
|
||
|
|
[NoBypass, P440_GPR_Bypass]>,
|
||
|
|
InstrItinData<IIC_SprSC, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
|
||
|
|
InstrStage<1, [P440_IRACC]>,
|
||
|
|
InstrStage<1, [P440_IEXE1]>,
|
||
|
|
InstrStage<1, [P440_IEXE2]>,
|
||
|
|
InstrStage<1, [P440_IWB]>],
|
||
|
|
[4, 0],
|
||
|
|
[NoBypass, P440_GPR_Bypass]>,
|
||
|
|
InstrItinData<IIC_FPGeneral, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
|
||
|
|
InstrStage<1, [P440_FRACC]>,
|
||
|
|
InstrStage<1, [P440_FEXE1]>,
|
||
|
|
InstrStage<1, [P440_FEXE2]>,
|
||
|
|
InstrStage<1, [P440_FEXE3]>,
|
||
|
|
InstrStage<1, [P440_FEXE4]>,
|
||
|
|
InstrStage<1, [P440_FEXE5]>,
|
||
|
|
InstrStage<1, [P440_FEXE6]>,
|
||
|
|
InstrStage<1, [P440_FWB]>],
|
||
|
|
[6, 0, 0],
|
||
|
|
[P440_FPR_Bypass,
|
||
|
|
P440_FPR_Bypass, P440_FPR_Bypass]>,
|
||
|
|
InstrItinData<IIC_FPAddSub, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
|
||
|
|
InstrStage<1, [P440_FRACC]>,
|
||
|
|
InstrStage<1, [P440_FEXE1]>,
|
||
|
|
InstrStage<1, [P440_FEXE2]>,
|
||
|
|
InstrStage<1, [P440_FEXE3]>,
|
||
|
|
InstrStage<1, [P440_FEXE4]>,
|
||
|
|
InstrStage<1, [P440_FEXE5]>,
|
||
|
|
InstrStage<1, [P440_FEXE6]>,
|
||
|
|
InstrStage<1, [P440_FWB]>],
|
||
|
|
[6, 0, 0],
|
||
|
|
[P440_FPR_Bypass,
|
||
|
|
P440_FPR_Bypass, P440_FPR_Bypass]>,
|
||
|
|
InstrItinData<IIC_FPCompare, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
|
||
|
|
InstrStage<1, [P440_FRACC]>,
|
||
|
|
InstrStage<1, [P440_FEXE1]>,
|
||
|
|
InstrStage<1, [P440_FEXE2]>,
|
||
|
|
InstrStage<1, [P440_FEXE3]>,
|
||
|
|
InstrStage<1, [P440_FEXE4]>,
|
||
|
|
InstrStage<1, [P440_FEXE5]>,
|
||
|
|
InstrStage<1, [P440_FEXE6]>,
|
||
|
|
InstrStage<1, [P440_FWB]>],
|
||
|
|
[6, 0, 0],
|
||
|
|
[P440_FPR_Bypass, P440_FPR_Bypass,
|
||
|
|
P440_FPR_Bypass]>,
|
||
|
|
InstrItinData<IIC_FPDivD, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
|
||
|
|
InstrStage<1, [P440_FRACC]>,
|
||
|
|
InstrStage<1, [P440_FEXE1]>,
|
||
|
|
InstrStage<1, [P440_FEXE2]>,
|
||
|
|
InstrStage<1, [P440_FEXE3]>,
|
||
|
|
InstrStage<1, [P440_FEXE4]>,
|
||
|
|
InstrStage<1, [P440_FEXE5]>,
|
||
|
|
InstrStage<1, [P440_FEXE6]>,
|
||
|
|
InstrStage<25, [P440_FWB]>],
|
||
|
|
[31, 0, 0],
|
||
|
|
[NoBypass, P440_FPR_Bypass, P440_FPR_Bypass]>,
|
||
|
|
InstrItinData<IIC_FPDivS, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
|
||
|
|
InstrStage<1, [P440_FRACC]>,
|
||
|
|
InstrStage<1, [P440_FEXE1]>,
|
||
|
|
InstrStage<1, [P440_FEXE2]>,
|
||
|
|
InstrStage<1, [P440_FEXE3]>,
|
||
|
|
InstrStage<1, [P440_FEXE4]>,
|
||
|
|
InstrStage<1, [P440_FEXE5]>,
|
||
|
|
InstrStage<1, [P440_FEXE6]>,
|
||
|
|
InstrStage<13, [P440_FWB]>],
|
||
|
|
[19, 0, 0],
|
||
|
|
[NoBypass, P440_FPR_Bypass, P440_FPR_Bypass]>,
|
||
|
|
InstrItinData<IIC_FPFused, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
|
||
|
|
InstrStage<1, [P440_FRACC]>,
|
||
|
|
InstrStage<1, [P440_FEXE1]>,
|
||
|
|
InstrStage<1, [P440_FEXE2]>,
|
||
|
|
InstrStage<1, [P440_FEXE3]>,
|
||
|
|
InstrStage<1, [P440_FEXE4]>,
|
||
|
|
InstrStage<1, [P440_FEXE5]>,
|
||
|
|
InstrStage<1, [P440_FEXE6]>,
|
||
|
|
InstrStage<1, [P440_FWB]>],
|
||
|
|
[6, 0, 0, 0],
|
||
|
|
[P440_FPR_Bypass,
|
||
|
|
P440_FPR_Bypass, P440_FPR_Bypass,
|
||
|
|
P440_FPR_Bypass]>,
|
||
|
|
InstrItinData<IIC_FPRes, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
|
||
|
|
InstrStage<1, [P440_FRACC]>,
|
||
|
|
InstrStage<1, [P440_FEXE1]>,
|
||
|
|
InstrStage<1, [P440_FEXE2]>,
|
||
|
|
InstrStage<1, [P440_FEXE3]>,
|
||
|
|
InstrStage<1, [P440_FEXE4]>,
|
||
|
|
InstrStage<1, [P440_FEXE5]>,
|
||
|
|
InstrStage<1, [P440_FEXE6]>,
|
||
|
|
InstrStage<1, [P440_FWB]>],
|
||
|
|
[6, 0],
|
||
|
|
[P440_FPR_Bypass, P440_FPR_Bypass]>
|
||
|
|
]>;
|
||
|
|
|
||
|
|
// ===---------------------------------------------------------------------===//
|
||
|
|
// PPC440 machine model for scheduling and other instruction cost heuristics.
|
||
|
|
|
||
|
|
def PPC440Model : SchedMachineModel {
|
||
|
|
let IssueWidth = 2; // 2 instructions are dispatched per cycle.
|
||
|
|
let LoadLatency = 5; // Optimistic load latency assuming bypass.
|
||
|
|
// This is overriden by OperandCycles if the
|
||
|
|
// Itineraries are queried instead.
|
||
|
|
|
||
|
|
let CompleteModel = 0;
|
||
|
|
|
||
|
|
let Itineraries = PPC440Itineraries;
|
||
|
|
}
|
||
|
|
|