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69 lines
2.6 KiB
LLVM
69 lines
2.6 KiB
LLVM
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; RUN: opt -loop-vectorize -S < %s | FileCheck %s
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128-ni:1"
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target triple = "x86_64-unknown-linux-gnu"
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; PR34965/D39346
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; LV retains the original scalar loop intact as remainder loop. However,
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; after this transformation, analysis information concerning the remainder
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; loop may differ from the original scalar loop. This test is an example of
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; that behaviour, where values inside the remainder loop which SCEV could
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; originally analyze now require flow-sensitive analysis currently not
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; supported in SCEV. In particular, during LV code generation, after turning
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; the original scalar loop into the remainder loop, LV expected
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; Legal->isConsecutivePtr() to be consistent and return the same output as
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; during legal/cost model phases (original scalar loop). Unfortunately, that
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; condition was not satisfied because of the aforementioned SCEV limitation.
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; After D39346, LV code generation doesn't rely on Legal->isConsecutivePtr(),
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; i.e., SCEV. This test verifies that LV is able to handle the described cases.
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;
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; TODO: The SCEV limitation described before may affect plans to further
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; optimize the remainder loop of this particular test case. One tentative
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; solution is to detect the problematic IVs in LV (%7 and %8) and perform an
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; in-place IV optimization by replacing:
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; %8 = phi i32 [ %.ph2, %.outer ], [ %7, %6 ] with
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; with
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; %8 = sub i32 %7, 1.
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; Verify that store is vectorized as stride-1 memory access.
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; CHECK: vector.body:
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; CHECK: store <4 x i32>
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; Function Attrs: uwtable
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define void @test() {
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br label %.outer
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; <label>:1: ; preds = %2
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ret void
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; <label>:2: ; preds = %._crit_edge.loopexit
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%3 = add nsw i32 %.ph, -2
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br i1 undef, label %1, label %.outer
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.outer: ; preds = %2, %0
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%.ph = phi i32 [ %3, %2 ], [ 336, %0 ]
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%.ph2 = phi i32 [ 62, %2 ], [ 110, %0 ]
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%4 = and i32 %.ph, 30
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%5 = add i32 %.ph2, 1
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br label %6
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; <label>:6: ; preds = %6, %.outer
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%7 = phi i32 [ %5, %.outer ], [ %13, %6 ]
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%8 = phi i32 [ %.ph2, %.outer ], [ %7, %6 ]
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%9 = add i32 %8, 2
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%10 = zext i32 %9 to i64
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%11 = getelementptr inbounds i32, i32 addrspace(1)* undef, i64 %10
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%12 = ashr i32 undef, %4
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store i32 %12, i32 addrspace(1)* %11, align 4
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%13 = add i32 %7, 1
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%14 = icmp sgt i32 %13, 61
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br i1 %14, label %._crit_edge.loopexit, label %6
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._crit_edge.loopexit: ; preds = %._crit_edge.loopexit, %6
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br i1 undef, label %2, label %._crit_edge.loopexit
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}
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