diff --git a/docs/x86/optable.xml b/docs/x86/optable.xml
index 61076e1..16a63cc 100644
--- a/docs/x86/optable.xml
+++ b/docs/x86/optable.xml
@@ -842,7 +842,21 @@
         <mnemonic>cmpxchg8b</mnemonic>
         <def>
             <pfx>aso rexr rexx rexb</pfx>
-            <opc>0f c7 /reg=1</opc>
+            <opc>0f c7 /reg=1 /o=16</opc>
+            <opr>M</opr>
+        </def>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f c7 /reg=1 /o=32</opc>
+            <opr>M</opr>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>cmpxchg16b</mnemonic>
+        <def>
+            <pfx>aso rexr rexx rexb</pfx>
+            <opc>0f c7 /reg=1 /o=64</opc>
             <opr>M</opr>
         </def>
     </instruction>
@@ -5627,7 +5641,7 @@
         <def>
             <pfx>aso rexx rexr rexb</pfx>
             <opc>/sse=66 0f 3a 15</opc>
-            <opr>MwRv V Ib</opr>
+            <opr>MwRd V Ib</opr>
         </def>
     </instruction>
 
diff --git a/libudis86/decode.h b/libudis86/decode.h
index 85ce376..a7362c8 100644
--- a/libudis86/decode.h
+++ b/libudis86/decode.h
@@ -122,6 +122,7 @@ enum ud_operand_size {
      */
     SZ_BD  = (SZ_B << 8) | SZ_D,
     SZ_BV  = (SZ_B << 8) | SZ_V,
+    SZ_WD  = (SZ_W << 8) | SZ_D,
     SZ_WV  = (SZ_W << 8) | SZ_V,
     SZ_WY  = (SZ_W << 8) | SZ_Y,
     SZ_DY  = (SZ_D << 8) | SZ_Y,
diff --git a/scripts/ud_itab.py b/scripts/ud_itab.py
index 84ee309..b17fe69 100644
--- a/scripts/ud_itab.py
+++ b/scripts/ud_itab.py
@@ -61,6 +61,7 @@ class UdItabGenerator( ud_opcode.UdOpcodeTables ):
         "MbRd"     : [    "OP_MR"       , "SZ_BD"    ],
         "MbRv"     : [    "OP_MR"       , "SZ_BV"    ],
         "MwRv"     : [    "OP_MR"       , "SZ_WV"    ],
+        "MwRd"     : [    "OP_MR"       , "SZ_WD"    ],
         "MwRy"     : [    "OP_MR"       , "SZ_WY"    ],
         "MdRy"     : [    "OP_MR"       , "SZ_DY"    ],
         "I1"       : [    "OP_I1"       , "SZ_NA"    ],
diff --git a/tests/oprgen.py b/tests/oprgen.py
index aec5cb4..9ab7634 100644
--- a/tests/oprgen.py
+++ b/tests/oprgen.py
@@ -435,6 +435,9 @@ class UdTestGenerator( ud_opcode.UdOpcodeTables ):
     def Insn_MwRv(self):
         return [self.Opr_MwRv(cast=True)]
 
+    def Insn_MwRd_V_Ib(self):
+        return [self.Opr_MwRd(cast=False), self.Opr_V(), self.Opr_Ib()]
+
     def Insn_S_MwRv(self):
         if self.mode == 64:
             return [self.Opr_S(), self.Opr_MwRd(cast=False)]