mirror of
https://github.com/ModOrganizer2/udis86.git
synced 2026-07-27 14:05:57 -07:00
Use standard notation for sse opcode extension (/sse=66,f3,f2)
This commit is contained in:
Vivek Thampi
+66
-60
@@ -37,6 +37,8 @@ class UdOpcodeTables:
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'/o' : { 'name' : 'UD_TAB__OPC_OSIZE', 'size' : 3 },
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'/3dnow' : { 'name' : 'UD_TAB__OPC_3DNOW', 'size' : 256 },
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'vendor' : { 'name' : 'UD_TAB__OPC_VENDOR', 'size' : 3 },
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'/vex.p' : { 'name' : 'UD_TAB__OPC_VEX_P', 'size' : 4 },
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'/vex.m' : { 'name' : 'UD_TAB__OPC_VEX_M', 'size' : 3 },
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}
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OpcodeTable0 = {
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@@ -72,14 +74,27 @@ class UdOpcodeTables:
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'amd' : '00',
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'intel' : '01',
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'any' : '02'
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}
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},
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'vex.p': {
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'none' : '00',
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'f2' : '01',
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'f3' : '02',
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'66' : '03'
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},
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'vex.m': {
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'none' : '00',
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'38' : '01',
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'3a' : '02',
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},
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}
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InsnTable = []
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MnemonicsTable = []
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ThreeDNowTable = {}
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def sizeOfTable( self, t ):
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return self.TableInfo[ t ][ 'size' ]
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@@ -96,7 +111,7 @@ class UdOpcodeTables:
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table[ 'entries' ][ index ] = { 'type' : type, 'entries' : {}, 'meta' : meta }
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if table[ 'entries' ][ index ][ 'type' ] != type:
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raise NameError( "error: violation in opcode mapping (overwrite) %s with %s." %
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( table[ 'entries' ][ index ][ 'type' ], type) )
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( table[ 'entries' ][ index ], type) )
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return table[ 'entries' ][ index ]
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class Insn:
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@@ -118,73 +133,59 @@ class UdOpcodeTables:
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'/o' : lambda v: "%02x" % (int(v) / 32),
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'/a' : lambda v: "%02x" % (int(v) / 32),
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'/m' : lambda v: '00' if v == '!64' else '01',
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'/sse' : lambda v: UdOpcodeTables.OpcExtIndex['sse'][v]
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# SSE
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'/sse' : lambda v: UdOpcodeTables.OpcExtIndex['sse'][v],
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# AVX
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'/vex.p' : lambda v: UdOpcodeTables.OpcExtIndex['vex.p'][v],
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'/vex.m' : lambda v: UdOpcodeTables.OpcExtIndex['vex.m'][v]
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}
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def __init__(self, prefixes, mnemonic, opcodes, operands, vendor):
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self.opcodes = opcodes
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self.opcodes = []
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self.prefixes = prefixes
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self.mnemonic = mnemonic
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self.operands = operands
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self.vendor = vendor
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self.opcext = {}
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ssePrefix = None
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if self.opcodes[0] in ('ssef2', 'ssef3', 'sse66'):
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ssePrefix = self.opcodes[0][3:]
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self.opcodes.pop(0)
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# artificially add a /sse=none for 2 byte opcodes
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if opcodes[0] == '0f' and opcodes[1] != '0f':
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opcodes.append('/sse=none')
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# do some preliminary decoding of the instruction type
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# 1byte, 2byte or 3byte instruction?
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self.nByteInsn = 1
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if self.opcodes[0] == '0f': # 2byte
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# 2+ byte opcodes are always disambiguated by an
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# sse prefix, unless it is a 3d now instruction
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# which is 0f 0f ...
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if self.opcodes[1] != '0f' and ssePrefix is None:
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ssePrefix = 'none'
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if self.opcodes[1] in ('38', '3a'): # 3byte
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self.nByteInsn = 3
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else:
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self.nByteInsn = 2
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# The opcode that indexes into the opcode table.
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self.opcode = self.opcodes[self.nByteInsn - 1]
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# Record opcode extensions
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for opcode in self.opcodes[self.nByteInsn:]:
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arg, val = opcode.split('=')
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self.opcext[arg] = self.OpcExtMap[arg](val)
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# begin the list with all plain opcodes
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for opc in opcodes:
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if not opc.startswith('/'):
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self.opcodes.append(opc)
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# Record sse extension: the reason sse extension is handled
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# separately is that historically sse was handled as a first
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# class opcode, not as an extension. Now that sse is handled
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# as an extension, we do the manual conversion here, as opposed
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# to modifying the opcode xml file.
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if ssePrefix is not None:
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self.opcext['/sse'] = self.OpcExtMap['/sse'](ssePrefix)
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# re-order vex/xop prefixes to follow vex opcode
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if self.opcodes[0] == 'c4' or self.opcodes[0] == 'c5':
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for opc in opcodes:
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if opc.startswith('/vex'):
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self.opcodes.insert(1, opc)
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# Add extensions. The order is important, and determines how
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# well the opcode table is packed. Also note, /sse must be
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# before /o, because /sse may consume operand size prefix
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# affect the outcome of /o.
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for ext in ('/mod', '/x87', '/reg', '/rm', '/sse',
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'/o', '/a', '/m', '/3dnow'):
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for opc in opcodes:
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if opc.startswith(ext):
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self.opcodes.append(opc)
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def parse(self, table, insn):
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# Walk down the tree, create levels as needed
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assert not insn.opcodes[0].startswith("/")
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index = insn.opcodes[0];
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if insn.nByteInsn > 1:
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assert index == '0f'
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table = self.updateTable(table, index, 'opctbl', '0f')
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index = insn.opcodes[1]
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if insn.nByteInsn == 3:
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table = self.updateTable(table, index, 'opctbl', index)
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index = insn.opcodes[2]
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# Walk down the tree, create levels as needed, for opcode
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# extensions. The order is important, and determines how
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# well the opcode table is packed. Also note, /sse must be
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# before /o, because /sse may consume operand size prefix
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# affect the outcome of /o.
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for ext in ('/mod', '/x87', '/reg', '/rm', '/sse',
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'/o', '/a', '/m', '/3dnow'):
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if ext in insn.opcext:
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for opc in insn.opcodes[1:]:
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if opc.startswith('/'):
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ext, v= opc.split('=')
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table = self.updateTable(table, index, ext, ext)
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index = insn.opcext[ext]
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index = insn.OpcExtMap[ext](v)
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insn.opcext[ext] = index
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else:
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table = self.updateTable(table, index, 'opctbl', index)
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index = opc
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# additional table for disambiguating vendor
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if len(insn.vendor):
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@@ -200,10 +201,11 @@ class UdOpcodeTables:
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# add instruction to linear table of instruction forms
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self.InsnTable.append({ 'prefixes' : insn.prefixes,
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'opcext' : insn.opcext,
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'mnemonic' : insn.mnemonic,
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'operands' : insn.operands,
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'vendor' : insn.vendor })
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'vendor' : insn.vendor,
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'opcext' : insn.opcext,
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'opcodes' : insn.opcodes })
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# add mnemonic to mnemonic table
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if not insn.mnemonic in self.MnemonicsTable:
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@@ -217,7 +219,11 @@ class UdOpcodeTables:
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opcodes=opcodes,
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operands=operands,
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vendor=vendor)
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self.parse(self.OpcodeTable0, insn)
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try:
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self.parse(self.OpcodeTable0, insn)
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except:
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self.print_tree()
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raise
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def print_table( self, table, pfxs ):
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print("%s |" % pfxs)
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@@ -227,7 +233,7 @@ class UdOpcodeTables:
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for idx in keys:
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e = table[ 'entries' ][ idx ]
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if e[ 'type' ] == 'insn':
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print("%s |-<%s>" % ( pfxs, idx ),)
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print("%s |-<%s>" % ( pfxs, idx )),
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print("%s %s" % ( e[ 'mnemonic' ], ' '.join( e[ 'operands'] ) ))
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else:
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print("%s |-<%s> %s" % ( pfxs, idx, e['type'] ))
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