diff --git a/docs/assets/img/product_pics/core/minicore/m5stickv/m5stickv_mpu6886_sch.webp b/docs/assets/img/product_pics/core/minicore/m5stickv/m5stickv_mpu6886_sch.webp new file mode 100644 index 00000000..d874c838 Binary files /dev/null and b/docs/assets/img/product_pics/core/minicore/m5stickv/m5stickv_mpu6886_sch.webp differ diff --git a/docs/assets/img/product_pics/unit/trace_sch.webp b/docs/assets/img/product_pics/unit/trace_sch.webp index 41fb953e..41666a47 100644 Binary files a/docs/assets/img/product_pics/unit/trace_sch.webp and b/docs/assets/img/product_pics/unit/trace_sch.webp differ diff --git a/docs/en/core/m5stickv.md b/docs/en/core/m5stickv.md index 109b7c95..73ddfb6e 100644 --- a/docs/en/core/m5stickv.md +++ b/docs/en/core/m5stickv.md @@ -350,6 +350,13 @@ The chip contains a high-performance, low power RISC-V ISA-based dual core 64-bi - Wake-on-motion interrupt for low power operation of applications processor - Self-test +#### SPI/I2C dual communication mode + +- In the latest version of M5StickV circuit design, MPU6886 supports the user to configure its communication mode to SPI or I2C. When in use, the mode can be switched by switching the CS pin level (high level 1 is I2C mode, low level 0 is (SPI mode) +- The specific pin mapping is shown below: + + + ## Links - **datasheet** @@ -375,6 +382,30 @@ The chip contains a high-performance, low power RISC-V ISA-based dual core 64-bi - [V-Training](https://docs.m5stack.com/#/en/related_documents/v-training) +## Version Change + + + + + + + + + + + + + + + + + + + + + +
Release DateProduct ChangeNote:
2017.7Initial public release/
2020.3The circuit supports configuring MPU6886 to use SPI or I2C protocol for communication.Program to drive the chip select pin CS for modification, high level 1 is I2C mode, low level 0 is SPI mode.
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