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@@ -350,6 +350,13 @@ The chip contains a high-performance, low power RISC-V ISA-based dual core 64-bi
- Wake-on-motion interrupt for low power operation of applications processor
- Self-test
+#### SPI/I2C dual communication mode
+
+- In the latest version of M5StickV circuit design, MPU6886 supports the user to configure its communication mode to SPI or I2C. When in use, the mode can be switched by switching the CS pin level (high level 1 is I2C mode, low level 0 is (SPI mode)
+- The specific pin mapping is shown below:
+
+
+
## Links
- **datasheet**
@@ -375,6 +382,30 @@ The chip contains a high-performance, low power RISC-V ISA-based dual core 64-bi
- [V-Training](https://docs.m5stack.com/#/en/related_documents/v-training)
+## Version Change
+
+
| Release Date | +Product Change | +Note: | +
|---|---|---|
| 2017.7 | +Initial public release | +/ | +
| 2020.3 | +The circuit supports configuring MPU6886 to use SPI or I2C protocol for communication. | +Program to drive the chip select pin CS for modification, high level 1 is I2C mode, low level 0 is SPI mode. | +