From b0597ba37c094093760b7812b78f53b96b670601 Mon Sep 17 00:00:00 2001 From: Sean <1026025056@qq.com> Date: Tue, 2 Mar 2021 19:09:07 +0800 Subject: [PATCH] add 4relay and bugc protocol --- docs/en/atom/atom_motion.md | 3 +- docs/en/hat/hat-bugc.md | 32 +++++++++++- docs/en/unit/4relay.md | 21 ++++++++ docs/en/unit/dds.md | 74 ++++++++++++++-------------- docs/zh_CN/atom/atom_motion.md | 3 +- docs/zh_CN/hat/hat-bugc.md | 32 ++++++++++++ docs/zh_CN/module/comx_lorawan470.md | 13 +++-- docs/zh_CN/module/comx_lorawan915.md | 2 +- docs/zh_CN/unit/4relay.md | 21 ++++++++ docs/zh_CN/unit/dds.md | 64 ++++++++++++------------ 10 files changed, 189 insertions(+), 76 deletions(-) diff --git a/docs/en/atom/atom_motion.md b/docs/en/atom/atom_motion.md index 1cef4a3b..c415e4ba 100644 --- a/docs/en/atom/atom_motion.md +++ b/docs/en/atom/atom_motion.md @@ -109,8 +109,9 @@ ATOM MotionPORT-B(Black)PORT-C(Blue) -## I2C register +## Protocol +- Protocol type I2C - I2C Address: **0x38** diff --git a/docs/en/hat/hat-bugc.md b/docs/en/hat/hat-bugc.md index 638544b6..b7af6e87 100644 --- a/docs/en/hat/hat-bugc.md +++ b/docs/en/hat/hat-bugc.md @@ -77,13 +77,43 @@ The Bugc base needs to be used in conjunction with the M5StickC controller. The >2. After downloading the software, double-click to run the application, connect the M5 device to the computer through the data cable, select the port parameters, click **"Burn"** to burn the program (**For M5StickC, set the baud rate to 750000 or 115200**) -### 管脚映射 +## PinMap
M5StickCGPIO0GPIO263.3VGNDBAT
BugCSDASCL3.3VGNDBAT
+## Protocol + +- Protocol type I2C +- I2C Address: **0x38** + +```clike +/*--------------------------------------------------------------------------------------------------*/ +| MOTOR SPEED REG | 0x00 +| ------------------------------------------------------------------------------------------------ +| FRONT_LEFT_reg[0] | R/W | FRONT_LEFT SPEED +| FRONT_RIGHT_reg[1] | R/W | FRONT_RIGHT SPEED +| REAR_LEFT_reg[2] | R/W | REAR_LEFT SPEED +| REAR_RIGHT_reg[2] | R/W | REAR_RIGHT SPEED +/*---------------------------------------------------------------------------------------------------- + +/*--------------------------------------------------------------------------------------------------*/ +| RGB LED COLOR REG | 0x10 +| ------------------------------------------------------------------------------------------------ +| left/right_reg[0] | R/W | left/right control + | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | + | R | R | R | R | R | R | R | SELECT | + | -SELECT: 0 FRONT_LEFT RGB LED + | 1 FRONT_RIGHT RGB LED +| rgb_r_reg[1] | R/W | RED value +| rgb_g_reg[2] | R/W | Green value +| rgb_b_reg[2] | R/W | Blue value +/*---------------------------------------------------------------------------------------------------- + +``` + ## Example ### 1. Arduino diff --git a/docs/en/unit/4relay.md b/docs/en/unit/4relay.md index 7c80560c..2f06958c 100644 --- a/docs/en/unit/4relay.md +++ b/docs/en/unit/4relay.md @@ -103,6 +103,27 @@ 4-relay UnitSDASCL5VGND +## Protocol + +- Protocol type I2C +- I2C Address: **0x26** + +```clike +/*-----------------------------------------------------------------------------*/ +|RELAY control reg | 0x10 +|----------------------------------------------------------------------------- +|Relay_ctrl_mode_reg[0] | R/W | System control + | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | + | R | R | R | R | R | R | R | Sync Mode | + | -Sync Mode:0 LED&Relay Async + | -Sync Mode:1 LED&Relay Sync +//--------------------------------------------------------------------------------- +|Relay_ctrl_mode_reg[1] | R/W | Relay & LED control + | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | + | LED1| LED2| LED3| LED4| RLY1| RLY2| RLY3| RLY4| +/*-------------------------------------------------------------------------------*/ +``` + ## Example ### 1. Arduino diff --git a/docs/en/unit/dds.md b/docs/en/unit/dds.md index 68ebb482..9bad2c49 100644 --- a/docs/en/unit/dds.md +++ b/docs/en/unit/dds.md @@ -126,55 +126,55 @@ It supports deep sleep mode, which can reduce the power consumption in the idle DDS UnitGPIO22GPIO215VGND -## I2C register +## Protocol +- Protocol type I2C - I2C Address: **0x31** >When writing a register, the highest bit must be set to 1. The mclk is set to "1" by default, it will keep the last output signal magnitude. Once the DAC is set to 1, it stops the Unit output. -``` -/*------------------------------------------------ -------------------------------------------------- */ -// | DDS CTRL REG | 0x20 -// | ----------------------------------------------- ------------------------------------------------- -// | dds_ctrl_reg[0] | R/W | System control -// | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | -// | W | R | R | R | R | MODE | +```clike +/*--------------------------------------------------------------------------------------------------*/ + | DDS CTRL REG | 0x20 + | ------------------------------------------------------------------------------------------------ + | dds_ctrl_reg[0] | R/W | System control + | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | + | W | R | R | R | R | MODE | + + | -MODE: 000 Reserved + | 001 SINUS + | 010 TRIANGLE + | 011 SQUARE + | 100 SAWTOOTH + | 101 DC // -// | -MODE: 000 Reserved -// | 001 SINUS -// | 010 TRIANGLE -// | 011 SQUARE -// | 100 SAWTOOTH -// | 101 DC -// -// | dds_ctrl_reg[1] | R/W | System control -// | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | -// | W | FSELECT | PSELECT | S01 | S12 | RSET | R | R | -// -// | -FSELECT: 0 Used FREQ0 -// 1 Used FREQ1 -// | -PSELECT: 0 Used PHASE0 -// 1 Used PHASE1 -// | -SLEEP01: 1 Disenable mclk -// | -SLEEP12: 1 Disenable DAC -/*------------------------------------------------ -------------------------------------------------- - + | dds_ctrl_reg[1] | R/W | System control + | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | + | W | FSELECT | PSELECT | S01 | S12 | RSET | R | R | + + | -FSELECT: 0 Used FREQ0 + 1 Used FREQ1 + | -PSELECT: 0 Used PHASE0 + 1 Used PHASE1 + | -SLEEP01: 1 Disenable mclk + | -SLEEP12: 1 Disenable DAC +/*---------------------------------------------------------------------------------------------------- -/*------------------------------------------------ -------------------------------------------------- */ -// | DDS FREQ PHASE REG | 0x30 -// | ----------------------------------------------- ------------------------------------------------- - // | dds_freq_phase_reg[0:3] | R/W | FREQ(28bit) - // | 31 | 30 | 29:28 | 27:0 | - // | W | N | R | freq reg 0 | +/*--------------------------------------------------------------------------------------------------*/ + | DDS FREQ PHASE REG | 0x30 + | ------------------------------------------------------------------------------------------------ + | dds_freq_phase_reg[0:3] | R/W | FREQ(28bit) + | 31 | 30 | 29:28 | 27:0 | + | W | N | R | freq reg 0 | // - // | dds_freq_phase_reg[4:5] | R/W | PHASE(12bit) - // | 15 | 14 | 13:12 | 11:0 | - // | W | N | R | phase reg 1 | + | dds_freq_phase_reg[4:5] | R/W | PHASE(12bit) + | 15 | 14 | 13:12 | 11:0 | + | W | N | R | phase reg 1 | // -/*------------------------------------------------ -------------------------------------------------- -*/ +/*---------------------------------------------------------------------------------------------------*/ ``` -