Files
imliubo fee405adf5 boards: add M5Stack CoreS3 board support
Add a complete board package for the M5Stack CoreS3 under
application/basic_demo/boards/m5stack_cores3/, so basic_demo can be
built and flashed on CoreS3 with:

  idf.py gen-bmgr-config -c ./boards -b m5stack_cores3
  idf.py build flash monitor

Highlights:

* board_info.yaml / board_peripherals.yaml / board_devices.yaml
  describe the CoreS3 hardware for esp_board_manager:
    - I2C0 (SDA=12, SCL=11) for AXP2101, AW9523B, AW88298, ES7210, FT5x06
    - I2S0 48 kHz stereo (MCLK=0, BCLK=34, WS=33, DOUT=13, DIN=14)
    - SPI2 (MOSI=37, MISO=35, SCLK=36) for the ILI9341 LCD
    - GPIO46 for AW88298 PA enable
    - ILI9341 SPI panel (320x240, BGR, big-endian, color inverted)
    - FT5x06 I2C touch
    - AW9523B GPIO expander with the output mask required by CoreS3
      (incl. pin 1 BUS_EN and pin 15 BOOST_EN for the Grove 5V rail)

* power_manager.[ch]: custom AXP2101 power manager that brings up
  SD / Speaker / LCD / Touch / Grove 5V in order, configures the
  AXP rails (ALDO1/2/3/4 and DLDO1 for the LCD backlight), and
  exposes cores3_power_manager_enable() for runtime control.

* setup_device.c: factory entries for the AW9523B expander, the
  ILI9341 LCD panel and the FT5x06 touch panel. The expander setup
  programs GCR=0x10 (P0 push-pull) and LEDMODE0/1=0xFF so every
  P0/P1 pin leaves the power-on LED constant-current mode and acts
  as a real GPIO; without this, set_level(high) only releases the
  current sink and cannot drive enables such as BUS_EN/BOOST_EN, so
  the Grove port stays at 0 V.

* components/esp_io_expander_aw9523b/: minimal AW9523B driver
  (16 IOs, push-pull / LED mode register definitions, raw register
  write helper) used by the board package.

* sdkconfig.defaults.board:
    - 16 MB QIO flash @ 80 MHz
    - 8 MB Quad PSRAM @ 80 MHz with XIP / instr / rodata in PSRAM
      disabled (octal-only on ESP32-S3)
    - CONFIG_FREERTOS_TASK_CREATE_ALLOW_EXT_MEM=n so claw tasks
      tagged CLAW_TASK_STACK_PREFER_PSRAM fall back to internal
      RAM, avoiding the cache-disabled stack-sanity assert that
      Quad PSRAM triggers during SPI flash transactions.

Signed-off-by: imliubo <imliubo@makingfun.xyz>
2026-04-22 12:16:05 +08:00
..
2026-04-03 15:48:11 +08:00