diff --git a/README.md b/README.md index b9ee234..5574238 100644 --- a/README.md +++ b/README.md @@ -81,21 +81,28 @@ configurations: how Device Tree files generated by CubeMX can be integrated in a Buildroot configuration. -| Feature | st_stm32mp157*_dk1 | st_stm32mp157*_dk2 | st_stm32mp157*_dk1_demo | st_stm32mp157*_dk2_demo | st_stm32mp135f_dk | st_stm32mp135f_dk_demo | -| ------- | ------------------ | ------------------ | ----------------------- | ----------------------- | ----------------------- | ----------------------- | -| TF-A | v2.8-stm32mp-r1.1 | v2.8-stm32mp-r1.1 | v2.8-stm32mp-r1.1 | v2.8-stm32mp-r1.1 | v2.8-stm32mp-r1.1 | v2.8-stm32mp-r1.1 | -| U-Boot | v2022.10-stm32mp-r1.1 | v2022.10-stm32mp-r1.1 | v2022.10-stm32mp-r1.1 | v2022.10-stm32mp-r1.1 | v2022.10-stm32mp-r1.1 | v2022.10-stm32mp-r1.1 | -| Linux | v6.1-stm32mp-r1.1 | v6.1-stm32mp-r1.1 | v6.1-stm32mp-r1.1 | v6.1-stm32mp-r1.1 | v6.1-stm32mp-r1.1 | v6.1-stm32mp-r1.1 | -| OP-TEE | 3.19.0-stm32mp-r1.1 | 3.19.0-stm32mp-r1.1 | 3.19.0-stm32mp-r1.1 | 3.19.0-stm32mp-r1.1 | 3.19.0-stm32mp-r1.1 | 3.19.0-stm32mp-r1.1 | -| Qt5 | No | No | Yes | Yes | No | Yes | -| OpenGL | No | No | Yes | Yes | No | Yes | -| WiFi | N/A | No | N/A | Yes | No | Yes | -| Bluetooth | N/A | No | N/A | Yes | No | Yes | -| Audio | No | No | Yes | Yes | N/A | N/A | -| Video | N/A | N/A | N/A | N/A | No | Yes | -| CubeMX Device Tree | No | No | Yes | Yes | No | Yes | -| Cortex M4 Firmware examples | No | No | Yes | Yes | N/A | N/A | -| RAUC OTA | No | No | Yes | Yes | No | Yes | +11. `m5stack_core135_defconfig`, which is a more feature-ful + configuration to support the [STM32MP135F Discovery Kit](https://wiki.st.com/stm32mpu/wiki/STM32MP13_microprocessor) + board. It has support for OpenGL and Qt5 for graphics, for OP-TEE + as a Trusted Execution Environment, for RAUC for OTA. It also shows + how Device Tree files generated by CubeMX can be integrated in a + Buildroot configuration. + +| Feature | st_stm32mp157*_dk1 | st_stm32mp157*_dk2 | st_stm32mp157*_dk1_demo | st_stm32mp157*_dk2_demo | st_stm32mp135f_dk | st_stm32mp135f_dk_demo | m5stack_core135 | +| ------- | ------------------ | ------------------ | ----------------------- | ----------------------- | ----------------------- | ----------------------- | ----------------------- | +| TF-A | v2.8-stm32mp-r1.1 | v2.8-stm32mp-r1.1 | v2.8-stm32mp-r1.1 | v2.8-stm32mp-r1.1 | v2.8-stm32mp-r1.1 | v2.8-stm32mp-r1.1 | v2.8-stm32mp-r1.1 | +| U-Boot | v2022.10-stm32mp-r1.1 | v2022.10-stm32mp-r1.1 | v2022.10-stm32mp-r1.1 | v2022.10-stm32mp-r1.1 | v2022.10-stm32mp-r1.1 | v2022.10-stm32mp-r1.1 | v2022.10-stm32mp-r1.1 | +| Linux | v6.1-stm32mp-r1.1 | v6.1-stm32mp-r1.1 | v6.1-stm32mp-r1.1 | v6.1-stm32mp-r1.1 | v6.1-stm32mp-r1.1 | v6.1-stm32mp-r1.1 | v6.1-stm32mp-r1.1 | +| OP-TEE | 3.19.0-stm32mp-r1.1 | 3.19.0-stm32mp-r1.1 | 3.19.0-stm32mp-r1.1 | 3.19.0-stm32mp-r1.1 | 3.19.0-stm32mp-r1.1 | 3.19.0-stm32mp-r1.1 | 3.19.0-stm32mp-r1.1 | +| Qt5 | No | No | Yes | Yes | No | Yes | Yes | +| OpenGL | No | No | Yes | Yes | No | Yes | Yes | +| WiFi | N/A | No | N/A | Yes | No | Yes | NO | +| Bluetooth | N/A | No | N/A | Yes | No | Yes | NO | +| Audio | No | No | Yes | Yes | N/A | N/A | N/A | +| Video | N/A | N/A | N/A | N/A | No | Yes | Yes | +| CubeMX Device Tree | No | No | Yes | Yes | No | Yes | Yes | +| Cortex M4 Firmware examples | No | No | Yes | Yes | N/A | N/A | N/A | +| RAUC OTA | No | No | Yes | Yes | No | Yes | No | Note that upstream Buildroot also contains pre-defined configurations for STM32MP1 platforms, but they use the upstream versions of TF-A, diff --git a/board/m5stack/core135/flash.tsv b/board/m5stack/core135/flash.tsv new file mode 100644 index 0000000..33637ba --- /dev/null +++ b/board/m5stack/core135/flash.tsv @@ -0,0 +1,4 @@ +#opt Id Name Type Device Offset Binary +- 0x01 fsbl_boot Binary none 0x0 %ATFBIN% +- 0x03 fip_boot Binary none 0x0 fip.bin +P 0x10 sdcard RawImage mmc0 0x0 sdcard.img diff --git a/board/m5stack/core135/genimage.cfg b/board/m5stack/core135/genimage.cfg new file mode 100644 index 0000000..97f092c --- /dev/null +++ b/board/m5stack/core135/genimage.cfg @@ -0,0 +1,26 @@ +image sdcard.img { + hdimage { + partition-table-type = "gpt" + } + + partition fsbl1 { + image = "%ATFBIN%" + } + + partition fsbl2 { + image = "%ATFBIN%" + } + + partition fip { + image = "fip.bin" + } + + partition u-boot-env { + size = 2M + } + + partition rootfs { + image = "rootfs.ext4" + bootable = "yes" + } +} diff --git a/board/m5stack/core135/linux-disable-etnaviv.config b/board/m5stack/core135/linux-disable-etnaviv.config new file mode 100644 index 0000000..e9f67ce --- /dev/null +++ b/board/m5stack/core135/linux-disable-etnaviv.config @@ -0,0 +1 @@ +# CONFIG_DRM_ETNAVIV is not set diff --git a/board/m5stack/core135/linux-dts/stm32mp135f-core135.dts b/board/m5stack/core135/linux-dts/stm32mp135f-core135.dts new file mode 100644 index 0000000..efafe12 --- /dev/null +++ b/board/m5stack/core135/linux-dts/stm32mp135f-core135.dts @@ -0,0 +1,1286 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2021 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include "stm32mp135.dtsi" +#include "stm32mp13xf.dtsi" +#include "stm32mp13-pinctrl.dtsi" + +/ { + model = "STMicroelectronics STM32MP135F-DK Discovery Board"; + compatible = "st,stm32mp135f-dk", "st,stm32mp135"; + + aliases { + ethernet0 = ð1; + ethernet1 = ð2; + serial0 = &usart6; + serial1 = &usart1; + serial2 = &uart8; + serial3 = &usart3; // rs485 + + i2c0 = &i2c3; + i2c1 = &i2c5; + + i2c2 = &i2c1; + i2c3 = &i2c2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + framebuffer { + compatible = "simple-framebuffer"; + clocks = <&rcc LTDC_PX>; + status = "disabled"; + }; + }; + + clocks { + }; + + memory@c0000000 { + device_type = "memory"; + reg = <0xc0000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + optee@dd000000 { + reg = <0xdd000000 0x3000000>; + no-map; + }; + }; + + + panel_rgb: panel-rgb { + compatible = "panel-dpi"; + power-supply = <&scmi_v3v3_sw>; + data-mapping = "rgb24"; + status = "okay"; + // 1920×1080 + width-mm = <320>; + height-mm = <180>; + port { + panel_in_rgb: endpoint { + remote-endpoint = <<dc_out_rgb>; + }; + }; + // CEA-861: https://tomverbeure.github.io/video_timings_calculator + panel-timing { + clock-frequency = <74250000>; + hactive = <1280>; + vactive = <720>; + hsync-len = <40>; + hfront-porch = <110>; + hback-porch = <220>; + vsync-len = <5>; + vfront-porch = <5>; + vback-porch = <20>; + + hsync-active = <0>; + vsync-active = <0>; + + de-active = <1>; + pixelclk-active = <1>; + }; + }; + + v3v3_ao: v3v3-ao { + compatible = "regulator-fixed"; + regulator-name = "v3v3_ao"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + v3v3_touch: v3v3_touch { + compatible = "regulator-fixed"; + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + v1v8_audio: regulator-v1v8_audio { + compatible = "regulator-fixed"; + regulator-name = "v1v8_audio"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + sound { + compatible = "audio-graph-card"; + label = "STM32MP135F-DK"; + dais = <&sai1a_port &sai1b_port>; + status = "okay"; + }; + + OutToPins_codec: OutToPins_codec@0 { + compatible = "OutToPins_codec"; + #reg = <0>; + #sound-dai-cells = <0>; + clocks = <&sai1a>; + clock-names = "MCLK"; + status = "okay"; + + OutToPins_port: port { + #address-cells = <1>; + #size-cells = <0>; + + OutToPins_tx0_endpoint: endpoint@0 { + reg = <0>; + remote-endpoint = <&sai1a_endpoint>; + }; + + OutToPins_tx1_endpoint: endpoint@1 { + reg = <1>; + remote-endpoint = <&sai1b_endpoint>; + }; + }; + }; +}; + +&sai1 { + clocks = <&rcc SAI1>, <&scmi_clk CK_SCMI_PLL3_Q>, <&scmi_clk CK_SCMI_PLL3_R>; + clock-names = "pclk", "x8k", "x11k"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sai1a_pins_mx>, <&sai1b_pins_mx>; + pinctrl-1 = <&sai1a_sleep_pins_mx>, <&sai1b_sleep_pins_mx>; + status = "okay"; +}; + +&sai1a{ + #clock-cells = <0>; + dma-names = "tx"; + status = "okay"; + + sai1a_port: port { + sai1a_endpoint: endpoint { + remote-endpoint = <&OutToPins_tx0_endpoint>; + format = "i2s"; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + }; + }; +}; + +&sai1b{ + #clock-cells = <0>; + dma-names = "tx"; + status = "okay"; + + sai1b_port: port { + sai1b_endpoint: endpoint { + remote-endpoint = <&OutToPins_tx1_endpoint>; + format = "i2s"; + dai-tdm-slot-num = <2>; + dai-tdm-slot-width = <32>; + }; + }; +}; + +&crc1 { + status = "okay"; +}; + +&cryp { + status = "okay"; +}; + +&dts { + status = "okay"; +}; + +ð1 { + status = "okay"; + pinctrl-0 = <ð1_pins_mx>; + pinctrl-1 = <ð1_sleep_pins_mx>; + pinctrl-names = "default", "sleep"; + phy-mode = "rgmii-id"; + max-speed = <1000>; + nvmem-cells = <ðernet_mac1_address>; + nvmem-cell-names = "mac-address"; + phy-handle = <&rtl8211f_eth1>; + st,eth-clk-sel; + mdio1 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + rtl8211f_eth1: ethernet-phy@0 { + compatible = "ethernet-phy-id001c.c916"; + reg = <0>; + reset-assert-us = <10000>; + reset-deassert-us = <30000>; + reset-gpios = <&gpioa 10 GPIO_ACTIVE_LOW>; + realtek,clkout-disable; + }; + }; +}; + +ð2 { + status = "okay"; + pinctrl-0 = <ð2_pins_mx>; + pinctrl-1 = <ð2_sleep_pins_mx>; + pinctrl-names = "default", "sleep"; + phy-mode = "rgmii-id"; + max-speed = <1000>; + phy-handle = <&rtl8211f_eth2>; + nvmem-cells = <ðernet_mac2_address>; + nvmem-cell-names = "mac-address"; + st,eth-clk-sel; + + mdio1 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + rtl8211f_eth2: ethernet-phy@0 { + compatible = "ethernet-phy-id001c.c916"; + reg = <0>; + reset-assert-us = <10000>; + reset-deassert-us = <30000>; + reset-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; + realtek,clkout-disable; + }; + }; + +}; + +// bus i2c1 +&i2c1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_pins_mx>; + pinctrl-1 = <&i2c1_sleep_pins_mx>; + // i2c-scl-rising-time-ns = <96>; + // i2c-scl-falling-time-ns = <3>; + clock-frequency = <100000>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; +}; + +// bus i2c2 +&i2c2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c2_pins_mx>; + pinctrl-1 = <&i2c2_sleep_pins_mx>; + clock-frequency = <100000>; + status = "okay"; + // status = "disabled"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + +}; + +// interior i2c +&i2c3 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c3_pins_mx>; + pinctrl-1 = <&i2c3_sleep_pins_mx>; + clock-frequency = <100000>; + status = "okay"; + // /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + touchscreen@38 { + compatible = "focaltech,ft6236"; + reg = <0x38>; + interrupt-parent = <&gpioi>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; + touchscreen-size-x = <240>; + touchscreen-size-y = <320>; + status = "okay"; + }; + + pcf8563@51 { + compatible = "nxp,pcf8563"; + reg = <0x51>; + status = "okay"; + }; +}; + +//enclosure i2c +&i2c5 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c5_pins_mx>; + pinctrl-1 = <&i2c5_sleep_pins_mx>; + clock-frequency = <100000>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; +}; + +&iwdg2 { + timeout-sec = <32>; + status = "okay"; +}; + +<dc { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <<dc_pins_mx>; + pinctrl-1 = <<dc_sleep_pins_mx>; + status = "okay"; + + port { + #address-cells = <1>; + #size-cells = <0>; + + ltdc_out_rgb: endpoint@0 { + reg = <0>; + remote-endpoint = <&panel_in_rgb>; + }; + }; +}; + +&rtc { + status = "disabled"; +}; + +&scmi_regu { + scmi_vddcpu: voltd-vddcpu { + reg = ; + regulator-name = "vddcpu"; + }; + scmi_vdd: voltd-vdd { + reg = ; + regulator-name = "vdd"; + }; + scmi_vddcore: voltd-vddcore { + reg = ; + regulator-name = "vddcore"; + }; + scmi_vdd_adc: voltd-vdd-adc { + reg = ; + regulator-name = "vdd_adc"; + }; + scmi_vdd_usb: voltd-vdd-usb { + reg = ; + regulator-name = "vdd_usb"; + }; + scmi_vdd_sd: voltd-vdd-sd { + reg = ; + regulator-name = "vdd_sd"; + }; + scmi_v1v8_periph: voltd-v1v8-periph { + reg = ; + regulator-name = "v1v8_periph"; + }; + scmi_v3v3_sw: voltd-v3v3-sw { + reg = ; + regulator-name = "v3v3_sw"; + }; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_clk_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + non-removable; + disable-wp; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&scmi_vdd_sd>; + status = "okay"; +}; + +/* Wifi */ +// &sdmmc2 { +// pinctrl-names = "default", "opendrain", "sleep"; +// pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_clk_pins_a>; +// pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_clk_pins_a>; +// pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>; +// non-removable; +// st,neg-edge; +// bus-width = <4>; +// vmmc-supply = <&v3v3_ao>; +// mmc-pwrseq = <&wifi_pwrseq>; +// #address-cells = <1>; +// #size-cells = <0>; +// status = "disabled"; +// }; + + +&spi1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi1_pins_mx>; + pinctrl-1 = <&spi1_sleep_pins_mx>; + num-cs = <1>; + cs-gpios = <&gpioh 5 GPIO_ACTIVE_HIGH>; + status = "okay"; + + disply@0 { + compatible = "ilitek,ili9341_m5"; + reg = <0>; + dc-gpios = <&gpioh 4 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpioi 0 GPIO_ACTIVE_LOW>; + spi-max-frequency = <10000000>; + status = "okay"; + rotate = <180>; + bgr; + buswidth = <8>; + width = <320>; + height = <240>; + }; +}; + +// bus spi +&spi4 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi4_pins_mx>; + pinctrl-1 = <&spi4_sleep_pins_mx>; + // cs-gpios = <&gpiob 13 GPIO_ACTIVE_LOW>, <&gpioc 13 GPIO_ACTIVE_LOW>; + + /delete-property/dmas; + /delete-property/dma-names; + // status = "okay"; + status = "disabled"; + + spidev@0 { + compatible = "rohm,dh2228fv"; + reg = <0>; + spi-max-frequency = <50000000>; + /* 其他 SPI 设备属性配置 */ + }; +}; + + +&adc_1 { + pinctrl-names = "default"; + pinctrl-0 = <&adc1_pins_mx>; + vdda-supply = <&scmi_vdd_adc>; + vref-supply = <&scmi_vdd_adc>; + status = "disabled"; + adc1: adc@0 { + /delete-property/dmas; + /delete-property/dma-names; + st,min-sample-time-nsecs = <5000>; + st,adc-channels = <2 3 7 17>; + status = "disabled"; + }; + +}; + +// bus pwm +&timers1 { + /delete-property/dmas; + /delete-property/dma-names; + status = "disabled"; + pwm { + pinctrl-0 = <&tim1_pwm_pins_mx>; + pinctrl-1 = <&tim1_pwm_sleep_pins_mx>; + pinctrl-names = "default", "sleep"; + status = "disabled"; + }; + timer@0 { + status = "disabled"; + }; +}; + +// bus pwm +&timers2 { + /delete-property/dmas; + /delete-property/dma-names; + status = "disabled"; + pwm { + pinctrl-0 = <&tim2_pwm_pins_mx>; + pinctrl-1 = <&tim2_pwm_sleep_pins_mx>; + pinctrl-names = "default", "sleep"; + status = "disabled"; + }; + timer@1 { + status = "disabled"; + }; +}; + +&uart4 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart4_pins_a>; + pinctrl-1 = <&uart4_sleep_pins_a>; + pinctrl-2 = <&uart4_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; + status = "disabled"; +}; + +// log uart +&usart6 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&usart6_pins_mx>; + pinctrl-1 = <&usart6_sleep_pins_mx>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&uart8 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart8_pins_a>; + pinctrl-1 = <&uart8_sleep_pins_a>; + pinctrl-2 = <&uart8_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; + status = "disabled"; +}; + +// bus uart1 +&usart1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&usart1_pins_mx>; + pinctrl-1 = <&usart1_sleep_pins_mx>; + // pinctrl-2 = <&usart1_idle_pins_a>; + // uart-has-rtscts; + /delete-property/dmas; + /delete-property/dma-names; + status = "disabled"; +}; + +// bus uart2 +&usart2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&usart2_pins_mx>; + pinctrl-1 = <&usart2_sleep_pins_mx>; + // pinctrl-2 = <&usart1_idle_pins_a>; + // uart-has-rtscts; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +// rs485 +&usart3 { + /delete-property/dmas; + /delete-property/dma-names; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&usart3_pins_mx>; + pinctrl-1 = <&usart3_sleep_pins_mx>; + rts-gpios; + linux,rs485-enabled-at-boot-time; + status = "okay"; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + status = "okay"; +}; + +&usbotg_hs { + phys = <&usbphyc_port1 0>; + phy-names = "usb2-phy"; + usb-role-switch; + status = "okay"; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&scmi_vdd_usb>; + st,current-boost-microamp = <1000>; + st,decrease-hs-slew-rate; + st,tune-hs-dc-level = <2>; + st,enable-hs-rftime-reduction; + st,trim-hs-current = <11>; + st,trim-hs-impedance = <2>; + st,tune-squelch-level = <1>; + st,enable-hs-rx-gain-eq; + st,no-hs-ftime-ctrl; + st,no-lsfs-sc; + + /* + * Hack to keep hub active if wakeup source is enabled + * otherwise the hub will wakeup the port0 as soon as the v3v3_sw is disabled + */ + connector { + compatible = "usb-a-connector"; + vbus-supply = <&scmi_v3v3_sw>; + }; +}; + +&usbphyc_port1 { + phy-supply = <&scmi_vdd_usb>; + st,current-boost-microamp = <1000>; + st,decrease-hs-slew-rate; + st,tune-hs-dc-level = <2>; + st,enable-hs-rftime-reduction; + st,trim-hs-current = <11>; + st,trim-hs-impedance = <2>; + st,tune-squelch-level = <1>; + st,enable-hs-rx-gain-eq; + st,no-hs-ftime-ctrl; + st,no-lsfs-sc; +}; + +&m_can1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&fdcan1_pins_mx>; + pinctrl-1 = <&fdcan1_sleep_pins_mx>; + status = "okay"; +}; + +&m_can2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&fdcan2_pins_mx>; + pinctrl-1 = <&fdcan2_sleep_pins_mx>; + status = "okay"; +}; + +&pinctrl { + adc1_pins_mx: adc1_mx-0 { + pins { + pinmux = , /* ADC1_INP7 */ + , /* ADC1_INP3 */ + , /* ADC1_INP2 */ + ; /* ADC1_INP17 */ + // ; /* ADC1_INN2 */ + }; + }; + + adc1_sleep_pins_mx: adc1_sleep_mx-0 { + pins { + pinmux = , /* ADC1_INP7 */ + , /* ADC1_INP3 */ + , /* ADC1_INP2 */ + ; /* ADC1_INP17 */ + // ; /* ADC1_INN2 */ + }; + }; + + eth1_pins_mx: eth1_mx-0 { + pins1 { + pinmux = ; /* ETH1_MDIO */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = , /* ETH1_RX_CTL */ + , /* ETH1_RXD2 */ + , /* ETH1_RXD3 */ + , /* ETH1_RXD0 */ + , /* ETH1_RXD1 */ + ; /* ETH1_RX_CLK */ + bias-disable; + }; + pins3 { + pinmux = , /* ETH1_TX_CTL */ + , /* ETH1_GTX_CLK */ + , /* ETH1_TXD2 */ + , /* ETH1_TXD3 */ + , /* ETH1_MDC */ + , /* ETH1_TXD0 */ + ; /* ETH1_TXD1 */ + // , /* ETH1_CLK125 */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins4 { + pinmux = ; /* ETH1_CLK125 */ + bias-pull-down; + }; + }; + + eth1_sleep_pins_mx: eth1_sleep_mx-0 { + pins { + pinmux = , /* ETH1_MDIO */ + , /* ETH1_RX_CTL */ + , /* ETH1_RXD2 */ + , /* ETH1_RXD3 */ + , /* ETH1_TX_CTL */ + , /* ETH1_GTX_CLK */ + , /* ETH1_TXD2 */ + , /* ETH1_RXD0 */ + , /* ETH1_RXD1 */ + , /* ETH1_RX_CLK */ + , /* ETH1_TXD3 */ + , /* ETH1_MDC */ + , /* ETH1_TXD0 */ + ; /* ETH1_TXD1 */ + // , /* ETH1_CLK125 */ + }; + pins1 { + pinmux = ; /* ETH1_CLK125 */ + bias-pull-down; + }; + }; + + eth2_pins_mx: eth2_mx-0 { + pins1 { + pinmux = , /* ETH2_RXD3 */ + , /* ETH2_RXD1 */ + , /* ETH2_RXD0 */ + , /* ETH2_RX_CTL */ + , /* ETH2_RXD2 */ + ; /* ETH2_RX_CLK */ + bias-disable; + }; + pins2 { + pinmux = ; /* ETH2_MDIO */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = , /* ETH2_TXD3 */ + , /* ETH2_TX_CTL */ + , /* ETH2_TXD0 */ + , /* ETH2_TXD2 */ + , /* ETH2_GTX_CLK */ + , /* ETH2_MDC */ + ; /* ETH2_TXD1 */ + // ; /* ETH2_CLK125 */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins4 { + pinmux = ; /* ETH2_CLK125 */ + bias-pull-down; + }; + }; + + eth2_sleep_pins_mx: eth2_sleep_mx-0 { + pins { + pinmux = , /* ETH2_RXD3 */ + , /* ETH2_MDIO */ + , /* ETH2_RXD1 */ + , /* ETH2_TXD3 */ + , /* ETH2_RXD0 */ + , /* ETH2_TX_CTL */ + , /* ETH2_TXD0 */ + , /* ETH2_TXD2 */ + , /* ETH2_GTX_CLK */ + , /* ETH2_MDC */ + , /* ETH2_TXD1 */ + , /* ETH2_RX_CTL */ + , /* ETH2_RXD2 */ + ; /* ETH2_RX_CLK */ + // , /* ETH2_CLK125 */ + }; + pins1 { + pinmux = ; /* ETH2_CLK125 */ + bias-pull-down; + }; + }; + + fdcan1_pins_mx: fdcan1_mx-0 { + pins1 { + pinmux = ; /* FDCAN1_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* FDCAN1_RX */ + bias-disable; + }; + }; + + fdcan1_sleep_pins_mx: fdcan1_sleep_mx-0 { + pins { + pinmux = , /* FDCAN1_RX */ + ; /* FDCAN1_TX */ + }; + }; + + fdcan2_pins_mx: fdcan2_mx-0 { + pins1 { + pinmux = ; /* FDCAN2_RX */ + bias-disable; + }; + pins2 { + pinmux = ; /* FDCAN2_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + }; + + fdcan2_sleep_pins_mx: fdcan2_sleep_mx-0 { + pins { + pinmux = , /* FDCAN2_RX */ + ; /* FDCAN2_TX */ + }; + }; + + i2c1_pins_mx: i2c1_mx-0 { + pins { + pinmux = , /* I2C1_SCL */ + ; /* I2C1_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + i2c1_sleep_pins_mx: i2c1_sleep_mx-0 { + pins { + pinmux = , /* I2C1_SCL */ + ; /* I2C1_SDA */ + }; + }; + + i2c2_pins_mx: i2c2_mx-0 { + pins { + pinmux = , /* I2C2_SCL */ + ; /* I2C2_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + i2c2_sleep_pins_mx: i2c2_sleep_mx-0 { + pins { + pinmux = , /* I2C2_SCL */ + ; /* I2C2_SDA */ + }; + }; + + i2c3_pins_mx: i2c3_mx-0 { + pins { + pinmux = , /* I2C3_SDA */ + ; /* I2C3_SCL */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + i2c3_sleep_pins_mx: i2c3_sleep_mx-0 { + pins { + pinmux = , /* I2C3_SDA */ + ; /* I2C3_SCL */ + }; + }; + + ft6236_pins_b: ft6236-1 { + pins { + pinmux = ; + bias-pull-up; + }; + }; + + i2c4_pins_mx: i2c4_mx-0 { + pins { + pinmux = , /* I2C4_SDA */ + ; /* I2C4_SCL */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + i2c4_sleep_pins_mx: i2c4_sleep_mx-0 { + pins { + pinmux = , /* I2C4_SDA */ + ; /* I2C4_SCL */ + }; + }; + + i2c5_pins_mx: i2c5_mx-0 { + pins { + pinmux = , /* I2C5_SCL */ + ; /* I2C5_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + i2c5_sleep_pins_mx: i2c5_sleep_mx-0 { + pins { + pinmux = , /* I2C5_SCL */ + ; /* I2C5_SDA */ + }; + }; + + ltdc_pins_mx: ltdc_mx-0 { + pins1 { + pinmux = , /* LTDC_G6 */ + , /* LTDC_G7 */ + , /* LTDC_B2 */ + , /* LTDC_B6 */ + , /* LTDC_B7 */ + , /* LTDC_B1 */ + , /* LTDC_R3 */ + , /* LTDC_R0 */ + , /* LTDC_G2 */ + , /* LTDC_R1 */ + , /* LTDC_B0 */ + , /* LTDC_B5 */ + , /* LTDC_G5 */ + , /* LTDC_G4 */ + , /* LTDC_R4 */ + , /* LTDC_R5 */ + , /* LTDC_VSYNC */ + , /* LTDC_R6 */ + , /* LTDC_G1 */ + , /* LTDC_G0 */ + , /* LTDC_R7 */ + , /* LTDC_R2 */ + , /* LTDC_B3 */ + , /* LTDC_DE */ + , /* LTDC_HSYNC */ + , /* LTDC_G3 */ + ; /* LTDC_B4 */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* LTDC_CLK */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + }; + + ltdc_sleep_pins_mx: ltdc_sleep_mx-0 { + pins { + pinmux = , /* LTDC_G6 */ + , /* LTDC_G7 */ + , /* LTDC_B2 */ + , /* LTDC_B6 */ + , /* LTDC_B7 */ + , /* LTDC_B1 */ + , /* LTDC_R3 */ + , /* LTDC_R0 */ + , /* LTDC_CLK */ + , /* LTDC_G2 */ + , /* LTDC_R1 */ + , /* LTDC_B0 */ + , /* LTDC_B5 */ + , /* LTDC_G5 */ + , /* LTDC_G4 */ + , /* LTDC_R4 */ + , /* LTDC_R5 */ + , /* LTDC_VSYNC */ + , /* LTDC_R6 */ + , /* LTDC_G1 */ + , /* LTDC_G0 */ + , /* LTDC_R7 */ + , /* LTDC_R2 */ + , /* LTDC_B3 */ + , /* LTDC_DE */ + , /* LTDC_HSYNC */ + , /* LTDC_G3 */ + ; /* LTDC_B4 */ + }; + }; + + quadspi_pins_mx: quadspi_mx-0 { + pins1 { + pinmux = , /* QUADSPI_BK1_IO2 */ + , /* QUADSPI_BK1_IO3 */ + , /* QUADSPI_BK1_NCS */ + , /* QUADSPI_BK1_IO1 */ + ; /* QUADSPI_BK1_IO0 */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + pins2 { + pinmux = ; /* QUADSPI_CLK */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + }; + + quadspi_sleep_pins_mx: quadspi_sleep_mx-0 { + pins { + pinmux = , /* QUADSPI_BK1_IO2 */ + , /* QUADSPI_BK1_IO3 */ + , /* QUADSPI_BK1_NCS */ + , /* QUADSPI_BK1_IO1 */ + , /* QUADSPI_CLK */ + ; /* QUADSPI_BK1_IO0 */ + }; + }; + + sai1a_pins_mx: sai1a_mx-0 { + pins { + pinmux = , /* SAI1_SCK_A */ + , /* SAI1_MCLK_A */ + , /* SAI1_SD_A */ + ; /* SAI1_FS_A */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + }; + + sai1a_sleep_pins_mx: sai1a_sleep_mx-0 { + pins { + pinmux = , /* SAI1_SCK_A */ + , /* SAI1_MCLK_A */ + , /* SAI1_SD_A */ + ; /* SAI1_FS_A */ + }; + }; + + sai1b_pins_mx: sai1b_mx-0 { + pins { + pinmux = , /* SAI1_FS_B */ + , /* SAI1_SCK_B */ + , /* SAI1_MCLK_B */ + ; /* SAI1_SD_B */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + }; + + sai1b_sleep_pins_mx: sai1b_sleep_mx-0 { + pins { + pinmux = , /* SAI1_FS_B */ + , /* SAI1_SCK_B */ + , /* SAI1_MCLK_B */ + ; /* SAI1_SD_B */ + }; + }; + + sdmmc1_pins_mx: sdmmc1_mx-0 { + pins1 { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + ; /* SDMMC1_CMD */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + pins2 { + pinmux = ; /* SDMMC1_CK */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + }; + + sdmmc1_opendrain_pins_mx: sdmmc1_opendrain_mx-0 { + pins1 { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + ; /* SDMMC1_D3 */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + pins2 { + pinmux = ; /* SDMMC1_CK */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + pins3 { + pinmux = ; /* SDMMC1_CMD */ + bias-disable; + drive-open-drain; + slew-rate = <1>; + }; + }; + + sdmmc1_sleep_pins_mx: sdmmc1_sleep_mx-0 { + pins { + pinmux = , /* SDMMC1_D0 */ + , /* SDMMC1_D1 */ + , /* SDMMC1_D2 */ + , /* SDMMC1_D3 */ + , /* SDMMC1_CK */ + ; /* SDMMC1_CMD */ + }; + }; + + spi1_pins_mx: spi1_mx-0 { + pins { + pinmux = , /* SPI1_MOSI */ + ; /* SPI1_SCK */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + }; + + spi1_sleep_pins_mx: spi1_sleep_mx-0 { + pins { + pinmux = , /* SPI1_MOSI */ + ; /* SPI1_SCK */ + }; + }; + + spi4_pins_mx: spi4_mx-0 { + pins { + pinmux = , /* SPI4_SCK */ + , /* SPI4_MOSI */ + ; /* SPI4_MISO */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + }; + + spi4_sleep_pins_mx: spi4_sleep_mx-0 { + pins { + pinmux = , /* SPI4_SCK */ + , /* SPI4_MOSI */ + ; /* SPI4_MISO */ + }; + }; + + tim1_pwm_pins_mx: tim1_pwm_mx-0 { + pins { + pinmux = , /* TIM1_CH1N */ + ; /* TIM1_CH1 */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + }; + + tim1_pwm_sleep_pins_mx: tim1_pwm_sleep_mx-0 { + pins { + pinmux = , /* TIM1_CH1N */ + ; /* TIM1_CH1 */ + }; + }; + + tim2_pwm_pins_mx: tim2_pwm_mx-0 { + pins { + pinmux = , /* TIM2_CH3 */ + ; /* TIM2_CH1 */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + }; + + tim2_pwm_sleep_pins_mx: tim2_pwm_sleep_mx-0 { + pins { + pinmux = , /* TIM2_CH3 */ + ; /* TIM2_CH1 */ + }; + }; + + usart1_pins_mx: usart1_mx-0 { + pins1 { + pinmux = ; /* USART1_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* USART1_RX */ + bias-disable; + }; + }; + + usart1_sleep_pins_mx: usart1_sleep_mx-0 { + pins { + pinmux = , /* USART1_TX */ + ; /* USART1_RX */ + }; + }; + + usart2_pins_mx: usart2_mx-0 { + pins1 { + pinmux = ; /* USART2_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* USART2_RX */ + bias-disable; + }; + }; + + usart2_sleep_pins_mx: usart2_sleep_mx-0 { + pins { + pinmux = , /* USART2_TX */ + ; /* USART2_RX */ + }; + }; + + usart3_pins_mx: usart3_mx-0 { + pins1 { + pinmux = , /* USART3_TX */ + ; /* USART3_DE */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* USART3_RX */ + bias-disable; + }; + }; + + usart3_sleep_pins_mx: usart3_sleep_mx-0 { + pins { + pinmux = , /* USART3_TX */ + , /* USART3_DE */ + ; /* USART3_RX */ + }; + }; + + usart6_pins_mx: usart6_mx-0 { + pins1 { + pinmux = ; /* USART6_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* USART6_RX */ + bias-pull-up; + }; + }; + + usart6_sleep_pins_mx: usart6_sleep_mx-0 { + pins { + pinmux = , /* USART6_TX */ + ; /* USART6_RX */ + }; + }; + + usb_otg_hs_pins_mx: usb_otg_hs_mx-0 { + pins { + pinmux = ; /* USB_OTG_HS_VBUS */ + }; + }; + + usb_otg_hs_sleep_pins_mx: usb_otg_hs_sleep_mx-0 { + pins { + pinmux = ; /* USB_OTG_HS_VBUS */ + }; + }; + +}; + diff --git a/board/m5stack/core135/linux-enable-fbdev-emul.config b/board/m5stack/core135/linux-enable-fbdev-emul.config new file mode 100644 index 0000000..16ef2c8 --- /dev/null +++ b/board/m5stack/core135/linux-enable-fbdev-emul.config @@ -0,0 +1 @@ +CONFIG_DRM_FBDEV_EMULATION=y diff --git a/board/m5stack/core135/linux-enable-m5stack.config b/board/m5stack/core135/linux-enable-m5stack.config new file mode 100644 index 0000000..04cea0e --- /dev/null +++ b/board/m5stack/core135/linux-enable-m5stack.config @@ -0,0 +1,22 @@ +CONFIG_SPI_STM32=y +CONFIG_FB_SYS_FILLRECT=y +CONFIG_FB_SYS_COPYAREA=y +CONFIG_FB_SYS_IMAGEBLIT=y +CONFIG_FB_SYS_FOPS=y +CONFIG_FB_DEFERRED_IO=y +CONFIG_FB_BACKLIGHT=y +CONFIG_STAGING=y +CONFIG_FB_TFT=y +CONFIG_FB_TFT_ILI9341_M5=m +CONFIG_RTC_DRV_PCF8563=y +CONFIG_GPIO_SYSFS=y +CONFIG_TOUCHSCREEN_FT6236=y + +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_MONO=y +CONFIG_LOGO_LINUX_VGA16=y +CONFIG_LOGO_LINUX_CLUT224=y +CONFIG_FONT_SUPPORT=y +CONFIG_FONT_8x8=y \ No newline at end of file diff --git a/board/m5stack/core135/optee-dts/stm32mp135f-core135.dts b/board/m5stack/core135/optee-dts/stm32mp135f-core135.dts new file mode 100644 index 0000000..6588789 --- /dev/null +++ b/board/m5stack/core135/optee-dts/stm32mp135f-core135.dts @@ -0,0 +1,759 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2021-2022 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include +#include "stm32mp135.dtsi" +#include "stm32mp13xf.dtsi" +#include "stm32mp13-pinctrl.dtsi" + +/ { + model = "STMicroelectronics STM32MP135F-DK Discovery Board"; + compatible = "st,stm32mp135f-dk", "st,stm32mp135"; + + aliases { + serial0 = &usart6; + serial1 = &usart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@c0000000 { + device_type = "memory"; + reg = <0xc0000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + optee_framebuffer: optee-framebuffer@dd000000 { + /* Secure framebuffer memory */ + reg = <0xdd000000 0x1000000>; + st,protreg = ; + }; + }; + + vin: vin { + compatible = "regulator-fixed"; + regulator-name = "vin"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + v3v3_ao: v3v3_ao { + compatible = "regulator-fixed"; + regulator-name = "v3v3_ao"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + // virtual power ----- start + vddcpu: buck1 { + compatible = "regulator-fixed"; + regulator-name = "vddcpu"; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + // regulator-over-current-protection; + + lp-stop { + regulator-suspend-microvolt = <1250000>; + }; + lplv-stop { + regulator-suspend-microvolt = <900000>; + }; + lplv-stop2 { + regulator-off-in-suspend; + }; + standby-ddr-sr { + regulator-off-in-suspend; + }; + standby-ddr-off { + regulator-off-in-suspend; + }; + }; + + vdd_ddr: buck2 { + compatible = "regulator-fixed"; + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-off-in-suspend; + regulator-always-on; + }; + + vdd: buck3 { + compatible = "regulator-fixed"; + regulator-name = "vdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-off-in-suspend; + regulator-always-on; + }; + + vddcore: buck4 { + compatible = "regulator-fixed"; + regulator-name = "vddcore"; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + regulator-off-in-suspend; + regulator-always-on; + }; + + vdd_adc: ldo1 { + compatible = "regulator-fixed"; + regulator-name = "vdd_adc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-off-in-suspend; + regulator-always-on; + }; + + vdd_usb: ldo4 { + compatible = "regulator-fixed"; + regulator-name = "vdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-off-in-suspend; + regulator-always-on; + }; + + vdd_sd: ldo5 { + compatible = "regulator-fixed"; + regulator-name = "vdd_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-off-in-suspend; + regulator-always-on; + // regulator-boot-on; + }; + + v1v8_periph: ldo6 { + compatible = "regulator-fixed"; + regulator-name = "v1v8_periph"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-off-in-suspend; + regulator-always-on; + }; + + v3v3_sw: pwr_sw2 { + compatible = "regulator-fixed"; + regulator-name = "v3v3_sw"; + // regulator-active-discharge = <1>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + // virtual power ----- end +}; + +&bsec { + board_id: board_id@f0 { + reg = <0xf0 0x4>; + st,non-secure-otp; + }; +}; + +&cpu0 { + cpu-supply = <&vddcpu>; +}; + +&etzpc { + st,decprot = < + DECPROT(STM32MP1_ETZPC_ADC1_ID, DECPROT_NS_RW, DECPROT_UNLOCK) + DECPROT(STM32MP1_ETZPC_ADC2_ID, DECPROT_NS_RW, DECPROT_UNLOCK) + DECPROT(STM32MP1_ETZPC_BKPSRAM_ID, DECPROT_S_RW, DECPROT_UNLOCK) + DECPROT(STM32MP1_ETZPC_CRYP_ID, DECPROT_NS_RW, DECPROT_UNLOCK) + DECPROT(STM32MP1_ETZPC_DCMIPP_ID, DECPROT_NS_RW, DECPROT_UNLOCK) + DECPROT(STM32MP1_ETZPC_DDRCTRLPHY_ID, DECPROT_NS_R_S_W, DECPROT_UNLOCK) + DECPROT(STM32MP1_ETZPC_ETH1_ID, DECPROT_NS_RW, DECPROT_UNLOCK) + DECPROT(STM32MP1_ETZPC_ETH2_ID, DECPROT_NS_RW, DECPROT_UNLOCK) + DECPROT(STM32MP1_ETZPC_FMC_ID, DECPROT_NS_RW, DECPROT_UNLOCK) + DECPROT(STM32MP1_ETZPC_HASH_ID, DECPROT_S_RW, DECPROT_UNLOCK) + DECPROT(STM32MP1_ETZPC_I2C3_ID, DECPROT_NS_RW, DECPROT_UNLOCK) + DECPROT(STM32MP1_ETZPC_I2C4_ID, DECPROT_S_RW, DECPROT_UNLOCK) + DECPROT(STM32MP1_ETZPC_I2C5_ID, DECPROT_NS_RW, DECPROT_UNLOCK) + DECPROT(STM32MP1_ETZPC_IWDG1_ID, DECPROT_S_RW, DECPROT_UNLOCK) + DECPROT(STM32MP1_ETZPC_LPTIM2_ID, DECPROT_NS_RW, DECPROT_UNLOCK) + DECPROT(STM32MP1_ETZPC_LPTIM3_ID, DECPROT_S_RW, DECPROT_UNLOCK) + DECPROT(STM32MP1_ETZPC_LTDC_ID, DECPROT_NS_RW, DECPROT_UNLOCK) + DECPROT(STM32MP1_ETZPC_MCE_ID, DECPROT_S_RW, DECPROT_UNLOCK) + DECPROT(STM32MP1_ETZPC_OTG_ID, DECPROT_NS_RW, DECPROT_UNLOCK) + DECPROT(STM32MP1_ETZPC_PKA_ID, DECPROT_S_RW, DECPROT_UNLOCK) + DECPROT(STM32MP1_ETZPC_QSPI_ID, DECPROT_NS_RW, DECPROT_UNLOCK) + DECPROT(STM32MP1_ETZPC_RNG_ID, DECPROT_S_RW, DECPROT_UNLOCK) + DECPROT(STM32MP1_ETZPC_SAES_ID, DECPROT_S_RW, DECPROT_UNLOCK) + DECPROT(STM32MP1_ETZPC_SDMMC1_ID, DECPROT_NS_RW, DECPROT_UNLOCK) + DECPROT(STM32MP1_ETZPC_SDMMC2_ID, DECPROT_NS_RW, DECPROT_UNLOCK) + DECPROT(STM32MP1_ETZPC_SPI4_ID, DECPROT_NS_RW, DECPROT_UNLOCK) + DECPROT(STM32MP1_ETZPC_SPI5_ID, DECPROT_NS_RW, DECPROT_UNLOCK) + DECPROT(STM32MP1_ETZPC_SRAM1_ID, DECPROT_NS_RW, DECPROT_UNLOCK) + DECPROT(STM32MP1_ETZPC_SRAM2_ID, DECPROT_NS_RW, DECPROT_UNLOCK) + DECPROT(STM32MP1_ETZPC_SRAM3_ID, DECPROT_S_RW, DECPROT_UNLOCK) + DECPROT(STM32MP1_ETZPC_STGENC_ID, DECPROT_S_RW, DECPROT_UNLOCK) + DECPROT(STM32MP1_ETZPC_TIM12_ID, DECPROT_S_RW, DECPROT_UNLOCK) + DECPROT(STM32MP1_ETZPC_TIM13_ID, DECPROT_NS_RW, DECPROT_UNLOCK) + DECPROT(STM32MP1_ETZPC_TIM14_ID, DECPROT_NS_RW, DECPROT_UNLOCK) + DECPROT(STM32MP1_ETZPC_TIM15_ID, DECPROT_S_RW, DECPROT_UNLOCK) + DECPROT(STM32MP1_ETZPC_TIM16_ID, DECPROT_NS_RW, DECPROT_UNLOCK) + DECPROT(STM32MP1_ETZPC_TIM17_ID, DECPROT_NS_RW, DECPROT_UNLOCK) + DECPROT(STM32MP1_ETZPC_USART1_ID, DECPROT_NS_RW, DECPROT_UNLOCK) + DECPROT(STM32MP1_ETZPC_USART2_ID, DECPROT_NS_RW, DECPROT_UNLOCK) + DECPROT(STM32MP1_ETZPC_USBPHYCTRL_ID, DECPROT_NS_RW, DECPROT_UNLOCK) + DECPROT(STM32MP1_ETZPC_VREFBUF_ID, DECPROT_NS_RW, DECPROT_UNLOCK) + >; +}; + +&hash { + status = "okay"; +}; + +&hse_monitor { + status = "okay"; +}; + +&iwdg1 { + timeout-sec = <32>; + secure-timeout-sec = <5>; + status = "okay"; +}; + +&lptimer3 { + status = "okay"; + + counter { + status = "okay"; + }; +}; + + +<dc { + pinctrl-names = "default"; + pinctrl-0 = <<dc_pins_mx>; + status = "okay"; +}; + +&oem_enc_key { + st,non-secure-otp-provisioning; +}; + +&osc_calibration { + csi-calibration { + status = "okay"; + }; + + hsi-calibration { + status = "okay"; + }; +}; + +&pka { + status = "okay"; +}; + +&pwr_irq { + reg = <0x50001010 0x01>; +}; + +&pwr_regulators { + system_suspend_supported_soc_modes = < + STM32_PM_CSLEEP_RUN + STM32_PM_CSTOP_ALLOW_LP_STOP + STM32_PM_CSTOP_ALLOW_LPLV_STOP + STM32_PM_CSTOP_ALLOW_LPLV_STOP2 + STM32_PM_CSTOP_ALLOW_STANDBY_DDR_SR + >; + + system_off_soc_mode = ; + vdd-supply = <&vdd>; + vdd_3v3_usbfs-supply = <&vdd_usb>; +}; + +&rcc { + st,clksrc = < + CLK_MPU_PLL1P + CLK_AXI_PLL2P + CLK_MLAHBS_PLL3 + CLK_RTC_LSE + CLK_MCO1_DISABLED + CLK_MCO2_DISABLED + CLK_CKPER_HSE + CLK_SDMMC1_PLL4P + CLK_SDMMC2_PLL4P + CLK_ETH1_PLL4P + CLK_ETH2_PLL4P + CLK_STGEN_HSE + CLK_USBPHY_HSE + CLK_I2C4_HSI + CLK_USBO_USBPHY + CLK_ADC1_CKPER + CLK_ADC2_CKPER + CLK_I2C12_HSI + CLK_UART1_HSI + CLK_UART2_HSI + CLK_UART35_HSI + CLK_UART4_HSI + CLK_UART6_HSI + CLK_UART78_HSI + CLK_SAES_AXI + CLK_DCMIPP_PLL2Q + CLK_LPTIM2_PCLK3 + CLK_LPTIM3_PCLK3 + CLK_RNG1_PLL4R + CLK_SAI1_PLL3Q + >; + + st,clkdiv = < + DIV(DIV_MPU, 1) + DIV(DIV_AXI, 0) + DIV(DIV_MLAHB, 0) + DIV(DIV_APB1, 1) + DIV(DIV_APB2, 1) + DIV(DIV_APB3, 1) + DIV(DIV_APB4, 1) + DIV(DIV_APB5, 2) + DIV(DIV_APB6, 1) + DIV(DIV_RTC, 0) + DIV(DIV_MCO1, 0) + DIV(DIV_MCO2, 0) + >; + + st,pll_vco { + pll1_vco_2000Mhz: pll1-vco-2000Mhz { + src = ; + divmn = <1 82>; + frac = <0xAAA>; + }; + + pll1_vco_1600Mhz: pll1-vco-1600Mhz { + src = < CLK_PLL12_HSE >; + divmn = < 1 65 >; + frac = < 0x157c >; + }; + + pll1_vco_1980Mhz: pll1-vco-1980Mhz { + src = < CLK_PLL12_HSE >; + divmn = < 1 81 >; + frac = <0x1004>; + }; + + pll1_vco_1300Mhz: pll1-vco-1300Mhz { + src = ; + divmn = <2 80>; + frac = <0x800>; + }; + + pll2_vco_1066Mhz: pll2-vco-1066Mhz { + src = ; + divmn = <2 65>; + frac = <0x1400>; + }; + + pll3_vco_417_8Mhz: pll3-vco-417_8Mhz { + src = < CLK_PLL3_HSE >; + divmn = < 1 33 >; + frac = < 0x1a04 >; + }; + + pll3_vco_417Mhz: pll3-vco-417Mhz { + src = ; + divmn = <1 33>; + frac = <0x1a04>; + }; + + pll3_vco_412_776Mhz: pll3-vco-412_776Mhz { + src = < CLK_PLL3_HSE >; + divmn = < 2 50 >; + frac = < 0x131b >; + }; + + pll4_vco_600Mhz: pll4-vco-600Mhz { + src = ; + divmn = <1 49>; + }; + + pll4_vco_500Mhz: pll4-vco-500Mhz { + src = < CLK_PLL4_HSE >; + divmn = < 5 124 >; + }; + }; + + /* VCO = 1300.0 MHz => P = 650 (CPU) */ + pll1: st,pll@0 { + compatible = "st,stm32mp1-pll"; + reg = <0>; + + // st,pll = <&pll1_cfg1>; + st,pll = <&pll1_cfg4>; + + /*P = 650 (CPU)*/ + pll1_cfg1: pll1_cfg1 { + st,pll_vco = <&pll1_vco_1300Mhz>; + st,pll_div_pqr = <0 1 1>; + }; + + /*P = 1000 (CPU)*/ + pll1_cfg2: pll1_cfg2 { + st,pll_vco = <&pll1_vco_2000Mhz>; + st,pll_div_pqr = <0 1 1>; + }; + + /*P = 800 (CPU)*/ + pll1_cfg3: pll1_cfg3 { + st,pll_vco = < &pll1_vco_1600Mhz >; + st,pll_div_pqr = < 0 1 1 >; + }; + + /*P = 990 (CPU)*/ + pll1_cfg4: pll1_cfg4 { + st,pll_vco = < &pll1_vco_1980Mhz >; + st,pll_div_pqr = < 0 1 1 >; + }; + + /*P = 325 (CPU)*/ + pll1_cfg5: pll1_cfg5 { + st,pll_vco = < &pll1_vco_1300Mhz >; + st,pll_div_pqr = < 1 1 1 >; + }; + }; + + /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 266, R = 533 (DDR) */ + pll2: st,pll@1 { + compatible = "st,stm32mp1-pll"; + reg = <1>; + + st,pll = <&pll2_cfg1>; + + pll2_cfg1: pll2_cfg1 { + st,pll_vco = <&pll2_vco_1066Mhz>; + st,pll_div_pqr = <1 1 0>; + }; + }; + + /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ + pll3: st,pll@2 { + compatible = "st,stm32mp1-pll"; + reg = <2>; + + // st,pll = <&pll3_cfg1>; + st,pll = < &pll3_cfg2 >; + + /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ + pll3_cfg1: pll3_cfg1 { + st,pll_vco = <&pll3_vco_417Mhz>; + st,pll_div_pqr = <1 16 36>; + }; + + /* VCO = 412.776 MHz => P = 206.388, Q = 19.656017, R = 11.46601 */ + pll3_cfg2: pll3_cfg2 { + st,pll_vco = < &pll3_vco_412_776Mhz >; + st,pll_div_pqr = < 1 20 35 >; + }; + + }; + + /* VCO = 600.0 MHz => P = 50, Q = 10, R = 50 */ + pll4: st,pll@3 { + compatible = "st,stm32mp1-pll"; + reg = <3>; + // st,pll = <&pll4_cfg1>; + st,pll = < &pll4_cfg2 >; + + /* VCO = 600.0 MHz => P = 25, Q = 10, R = 50 */ + pll4_cfg1: pll4_cfg1 { + st,pll_vco = <&pll4_vco_600Mhz>; + st,pll_div_pqr = <11 59 11>; + }; + + /* VCO = 500.0 MHz => P = 125, Q = 83.33, R = 50 */ + pll4_cfg2: pll4_cfg2 { + st,pll_vco = < &pll4_vco_500Mhz >; + st,pll_div_pqr = < 3 5 9 >; + }; + + /* VCO = 500.0 MHz => P = 25, Q = 71.44, R = 50 */ + pll4_cfg3: pll4_cfg3 { + st,pll_vco = < &pll4_vco_500Mhz >; + st,pll_div_pqr = < 19 6 9 >; + }; + }; + + st,clk_opp { + /* CK_MPU clock config for MP13 */ + st,ck_mpu { + + cfg_1 { + hz = < 990000000 >; + st,clksrc = < CLK_MPU_PLL1P >; + st,pll = < &pll1_cfg4 >; + }; + + cfg_2 { + hz = < 650000000 >; + st,clksrc = < CLK_MPU_PLL1P >; + st,pll = < &pll1_cfg1 >; + }; + }; + }; +}; + +&rng { + status = "okay"; + clock-error-detect; + st,rng-config = ; +}; + +&rtc { + status = "okay"; +}; + +&saes { + status = "okay"; +}; + +&scmi_regu { + scmi_vddcpu: voltd-vddcpu { + reg = ; + voltd-supply = <&vddcpu>; + }; + scmi_vdd: voltd-vdd { + reg = ; + voltd-supply = <&vdd>; + }; + scmi_vddcore: voltd-vddcore { + reg = ; + voltd-supply = <&vddcore>; + }; + scmi_vdd_adc: voltd-vdd_adc { + reg = ; + voltd-supply = <&vdd_adc>; + }; + scmi_vdd_usb: voltd-vdd_usb { + reg = ; + voltd-supply = <&vdd_usb>; + }; + scmi_vdd_sd: voltd-vdd_sd { + reg = ; + voltd-supply = <&vdd_sd>; + }; + scmi_v1v8_periph: voltd-v1v8_periph { + reg = ; + voltd-supply = <&v1v8_periph>; + }; + scmi_v3v3_sw: voltd-v3v3_sw { + reg = ; + voltd-supply = <&v3v3_sw>; + }; +}; + +&tamp { + status = "okay"; + st,tamp_passive_nb_sample = <4>; + st,tamp_passive_sample_clk_div = <16384>; + + tamp_passive@2 { + pinctrl-0 = <&tamp0_in2_pin_a>; + status = "disabled"; + }; + + /* Connect pin8 and pin22 from CN8 */ + tamp_active@1 { + pinctrl-0 = <&tamp0_in3_pin_a &tamp0_out1_pin_a>; + status = "disabled"; + }; +}; + +&timers12 { + status = "okay"; + + counter { + reg = <0x4c007000 0x400>; + status = "okay"; + }; +}; + +&timers15 { + counter { + reg = <0x4c00a000 0x400>; + }; +}; + + + + +&tzc400 { + memory-region = <&optee_framebuffer>; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins_a>; + status = "disabled"; +}; + +&usart6 { + pinctrl-names = "default"; + pinctrl-0 = <&usart6_pins_mx>; + status = "okay"; +}; + + +&usart1 { + pinctrl-names = "default"; + pinctrl-0 = <&usart1_pins_a>; + uart-has-rtscts; + status = "disabled"; +}; + +&wakeup_pin_5 { + bias-pull-up; +}; + +&gpioa { + #address-cells = <1>; +}; +&gpiob { + #address-cells = <1>; +}; +&gpioc { + #address-cells = <1>; +}; +&gpiod { + #address-cells = <1>; +}; +&gpioe { + #address-cells = <1>; +}; +&gpiof { + #address-cells = <1>; +}; +&gpiog { + #address-cells = <1>; +}; +&gpioh { + #address-cells = <1>; +}; +&gpioi { + #address-cells = <1>; +}; +&exti { + #address-cells = <1>; +}; +&intc { + #address-cells = <1>; +}; + +&pinctrl { + usart6_pins_mx: usart6_mx-0 { + pins1 { + pinmux = ; /* USART6_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* USART6_RX */ + bias-pull-up; + }; + }; + + usart6_sleep_pins_mx: usart6_sleep_mx-0 { + pins { + pinmux = , /* USART6_TX */ + ; /* USART6_RX */ + }; + }; + + + + ltdc_pins_mx: ltdc_mx-0 { + pins1 { + pinmux = , /* LTDC_G6 */ + , /* LTDC_G7 */ + , /* LTDC_B2 */ + , /* LTDC_B6 */ + , /* LTDC_B7 */ + , /* LTDC_B1 */ + , /* LTDC_R3 */ + , /* LTDC_R0 */ + , /* LTDC_R1 */ + , /* LTDC_B0 */ + , /* LTDC_B5 */ + , /* LTDC_G5 */ + , /* LTDC_G4 */ + , /* LTDC_R4 */ + , /* LTDC_R5 */ + , /* LTDC_VSYNC */ + , /* LTDC_R6 */ + , /* LTDC_G3 */ + , /* LTDC_G0 */ + , /* LTDC_R7 */ + , /* LTDC_R2 */ + , /* LTDC_B3 */ + , /* LTDC_G1 */ + , /* LTDC_DE */ + , /* LTDC_HSYNC */ + , /* LTDC_G2 */ + ; /* LTDC_B4 */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* LTDC_CLK */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + }; + + ltdc_sleep_pins_mx: ltdc_sleep_mx-0 { + pins { + pinmux = , /* LTDC_G6 */ + , /* LTDC_G7 */ + , /* LTDC_B2 */ + , /* LTDC_B6 */ + , /* LTDC_B7 */ + , /* LTDC_B1 */ + , /* LTDC_R3 */ + , /* LTDC_R0 */ + , /* LTDC_CLK */ + , /* LTDC_R1 */ + , /* LTDC_B0 */ + , /* LTDC_B5 */ + , /* LTDC_G5 */ + , /* LTDC_G4 */ + , /* LTDC_R4 */ + , /* LTDC_R5 */ + , /* LTDC_VSYNC */ + , /* LTDC_R6 */ + , /* LTDC_G3 */ + , /* LTDC_G0 */ + , /* LTDC_R7 */ + , /* LTDC_R2 */ + , /* LTDC_B3 */ + , /* LTDC_G1 */ + , /* LTDC_DE */ + , /* LTDC_HSYNC */ + , /* LTDC_G2 */ + ; /* LTDC_B4 */ + }; + }; +}; \ No newline at end of file diff --git a/board/m5stack/core135/optee-dts/stm32mp13xd.dtsi b/board/m5stack/core135/optee-dts/stm32mp13xd.dtsi new file mode 100644 index 0000000..0e057b3 --- /dev/null +++ b/board/m5stack/core135/optee-dts/stm32mp13xd.dtsi @@ -0,0 +1,22 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelectronics. + */ + +&cpu0_opp_table { + opp-990000000 { + opp-hz = /bits/ 64 <990000000>; + opp-microvolt = <1250000>; + opp-supported-hw = <0x2>; + // st,opp-default; + }; + + opp-650000000 { + opp-hz = /bits/ 64 <650000000>; + opp-microvolt = <1250000>; + opp-supported-hw = <0x2>; + st,opp-default; + }; + +}; \ No newline at end of file diff --git a/board/m5stack/core135/patches/linux/0001-ASoC-cs42l51-fix-driver-to-properly-autoload-with-au.patch b/board/m5stack/core135/patches/linux/0001-ASoC-cs42l51-fix-driver-to-properly-autoload-with-au.patch new file mode 100644 index 0000000..1f3a08f --- /dev/null +++ b/board/m5stack/core135/patches/linux/0001-ASoC-cs42l51-fix-driver-to-properly-autoload-with-au.patch @@ -0,0 +1,89 @@ +From de1ccf088ca0b5ccbfe2afab79a295253fe7d7e3 Mon Sep 17 00:00:00 2001 +From: Thomas Petazzoni +Date: Thu, 13 Jul 2023 12:13:28 +0200 +Subject: [PATCH] ASoC: cs42l51: fix driver to properly autoload with automatic + module loading + +In commit 2cb1e0259f50 ("ASoC: cs42l51: re-hook of_match_table +pointer"), 9 years ago, some random guy fixed the cs42l51 after it was +split into a core part and an I2C part to properly match based on a +Device Tree compatible string. + +However, the fix in this commit is wrong: the MODULE_DEVICE_TABLE(of, +....) is in the core part of the driver, not the I2C part. Therefore, +automatic module loading based on module.alias, based on matching with +the DT compatible string, loads the core part of the driver, but not +the I2C part. And threfore, the i2c_driver is not registered, and the +codec is not known to the system, nor matched with a DT node with the +corresponding compatible string. + +In order to fix that, we move the MODULE_DEVICE_TABLE(of, ...) into +the I2C part of the driver. The cs42l51_of_match[] array is also moved +as well, as it is not possible to have this definition in one file, +and the MODULE_DEVICE_TABLE(of, ...) invocation in another file, due +to how MODULE_DEVICE_TABLE works. + +Thanks to this commit, the I2C part of the driver now properly +autoloads, and thanks to its dependency on the core part, the core +part gets autoloaded as well, resulting in a functional sound card +without having to manually load kernel modules. + +Fixes: 2cb1e0259f50 ("ASoC: cs42l51: re-hook of_match_table pointer") +Cc: stable@vger.kernel.org +Signed-off-by: Thomas Petazzoni +--- + sound/soc/codecs/cs42l51-i2c.c | 6 ++++++ + sound/soc/codecs/cs42l51.c | 7 ------- + sound/soc/codecs/cs42l51.h | 1 - + 3 files changed, 6 insertions(+), 8 deletions(-) + +diff --git a/sound/soc/codecs/cs42l51-i2c.c b/sound/soc/codecs/cs42l51-i2c.c +index b2106ff6a7cb..e7db7bcd0296 100644 +--- a/sound/soc/codecs/cs42l51-i2c.c ++++ b/sound/soc/codecs/cs42l51-i2c.c +@@ -19,6 +19,12 @@ static struct i2c_device_id cs42l51_i2c_id[] = { + }; + MODULE_DEVICE_TABLE(i2c, cs42l51_i2c_id); + ++const struct of_device_id cs42l51_of_match[] = { ++ { .compatible = "cirrus,cs42l51", }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, cs42l51_of_match); ++ + static int cs42l51_i2c_probe(struct i2c_client *i2c) + { + struct regmap_config config; +diff --git a/sound/soc/codecs/cs42l51.c b/sound/soc/codecs/cs42l51.c +index a67cd3ee84e0..a7079ae0ca09 100644 +--- a/sound/soc/codecs/cs42l51.c ++++ b/sound/soc/codecs/cs42l51.c +@@ -823,13 +823,6 @@ int __maybe_unused cs42l51_resume(struct device *dev) + } + EXPORT_SYMBOL_GPL(cs42l51_resume); + +-const struct of_device_id cs42l51_of_match[] = { +- { .compatible = "cirrus,cs42l51", }, +- { } +-}; +-MODULE_DEVICE_TABLE(of, cs42l51_of_match); +-EXPORT_SYMBOL_GPL(cs42l51_of_match); +- + MODULE_AUTHOR("Arnaud Patard "); + MODULE_DESCRIPTION("Cirrus Logic CS42L51 ALSA SoC Codec Driver"); + MODULE_LICENSE("GPL"); +diff --git a/sound/soc/codecs/cs42l51.h b/sound/soc/codecs/cs42l51.h +index a79343e8a54e..125703ede113 100644 +--- a/sound/soc/codecs/cs42l51.h ++++ b/sound/soc/codecs/cs42l51.h +@@ -16,7 +16,6 @@ int cs42l51_probe(struct device *dev, struct regmap *regmap); + void cs42l51_remove(struct device *dev); + int __maybe_unused cs42l51_suspend(struct device *dev); + int __maybe_unused cs42l51_resume(struct device *dev); +-extern const struct of_device_id cs42l51_of_match[]; + + #define CS42L51_CHIP_ID 0x1B + #define CS42L51_CHIP_REV_A 0x00 +-- +2.41.0 + diff --git a/board/m5stack/core135/patches/linux/0002-sund-out_to_pins.patch b/board/m5stack/core135/patches/linux/0002-sund-out_to_pins.patch new file mode 100644 index 0000000..153a2b4 --- /dev/null +++ b/board/m5stack/core135/patches/linux/0002-sund-out_to_pins.patch @@ -0,0 +1,105 @@ +--- a/sound/soc/codecs/out_to_pins.c 2024-03-27 18:41:29.759999974 +0800 ++++ b/sound/soc/codecs/out_to_pins.c 2024-04-11 09:59:33.273128140 +0800 +@@ -0,0 +1,102 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later ++/* ++ * Based on generic Bluetooth SCO link ++ */ ++ ++#include ++#include ++#include ++ ++#include ++ ++static const struct snd_soc_dapm_widget OutToPins_widgets[] = { ++ SND_SOC_DAPM_INPUT("RX"), ++ SND_SOC_DAPM_OUTPUT("TX"), ++}; ++ ++static const struct snd_soc_dapm_route OutToPins_routes[] = { ++ { "Capture", NULL, "RX" }, ++ { "TX", NULL, "Playback" }, ++}; ++ ++static struct snd_soc_dai_driver OutToPins_dai[] = { ++ { ++ .name = "OutToPins-pcm", ++ .playback = { ++ .stream_name = "Playback", ++ .channels_min = 1, ++ .channels_max = 4, ++ .rates = SNDRV_PCM_RATE_CONTINUOUS, ++ /* DMA does not support 24 bits transfers */ ++ .formats = ++ SNDRV_PCM_FMTBIT_S16_LE | ++ SNDRV_PCM_FMTBIT_S32_LE, ++ }, ++ .capture = { ++ .stream_name = "Capture", ++ .channels_min = 1, ++ .channels_max = 4, ++ .rates = SNDRV_PCM_RATE_CONTINUOUS, ++ /* DMA does not support 24 bits transfers */ ++ .formats = ++ SNDRV_PCM_FMTBIT_S16_LE | ++ SNDRV_PCM_FMTBIT_S32_LE, ++ }, ++ }, ++ ++}; ++ ++static int OutToPins_of_xlate_dai_id(struct snd_soc_component *component, ++ struct device_node *endpoint) ++{ ++ /* return dai id 0, whatever the endpoint index */ ++ return 0; ++} ++ ++static const struct snd_soc_component_driver soc_component_dev_OutToPins = { ++ .dapm_widgets = OutToPins_widgets, ++ .num_dapm_widgets = ARRAY_SIZE(OutToPins_widgets), ++ .dapm_routes = OutToPins_routes, ++ .num_dapm_routes = ARRAY_SIZE(OutToPins_routes), ++ .of_xlate_dai_id = OutToPins_of_xlate_dai_id, ++ .idle_bias_on = 1, ++ .use_pmdown_time = 1, ++ .endianness = 1, ++ .legacy_dai_naming = 1, ++}; ++ ++static int OutToPins_probe(struct platform_device *pdev) ++{ ++ return devm_snd_soc_register_component(&pdev->dev, ++ &soc_component_dev_OutToPins, ++ OutToPins_dai, ARRAY_SIZE(OutToPins_dai)); ++} ++ ++static int OutToPins_remove(struct platform_device *pdev) ++{ ++ return 0; ++} ++ ++ ++// #if defined(CONFIG_OF) ++static const struct of_device_id OutToPins_codec_of_match[] = { ++ { .compatible = "OutToPins_codec", }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, OutToPins_codec_of_match); ++// #endif ++ ++static struct platform_driver OutToPins_driver = { ++ .driver = { ++ .name = "OutToPins_codec", ++ .of_match_table = of_match_ptr(OutToPins_codec_of_match), ++ }, ++ .probe = OutToPins_probe, ++ .remove = OutToPins_remove, ++}; ++ ++module_platform_driver(OutToPins_driver); ++ ++MODULE_AUTHOR("martin.lesniak@st.com"); ++MODULE_DESCRIPTION("ASoC generic output driver"); ++MODULE_LICENSE("GPL"); diff --git a/board/m5stack/core135/patches/linux/0003-sund-kconfig.patch b/board/m5stack/core135/patches/linux/0003-sund-kconfig.patch new file mode 100644 index 0000000..dbac581 --- /dev/null +++ b/board/m5stack/core135/patches/linux/0003-sund-kconfig.patch @@ -0,0 +1,12 @@ +--- a/sound/soc/codecs/Kconfig 2024-04-11 10:10:19.544748160 +0800 ++++ b/sound/soc/codecs/Kconfig 2024-04-11 10:10:07.872537410 +0800 +@@ -2162,4 +2162,9 @@ config SND_SOC_LPASS_TX_MACRO + select SND_SOC_LPASS_MACRO_COMMON + tristate "Qualcomm TX Macro in LPASS(Low Power Audio SubSystem)" + ++config OUT_TO_PINS_CODEC ++ tristate "out_to_pins Speaker Amplifier" ++ default m ++ help ++ out_to_pins Speaker Amplifier. + endmenu diff --git a/board/m5stack/core135/patches/linux/0004-sund-makefile.patch b/board/m5stack/core135/patches/linux/0004-sund-makefile.patch new file mode 100644 index 0000000..2e12c9f --- /dev/null +++ b/board/m5stack/core135/patches/linux/0004-sund-makefile.patch @@ -0,0 +1,8 @@ +--- a/sound/soc/codecs/Makefile 2024-04-11 10:11:29.925865817 +0800 ++++ b/sound/soc/codecs/Makefile 2024-04-11 10:11:20.233717760 +0800 +@@ -719,3 +719,5 @@ obj-$(CONFIG_SND_SOC_LPASS_TX_MACRO) += + + # Mux + obj-$(CONFIG_SND_SOC_SIMPLE_MUX) += snd-soc-simple-mux.o ++ ++obj-$(CONFIG_OUT_TO_PINS_CODEC) += out_to_pins.o diff --git a/board/m5stack/core135/patches/linux/0005-fbdev-fb_ili9341_m5.patch b/board/m5stack/core135/patches/linux/0005-fbdev-fb_ili9341_m5.patch new file mode 100644 index 0000000..049426d --- /dev/null +++ b/board/m5stack/core135/patches/linux/0005-fbdev-fb_ili9341_m5.patch @@ -0,0 +1,307 @@ +--- a/drivers/staging/fbtft/fb_ili9341_m5.c 2024-03-27 18:41:29.759999974 +0800 ++++ b/drivers/staging/fbtft/fb_ili9341_m5.c 2024-04-11 10:15:12.533376430 +0800 +@@ -0,0 +1,304 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * FB driver for the ILI9341 LCD display controller ++ * ++ * This display uses 9-bit SPI: Data/Command bit + 8 data bits ++ * For platforms that doesn't support 9-bit, the driver is capable ++ * of emulating this using 8-bit transfer. ++ * This is done by transferring eight 9-bit words in 9 bytes. ++ * ++ * Copyright (C) 2013 Christian Vogelgsang ++ * Based on adafruit22fb.c by Noralf Tronnes ++ */ ++ ++#include ++#include ++#include ++#include ++#include