Tim Newsome bc72695f67 Lots of RISC-V improvements. ...

This represents months of continuing RISC-V work, with too many changes
to list individually. Some improvements:
* Fixed memory leaks.
* Better handling of dbus timeouts.
* Add `riscv expose_custom` command.
* Somewhat deal with cache coherency.
* Deal with more timeouts during block memory accesses.
* Basic debug compliance test.
* Tell gdb which watchpoint hit.
* SMP support for use with -rtos hwthread
* Add `riscv set_ir`

Change-Id: Ica507ee2a57eaf51b578ab1d9b7de71512fdf47f
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: http://openocd.zylin.com/4922
Tested-by: jenkins
Reviewed-by: Philipp Guehring <pg@futureware.at>
Reviewed-by: Liviu Ionescu <ilg@livius.net>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>

2019-03-27 08:53:09 +00:00

..

manual

doc: fix several typos within manual documents

2018-05-09 11:43:23 +01:00

fdl.texi

- update openocd.texi to fdl 1.2

2008-02-29 18:10:46 +00:00

Makefile.am

Convert to non-recursive make

2016-12-08 16:23:10 +00:00

openocd.1

docs: update incorrect urls

2013-03-28 23:24:40 +00:00

openocd.texi

Lots of RISC-V improvements.

2019-03-27 08:53:09 +00:00