Sergio Chico 93a3a82e49 topic: Support for the Xilinx BSCAN_* Virtual JTAG in Openrisc ...

This add support to the Xilinx BSCAN_* virtual JTAG interface.
This is the Xilinx equivalent of the Altera sld_virtual_jtag interface,
it allows a user to connect to the debug unit through the main
FPGA JTAG connection.

Change-Id: Ia438e910650cff9cbc8f810b719fc1d5de5a8188
Signed-off-by: Sergio Chico <sergio.chico@gmail.com>
Reviewed-on: http://openocd.zylin.com/1806
Tested-by: jenkins
Reviewed-by: Franck Jullien <franck.jullien@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>

2013-12-14 21:53:16 +00:00

..

manual

configure: remove AM_MAINTAINER_MODE, effectively always enabling all the rules

2013-07-15 10:13:51 +00:00

fdl.texi

- update openocd.texi to fdl 1.2

2008-02-29 18:10:46 +00:00

INSTALL.txt

Remove annoying end-of-line whitespace from doc/* files.

2009-09-21 18:52:45 +00:00

Makefile.am

build: add missing files to make dist

2011-06-17 12:21:01 +01:00

openocd.1

docs: update incorrect urls

2013-03-28 23:24:40 +00:00

openocd.texi

topic: Support for the Xilinx BSCAN_* Virtual JTAG in Openrisc

2013-12-14 21:53:16 +00:00