Jonathan McDowell d2fb461621 Correct ZynqMP configuration to be appropriately named ...

The xilinx_ultrascale.cfg target is actually the configuration for a
ZynqMP, which is a combination of an UltraScale+ FPGA core and a quad
core A53. Update the filename/comments to reflect this, and include
the tap IDs for all known FPGA cores for this part.

Change-Id: I70dfcc99861a482b83b6a795e83021d9cf1fe047
Signed-off-by: Jonathan McDowell <noodles@earth.li>
Reviewed-on: http://openocd.zylin.com/4850
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>

2019-01-23 15:26:48 +00:00

..

board

Correct ZynqMP configuration to be appropriately named

2019-01-23 15:26:48 +00:00

chip

Fix a typo.

2013-07-07 13:00:59 +00:00

cpld

xilinx-xc7: Add additional IDCODEs.

2018-10-27 14:37:43 +01:00

cpu/arm

Move TCL script files -- Step 2 of 2:

2009-05-27 06:49:24 +00:00

fpga

fpga/altera-10m50: add all device id

2018-07-31 18:56:14 +01:00

interface

stlink: add support for STLINK-V3

2018-12-06 13:06:59 +00:00

target

Correct ZynqMP configuration to be appropriately named

2019-01-23 15:26:48 +00:00

test

TCL scripts: replace "puts" with "echo"

2010-11-09 08:12:51 +01:00

tools

tcl/board: add Linksys WAG200G config

2016-10-17 09:16:33 +01:00

bitsbytes.tcl

TCL scripts: replace "puts" with "echo"

2010-11-09 08:12:51 +01:00

mem_helper.tcl

mem_helper: add mrh command

2018-12-06 09:38:41 +00:00

memory.tcl

target: add "phys" argument to mem2array, array2mem

2016-08-09 14:32:12 +01:00

mmr_helpers.tcl

TCL scripts: replace "puts" with "echo"

2010-11-09 08:12:51 +01:00