Matthias Welwarsky 442e2506b1 cortex_a: force cache and tlb bypass when cpu is in debug state ...

for minimal impact on the hardware state, force all memory accesses to
bypass the caches and tlbs. This may actually be the default, but ARM
recommends in DDI0406C to set proper default values on debug init.

Change-Id: If5ac097b6ee725c047b1e86c2f90eabe16b98c7b
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3079
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: jenkins

2015-11-30 10:07:10 +00:00

..

flash

adi_v5: Fix wrong ap value

2015-11-27 10:38:22 +00:00

helper

helper/options: Use OPENOCD_SCRIPTS dir if set.

2015-11-03 22:19:36 +00:00

jtag

jlink: Retrieve maximum speed from device.

2015-11-26 12:21:30 +00:00

pld

cpld/virtex2: allow JSTART to be disabled

2015-08-06 13:14:01 +01:00

rtos

rtos/mqx: Fix uninitialized parts of symbol table

2015-11-03 21:58:50 +00:00

server

tcl_server: Support line buffers up to 4M (v3)

2015-09-30 22:01:00 +01:00

svf

svf: fix progress reporting switch behaviour

2015-11-20 22:27:48 +00:00

target

cortex_a: force cache and tlb bypass when cpu is in debug state

2015-11-30 10:07:10 +00:00

transport

transport: make 'transport select' auto-select the first available transport if not set

2015-03-25 21:32:49 +00:00

xsvf

update files to correct FSF address

2013-06-05 19:52:42 +00:00

hello.c

update files to correct FSF address

2013-06-05 19:52:42 +00:00

hello.h

update files to correct FSF address

2013-06-05 19:52:42 +00:00

main.c

update files to correct FSF address

2013-06-05 19:52:42 +00:00

Makefile.am

Makefile.am: link libusb-1.0 after libusb-0.1 to fix dependencies

2015-02-04 21:56:45 +00:00

openocd.c

docs: update OpenOCD url's to openocd.org domain

2015-04-16 20:28:21 +01:00

openocd.h

Fix some problems with the bin2char utility

2014-08-02 09:01:32 +00:00