To alleviate the need to bitbang SWD, I've written a SWD SPI
implementation. This code is inspired by the work of luppy@appkaki.com
as shown at github.com/lupyuen/openocd-spi but with the desire to be
more generic. This implementation makes use of the more common 4 wire
SPI port using full duplex transfers to be able to capture the SWD ACK
bits when a SWD TX operation is in progress.
TEST:
Connects successfully with the following combinations:
Hosts:
Raspberry Pi 4B
Unnamed Qualcomm SoC with QUPv3 based SPI port
Targets:
Raspberry Pi 2040
Nordic nRF52840
NXP RT500
Change-Id: Ic2f38a1806085d527e6f999a3d15aea6f32d1019
Signed-off-by: Richard Pasek <rpasek@google.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8645
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: zapb <dev@zapb.de>
Tested-by: jenkins
Previously, Linux assigned gpiochip numbers sequentially depending on
when the chip driver was probed. As RP1 is on the end of a PCIe link, it
is probed later than the on-board chips (including expanders connected
over SPI/I2C). This meant that RP1's gpiochip assignment was at an
offset that could potentially change.
A downstream kernel patch now assigns fixed offsets for RP1 and the
onboard gpiochips. Query the device tree to get proper GPIO_CHIP index.
Change-Id: I759978d4b3021c815a7d9febb41961cd1d3d185c
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/8650
Reviewed-by: Jonathan Bell <jonathan@raspberrypi.com>
Tested-by: jenkins
The RISC-V coprocessor is currently not supported. It is attached to the
DAP via AP#2 but the AP implementation is unknown.
The nRFL54L series uses resistive RAM (RRAM) as non-volatile memory
which can be programmed directly. Since it does not fit in the current
flash memory infrastructure of OpenOCD there is no NVM support so far.
Change-Id: I9934af4fd3bb8b7272954fc4b17638c7dabbbee0
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8609
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
In previous implementation, it was known that it does not perform
full reset, and that some peripherals, such as GLB core,
which handles among other stuff GPIOs, was not reset.
It was presumed, that full reset by software is not possible,
although, by accident, even when comment says that
CTRL_PWRON_RESET is set to 1, it is not
(value written into 0x40000018 supposed to be 0x7, not 0x6).
CTRL_PWRON_RESET indeed triggers full "power-on like" reset,
so this method is implemented in this commit.
There are some workarounds to make reset seamless, without any
error messages, which are described in comments of TCL script.
Only down-side of this reset is, that chip is halted after reset
bit later in BootROM than previous implementation,
but it's still good.
Change-Id: Ife2cdcc6a2d96a2e24039bfec149705baf046318
Signed-off-by: Marek Kraus <gamelaster@outlook.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8529
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Provide cable specific configuration files like for the FTDI interface.
Depcrecate the old configuration files but keep them until the next
release for compatibility reasons.
Change-Id: I436bd60779a107120c9e1b1f0b8a69a39a240ad4
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8514
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
The STLink API that supports dap-direct is available from STLink
firmware v2j24, published in early 2015.
We can reasonably expect that any old STLink still in use today
has got at least one firmware update during the last 10 years.
Most of the board files in upstream OpenOCD still use the STLink
in HLA mode. This limits the test coverage of the dap-direct code,
which was introduced in OpenOCD v0.11.0.
- Rename interface/stlink.cfg as interface/stlink-hla.cfg to still
provide support for HLA, adding a deprecated message.
- Rename interface/stlink-dap.cfg as interface/stlink.cfg to make
dap-direct the default trasport.
- Add a redirect file interface/stlink-dap.cfg for users that have
out-of-tree custom board files.
- Update all the board files to the new setup.
- Remove STLink HLA mentions from the documentation, while adding
a reference to interface/stlink-hla.cfg
Checkpatch-ignore: LONG_LINE
Change-Id: I99366bb03cd3b83f8f408514e657f30e59813063
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8523
Tested-by: jenkins
Reviewed-by: Andrzej Sierżęga <asier70@gmail.com>
The _targets has to be global as it is accessed at the end of this file.
This is already the case for setup_a5x {}, assure it is the same way for
setup_crx{} . Without this change, the _targets at the end of this file
is empty in case the Cortex-R is the boot core, fix this.
Change-Id: I4979e3125ec7d93bbd56eee0096ae1d9c5f6a565
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8470
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
virtex2 refresh replaced virtex2 program, but the even older programming
commands like xc6s_program still suggest the old, now-removed program
command. This changes the warnings to suggest the command that is still
there, and also adds some indication that you will need to use the .pld
name instead of the .tap name.
Change-Id: I292da62a95a9b414c69cdb1bba8a28dfd16a7336
Signed-off-by: Adam Novak <interfect@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8468
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Daniel Anselmi <danselmi@gmx.ch>
Adds initial support for the BL702 series of chips, BL702, BL704 and BL706.
No flash bank support yet.
File name bl702.tcl was chosen over bl70x.tcl, because Bouffalo Lab
uses bl702 to mark the whole series in many of their tools.
The ndmreset bit in the RISC-V Debug Module isn't implemented correctly,
so it doesn't trigger a system reset as it should.
To solve this problem, the software reset is implemented
in the reset-assert-pre hook, which uses best reset method I could find.
What is not reset is the GLB core, which handles GPIOs, pinmux, etc.
The reset mechanism has been extensively tested, and works correctly
for both "reset run" and "reset halt", which the latter
halts very early in the BootROM.
Change-Id: I5ced6eb3902d1b9d9c1bba56f817ec5dc3493cb0
Signed-off-by: Marek Kraus <gamelaster@outlook.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8407
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Direct memory driver swd native configuration for am62a7, am62p and
J722S SoCs. All three share common memory map for the debug address
map, so there is a strong reuse. However, introduce board file
specific to the board to allow users to directly get started.
Change-Id: I5609925a2e9918fd4c91d9fd40fbee98de27fdbc
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8283
Tested-by: jenkins
Reviewed-by: Vaishnav M A <vaishnav@beagleboard.org>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
