Commit Graph

2061 Commits

Author SHA1 Message Date
ntfreak
f7f38fa70d - fixes the incorrect info msg displayed during stellaris flash programming.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2660 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-09-01 10:08:41 +00:00
ntfreak
fbf775c0b7 - fix a regression when using cortex_m3 emulated dcc channel
git-svn-id: svn://svn.berlios.de/openocd/trunk@2659 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-09-01 10:08:00 +00:00
duane
a41725c788 Warning fix
git-svn-id: svn://svn.berlios.de/openocd/trunk@2658 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-31 12:21:12 +00:00
oharboe
2a86a53c3f David Brownell <david-b@pacbell.net> Minor code bugfix: check right variable.
Via code review by Steve Grubb <sgrubb@redhat.com> 

Almost innocuous; this is value is checked later, this
check being wrong would make it check stack garbage.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2655 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-30 21:12:50 +00:00
oharboe
072d6d3db6 Dirk Behme <dirk.behme@googlemail.com> Fix typo in help text. It has to be 'production_test' instead of 'production' here.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2654 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-30 20:08:07 +00:00
oharboe
fbe1c23c12 David Brownell <david-b@pacbell.net> Fix Sandstorm revision checking: right bits, right value!
git-svn-id: svn://svn.berlios.de/openocd/trunk@2653 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-30 20:05:40 +00:00
oharboe
98ae6c24f0 David Brownell <david-b@pacbell.net> Remove duplicate check for flash write status.
Via code review by Steve Grubb <sgrubb@redhat.com> 

Also minor fixes for the message from "fill":  the byte
count is unsigned, not signed; and more importantly,
print the real number of bytes written

git-svn-id: svn://svn.berlios.de/openocd/trunk@2652 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-30 20:04:17 +00:00
oharboe
d879faa3cb David Brownell <david-b@pacbell.net> start phasing out integers as target IDs
git-svn-id: svn://svn.berlios.de/openocd/trunk@2650 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-30 17:30:14 +00:00
oharboe
4b9bdd664a David Brownell <david-b@pacbell.net> Be sure the built-in search paths always go *after* ones provided
on the command line ... matching comment in add_default_dirs().

Without this it's impossible to use a private config file which
happens to have the same name as an installed one.  Say, because
you're bugfixing a private copy...

git-svn-id: svn://svn.berlios.de/openocd/trunk@2649 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-30 17:27:50 +00:00
oharboe
69b8b5e0aa David Brownell <david-b@pacbell.net> fix warnings
git-svn-id: svn://svn.berlios.de/openocd/trunk@2648 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-28 17:18:36 +00:00
oharboe
ed8fd94d7c added arm11 timeout error messages
git-svn-id: svn://svn.berlios.de/openocd/trunk@2647 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-28 13:43:26 +00:00
oharboe
efef05870d restore ICE watchpoint registers when the *last* software breakpoint is removed
git-svn-id: svn://svn.berlios.de/openocd/trunk@2646 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-28 09:47:19 +00:00
oharboe
997d5284cb David Brownell <david-b@pacbell.net> ARM disassembly support for about five dozen non-Thumb instructions
that were added after ARMv5TE was defined:

 - ARMv5J "BXJ" (for Java/Jazelle)
 - ARMv6 "media" instructions (for OMAP2420, i.MX31, etc)

Compile-tested.  This might not set up the simulator right for the
ARMv6 single step support; only BXJ branches though, and docs to
support Jazelle branching are non-public (still, sigh).

ARMv6 instructions known to be mis-handled by this disassembler
include:  UMAAL, LDREX, STREX, CPS, SETEND, RFE, SRS, MCRR2, MRRC2

git-svn-id: svn://svn.berlios.de/openocd/trunk@2644 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-28 06:52:08 +00:00
oharboe
ae17ce23eb arm11 hardware step using simulation + breakpoint. Use "hardware_step enable" command to revert to hardware stepping. Ideally we could retire the "hardware_step enable" command once we no longer believe it to be necessary.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2643 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-27 10:37:01 +00:00
oharboe
c5145ceb19 arm11 single stepping wip - at least we know the next PC now
git-svn-id: svn://svn.berlios.de/openocd/trunk@2642 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-27 07:37:07 +00:00
oharboe
bb000a6f77 arm11 single stepping wip
git-svn-id: svn://svn.berlios.de/openocd/trunk@2641 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-27 07:35:47 +00:00
oharboe
32a2c70d3e refactor arm simulator to allow arm11 code to use it as well - no observable changes otherwise.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2640 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-27 06:50:36 +00:00
oharboe
327ba6cb0a Matt Hsu <matt@0xlab.org> and Holger Hans Peter Freyther <zecke@selfish.org> cortex-a8: Wait for the CPU to be halted/started
With DCCR we are asking the CPU to halt, we should wait until
the CPU has halted before proceeding with the operation.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2638 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-26 19:25:44 +00:00
oharboe
e921fead94 Matt Hsu <matt@0xlab.org> and Holger Hans Peter Freyther <zecke@selfish.org> Print the value that the method didn't like
git-svn-id: svn://svn.berlios.de/openocd/trunk@2637 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-26 19:24:45 +00:00
oharboe
01000e988a Matt Hsu <matt@0xlab.org> and Holger Hans Peter Freyther <zecke@selfish.org> Only dap_ap_select when we are going to do a memory access
in the fast reg case.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2636 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-26 19:23:35 +00:00
oharboe
fc7cd1d85e Matt Hsu <matt@0xlab.org> cortex-a8: Copy some more registers from the documentation
git-svn-id: svn://svn.berlios.de/openocd/trunk@2635 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-26 19:22:28 +00:00
oharboe
56a04a3413 Matt Hsu <matt@0xlab.org> cortex_a8_exec_opcode is writing the ARM instruction into
the ITR register but it will only be executed when the DSCR[13]
bit is set. The documentation is a bit weird as it classifies
the DSCR as read-only but the pseudo code is writing to it as
well. This is working on a beagleboard.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2634 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-26 19:21:26 +00:00
oharboe
f36d0083de Matt Hsu <matt@0xlab.org> Wait for the DTRRX to be full before reading it. Remove the trans_mode change as it is done in the mem_ap_read_atomic_u32 function.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2633 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-26 19:20:25 +00:00
oharboe
56b346447b Matt Hsu <matt@0xlab.org> and Holger Hans Peter Freyther <zecke@selfish.org> Before executing a new instruction wait for the previous
instruction to be finished. This comes from the pseudo code
of the cortex a8 trm.


git-svn-id: svn://svn.berlios.de/openocd/trunk@2632 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-26 19:16:08 +00:00
oharboe
dce1cdc9fb David Brownell <david-b@pacbell.net> Fix segv in jtag_examine_chain(): exit loop on no-tap. Keep
"next iteration" step with the rest of the loop overhead.

Cleanup:  remove spurious whitespace, and an overlong line;
only assign "tap->hasidcode" once.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2631 b42882b7-edfa-0310-969c-e2dbd0fdcd60
2009-08-26 19:06:56 +00:00