Keep using the same indentation rules while initializing struct
command_registration.
Change-Id: I900924600753ee7a72ca45da13db4112ab4b1522
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5015
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
Keep using the same indentation rules while initializing struct
command_registration.
Change-Id: Ie69d9d6a786e1ef0abbcfd3eef89a61206238ebe
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5014
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
Setting of flash_sector::is_erased in flash erase and mass erase
is popular folklore. Make clear it is useless.
Change-Id: Ide397eb6d24fc8fa38931e6c8a0693d39668a5d2
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4768
Tested-by: jenkins
Reviewed-by: Christopher Head <chead@zaber.com>
Instances of struct flash_driver are never written to at runtime. For a
small amount of memory saving and also robustness (fewer things for
stray pointer writes to hit), mark them const.
Change-Id: Iadbbbc2fac0976d892699200000c5f02856729f3
Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/4803
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Use target_addr_t exclusively for comparison of sector boudaries and
address range.
Use the last addres for both address range end and sector end.
It avoids problems with a flash bank mapped at the very end of
target address space.
Change-Id: Idf97c837453d97cbc4cf8a1c76ad799f4142f19e
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4985
Tested-by: jenkins
Reviewed-by: Tim Newsome <tim@sifive.com>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Bit 4 in OPTSR is IWDG1_SW (the code originally called it IWDG1_HW, but
the reference manual refers to it as IWDG1_SW). This is broken out into
a separate variable, independent_watchdog_selection, in stm32x_options.
However, this is not necessary: bit 4 is included in the user_options
field, which includes all of bits 2 through 7, and
independent_watchdog_selection is not referenced anywhere else. Delete
the field and just rely on user_options to transport that bit, along
with all the other bits it contains, between stm32x_read_options and
stm32x_write_options.
Change-Id: I4da63df9272cf091267b956c412b95671ea1d3c9
Signed-off-by: Christopher Head <chead@zaber.com>
Reviewed-on: http://openocd.zylin.com/4744
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This should allow users to configure flash at >32-bit addresses.
Change-Id: I7c9d3c5762579011a2d9708e5317e5765349845c
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: http://openocd.zylin.com/4919
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
The OTP is part of the flash memory. It has 512 (1024 for F7) bytes
and is organized in 16 sectors with 32 (64 for F7) bytes each.
The OTP is exposed as separate flash bank 1 and can be used
with the usual flash commands.
Writing the OTP can be done as follows:
> stm32f2x otp 1 enable
> flash write bank 1 foo.bin 0
> mdw 0x1fff7800 4
> verify_image foo.bin 0x1fff7800
> stm32f2x otp 1 disable
Note: This patch is largely a rebase/cleanup of a patch
from 2012 by Laurent Charpentier and he did most of the work.
No new Clang-Analyzer warnings.
Change-Id: I5e6371f6a7c7a9929c1d7907d6ba4724f9d20d97
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Reviewed-on: http://openocd.zylin.com/829
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Recent patches for STM32L4+ assumed all STM32L4 processors have a dual-
bank option. This is not the case for STM32L4{3,4,5,6}xx processors and
therefore, these processors (like STM32L433) failed when attempting to
flash the second half of the flash memory. This patch fixed this issue.
Tested on STM32L433xC, STM32L476xG and STM32L471xG.
Change-Id: I8262ba4f05190802c5868d753f3e7af50e581811
Signed-off-by: Armin van der Togt <armin@otheruse.nl>
Reviewed-on: http://openocd.zylin.com/4913
Tested-by: jenkins
Reviewed-by: Peter Tettelaar <peter@float-iot.nl>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Mark Schulte <mschulte@lyft.com>
Added id, name, flash size and RAM size for following parts to samc20_parts[]:
SAMC20N18A
SAMC20N17A
And the following to samc21_parts[]:
SAMC21N18A
SAMC21N17A
Change-Id: Ie8cf1c531a60bfaed6e814d436d232afb89dae3f
Signed-off-by: Kevin Vermilion <kevin.vermilion@gmail.com>
Reviewed-on: http://openocd.zylin.com/4880
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Adds ability to change the user data in STM32F1x/STM32F3x MCU's option byte.
Since OpenOCD prints the content of user data in option byte registers, it
is seems logical to also provide a way how to change this data.
Change-Id: Ie6cb756b4f11b5c6dabd34bc89434a358eb758ff
Signed-off-by: Jan Vojtech <honza.vojtech@gmail.com>
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4663
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Without this change xxx_start_algorithm() writes all register
parameters no matter of their direction. It usually results
in writing of uninitialized reg_params[].value - possibly
reported by valgrind.
While on it fix the wrong parameter direction in
kinetis_disable_wdog_algo(). This bug did not have any
impact because of unconditional write of reg_params.
Change-Id: Ia9c6a7b37f77d5eb6e5f5463012dddd50471742b
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4813
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
The new Microchip (former Atmel) series powered by Cortex-M4 looks
very similar to older M0+ powered SAM D2x at the first sight.
Unfortunately the new series differs a lot in important details.
NVMCTRL has different register addresses, moved important bits
and even changed binary command set. An universal driver for all SAM D/E
would be very complicated. That's why a new driver was derived.
Tested on Microchip SAM E54 Xplained Pro kit (board cfg included).
Adjusted for the restructured dap support.
Checked by valgrind and clang static analyzer.
Change-Id: I26c67047a552076f4b207b9b89285a53d69b4ca4
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4272
Tested-by: jenkins
Reviewed-by: Andres Vahter <andres.vahter@gmail.com>
stm32x_write_options() uses stm32x_write_block() at STM32_OB_RDP address.
The change eliminates subtracting bank->base (and later adding it back).
Change-Id: Icdd24afc7178b814be58e6033d4b93fdfb2d2a16
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: http://openocd.zylin.com/4859
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Christopher Head <chead@zaber.com>
samr34/r35 combine SAML21 and SX1276 (lora transceiver). This one was found on
xplaned pro evaluation kit. Ids for other r34/r35 chips are apparently not yet
documented.
Change-Id: I4054dd56ea53c9bae8d17abd5a3e4e65e1b9c8b1
Signed-off-by: Guillaume Revaillot <g.revaillot@gmail.com>
Reviewed-on: http://openocd.zylin.com/4872
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
The functions dap_to_jtag() and dap_to_swd() have been introduced by
3ef9beb52c ("ADIv5 DAP ops switching to JTAG or SWD modes") in
arm_adi_v5.c by using the JTAG queue only.
Later, in 6f8b8593d6 ("ADIv5 transport support moves to separate
files") the functions has been moved in adi_v5_swd.c and adi_v5_jtag.c
but keeping the dependency from JTAG queue.
The functions does not work if the current transport is not JTAG.
Move back the functions in arm_adi_v5.c, replace the input parameter
"target" with "dap", use the transport to detect if the JTAG queue is
present, in case of SWD transport use the proper method, for other
transports report error.
Reuse the ADI v5 sequences already present in jtag/swd.h.
Also, OpenOCD does not support switching to another transport after
the initial selection, so do not change DAP's ops vector.
Change-Id: Ib681fbaa60cb342f732bc831eb92de25afa4e4db
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4852
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
All the commands in OpenOCD have been inspected and have the
command mode initialize, apart for two of them.
This is not critical, because the uninitialized value (0) is
equivalent to the enum COMMAND_EXEC, that is also the correct
value for the two mentioned commands.
To keep the code consistent, initialize the command mode to
COMMAND_EXEC.
Change-Id: Iaf043364cbd1005418d787ed045a3ec653612382
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/4861
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This hardware id is e.g. used by the Insight SiP ISP1507-AX.
Change-Id: I82568d292f9882372ab061d8e3e36906b0cc5882
Signed-off-by: Mirko Vogt <mirko.vogt@sensorberg.com>
Reviewed-on: http://openocd.zylin.com/4845
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Tested-by: jenkins
Valgrind and Clang Static Analyzer have no complaints about this change.
Change-Id: I7757615ec52448372bdc57729cdf97c7016d97e8
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: http://openocd.zylin.com/4656
Tested-by: jenkins
Reviewed-by: Philipp Guehring <pg@futureware.at>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
These devices differ from LPC8xx devices in that they have a different
IAP entry point, but everything else is the same. Using Tcl to pass
different IAP entry point.
no new Clang analyser warnings and no new build sanitizers issues.
Change-Id: I2d654dd250f416e74262c0228cad8713a283402f
Signed-off-by: Rod Boyce <developer@teamboyce.co.uk>
Reviewed-on: http://openocd.zylin.com/4684
Reviewed-by: Jean-Christian de Rivaz <jcamdr70@gmail.com>
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Currently it is impossible to flash ELF with correct offsets. The reason
is a bogus offset calculation extracted from base.
Since any other spi drivers do not care about base, do the same for
ath79 as well.
Change-Id: I9e46e01c9e7a709c2d07da9203c634f302603afd
Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Reviewed-on: http://openocd.zylin.com/4821
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Longest erase all FLASH for nRF5 series is 295.3 ms for nRF52832.
Timeout period now is set to 340 ms (295.3 + 15%)
Change-Id: Iae00ed7b634f111b9798db11e35e4e066d4aaa95
Signed-off-by: Jānis Skujenieks <janis.skujenieks@gmail.com>
Reviewed-on: http://openocd.zylin.com/4822
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
