Add SWD multidrop setting.
Fix the name of AP #1 to AUX-AP
Set AUX-AP CSW Prot bit[0] to make RISC-V debug accessible on AUX-AP.
Change-Id: I496e07acfe90dd858e4403176a8330d8c1a0b560
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/8752
Tested-by: jenkins
Reviewed-by: zapb <dev@zapb.de>
AM261[1] is a optimized cutdown of AM263P SoC. The key difference is
the reduced number of R5F cores which is now dropped down to 2, and
the DIE ID is different from AM263p, but all other definitions are
compatible, so reuse the definition.
[1] https://www.ti.com/product/AM2612
Change-Id: Ib6ca0b59d0b8991df6e4ab349d371187438cb393
Signed-off-by: Shivasharan Nagalikar <shivasharan.nagalikar@ti.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8792
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Tested-by: jenkins
AM263P[1] adds additional features to AM263 SoC. [2] provides a
detailed list of differences, however, the key difference from
processor usage perspective is the increased SRAM and Remote L2(RL2)
Cache for improved performance of R5F. To differentiate the DIE ID
is different, however rest of the processor description remain
compatible to AM263, hence reuse the definition.
[1] https://www.ti.com/product/AM263P4
[2] https://www.ti.com/lit/pdf/spradb3
Change-Id: If47935caf1f995d7e606547e0d6545c39544678a
Signed-off-by: Shivasharan Nagalikar <shivasharan.nagalikar@ti.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8770
Reviewed-by: Nishanth Menon <nm@ti.com>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
TI K3 Debug systems have a Power Access Port (Power-AP) which allows
for functionality such as reset via debugger that using the SPREC
register. SoCs/Boards that do not have support for SRST or TRST can
make use of this to force a system reset via debug access.
Change-Id: Ic5f9cc7f7fba77b353b0c0b42d8afc02502251a0
Signed-off-by: Shivasharan Nagalikar <shivasharan.nagalikar@ti.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8769
Reviewed-by: Nishanth Menon <nm@ti.com>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
BL602, BL702 and BL702L series of chips are sharing same architecture,
so they all need same software reset mechanism as well.
Only difference (in terms of configuration needed for JTAG) are TAP ID,
workarea address and size. This is addressed by creating bl602_common.cfg
tcl file, which contains all those common stuff between the chips.
The script is prefixed by bl602, as this was
first *publicly* available chip from Bouffalo with this architecture.
This patch also improves reset mechanism. Previous reset mechanism did not
worked properly when slower JTAG adapter was used (it attached too late).
New reset mechanism uses various methods to keep CPU in BootROM, until
the JTAG adapter does not attach again after reset. Additionally,
we trigger SW Reset by directly using DMI commands to write to register
with system bus method, to avoid getting error about unsuccessful write.
The new method works on both FT232H (8MHz JTAG clock) and
unnamed CMSIS-DAP dongle (1.5MHz JTAG clock).
Change-Id: I5be3694927793fd3f64c9ed4ee6ded2db0d25cae
Signed-off-by: Marek Kraus <gamelaster@outlook.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8593
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
The RISC-V coprocessor is currently not supported. It is attached to the
DAP via AP#2 but the AP implementation is unknown.
The nRFL54L series uses resistive RAM (RRAM) as non-volatile memory
which can be programmed directly. Since it does not fit in the current
flash memory infrastructure of OpenOCD there is no NVM support so far.
Change-Id: I9934af4fd3bb8b7272954fc4b17638c7dabbbee0
Signed-off-by: Marc Schink <dev@zapb.de>
Reviewed-on: https://review.openocd.org/c/openocd/+/8609
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
In previous implementation, it was known that it does not perform
full reset, and that some peripherals, such as GLB core,
which handles among other stuff GPIOs, was not reset.
It was presumed, that full reset by software is not possible,
although, by accident, even when comment says that
CTRL_PWRON_RESET is set to 1, it is not
(value written into 0x40000018 supposed to be 0x7, not 0x6).
CTRL_PWRON_RESET indeed triggers full "power-on like" reset,
so this method is implemented in this commit.
There are some workarounds to make reset seamless, without any
error messages, which are described in comments of TCL script.
Only down-side of this reset is, that chip is halted after reset
bit later in BootROM than previous implementation,
but it's still good.
Change-Id: Ife2cdcc6a2d96a2e24039bfec149705baf046318
Signed-off-by: Marek Kraus <gamelaster@outlook.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8529
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
The _targets has to be global as it is accessed at the end of this file.
This is already the case for setup_a5x {}, assure it is the same way for
setup_crx{} . Without this change, the _targets at the end of this file
is empty in case the Cortex-R is the boot core, fix this.
Change-Id: I4979e3125ec7d93bbd56eee0096ae1d9c5f6a565
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8470
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Adds initial support for the BL702 series of chips, BL702, BL704 and BL706.
No flash bank support yet.
File name bl702.tcl was chosen over bl70x.tcl, because Bouffalo Lab
uses bl702 to mark the whole series in many of their tools.
The ndmreset bit in the RISC-V Debug Module isn't implemented correctly,
so it doesn't trigger a system reset as it should.
To solve this problem, the software reset is implemented
in the reset-assert-pre hook, which uses best reset method I could find.
What is not reset is the GLB core, which handles GPIOs, pinmux, etc.
The reset mechanism has been extensively tested, and works correctly
for both "reset run" and "reset halt", which the latter
halts very early in the BootROM.
Change-Id: I5ced6eb3902d1b9d9c1bba56f817ec5dc3493cb0
Signed-off-by: Marek Kraus <gamelaster@outlook.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8407
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Direct memory driver swd native configuration for am62a7, am62p and
J722S SoCs. All three share common memory map for the debug address
map, so there is a strong reuse. However, introduce board file
specific to the board to allow users to directly get started.
Change-Id: I5609925a2e9918fd4c91d9fd40fbee98de27fdbc
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8283
Tested-by: jenkins
Reviewed-by: Vaishnav M A <vaishnav@beagleboard.org>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Oleksij Rempel <linux@rempel-privat.de>
The flag '-coreid' is used by the command 'target create' to
specify the debug controller of the target, either in case of a
single debug controller for multiple CPU (e.g. RISC-V harts) or
in case of multiple CPU on a DAP access port (e.g. Cortex-A SMP
cluster).
It is also currently used to specify the CPU ID in a SMP cluster,
but this is going to be reworked.
This flag has no effects on Cortex-M; ARM specifies that only one
CPU Cortex-M can occupy the DAP access port by using hardcoded
addresses.
The flash driver 'psoc6' uses the flag '-coreid' to detect if the
current target is the Cortex-M0 on AP#1 or the Cortex-M4 on AP#2
in the SoC.
There are other ways to run such detection, without using such
unrelated '-coreid' flag, e.g. using the AP number or the arch
type of the target.
Use the arch type to detect Cortex-M0 (ARM_ARCH_V6M) vs Cortex-M4
(ARM_ARCH_V7M).
Drop the flags '-coreid' from the psoc6 configuration file.
Change-Id: I0b9601c160dd4f2421a03ce6e3e7c55c6212f714
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8128
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Both devices can be configured with or without SWD multidrop.
nRF53 network core is examined on demand to avoid problems
when the core is forced off.
Change-Id: I08f88ff48ff7ac592e9214b89ca8e5e9428573a5
Signed-off-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-on: https://review.openocd.org/c/openocd/+/8113
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Tested-by: jenkins
