mirror of
https://github.com/linux-msm/openocd.git
synced 2026-02-25 13:15:07 -08:00
Move TCL script files -- Step 2 of 2:
- Move src/tcl to tcl/. - Update top Makefile.am to use new path name. git-svn-id: svn://svn.berlios.de/openocd/trunk@1919 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
zwelch
@@ -1,61 +0,0 @@
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#----------------------------------------
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# Purpose - Create some $BIT variables
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# Create $K and $M variables
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# and some bit field extraction variables.
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# Creat helper variables ...
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# BIT0.. BIT31
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for { set x 0 } { $x < 32 } { set x [expr $x + 1]} {
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set vn [format "BIT%d" $x]
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global $vn
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set $vn [expr (1 << $x)]
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}
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# Create K bytes values
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# __1K ... to __2048K
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for { set x 1 } { $x < 2048 } { set x [expr $x * 2]} {
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set vn [format "__%dK" $x]
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global $vn
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set $vn [expr (1024 * $x)]
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}
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# Create M bytes values
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# __1M ... to __2048K
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for { set x 1 } { $x < 2048 } { set x [expr $x * 2]} {
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set vn [format "__%dM" $x]
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global $vn
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set $vn [expr (1024 * 1024 * $x)]
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}
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proc create_mask { MSB LSB } {
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return [expr (((1 << ($MSB - $LSB + 1))-1) << $LSB)]
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}
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# Cut Bits $MSB to $LSB out of this value.
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# Example: % format "0x%08x" [extract_bitfield 0x12345678 27 16]
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# Result: 0x02340000
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proc extract_bitfield { VALUE MSB LSB } {
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return [expr [create_mask $MSB $LSB] & $VALUE]
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}
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# Cut bits $MSB to $LSB out of this value
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# and shift (normalize) them down to bit 0.
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#
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# Example: % format "0x%08x" [normalize_bitfield 0x12345678 27 16]
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# Result: 0x00000234
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#
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proc normalize_bitfield { VALUE MSB LSB } {
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return [expr [extract_bitfield $VALUE $MSB $LSB ] >> $LSB]
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}
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proc show_normalize_bitfield { VALUE MSB LSB } {
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set m [create_mask $MSB $LSB]
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set mr [expr $VALUE & $m]
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set sr [expr $mr >> $LSB]
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puts [format "((0x%08x & 0x%08x) -> 0x%08x) >> %2d => (0x%x) %5d " $VALUE $m $mr $LSB $sr $sr]
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return $sr
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}
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@@ -1,10 +0,0 @@
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# This board is from ARM and has an samsung s3c45101x01 chip
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source [find target/samsung_s3c4510.cfg]
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#
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# FIXME:
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# Add (A) sdram configuration
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# Add (B) flash cfi programing configuration
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#
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@@ -1,78 +0,0 @@
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#
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# This is for the "at91rm9200-DK" (not the EK) eval board.
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#
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# The two are probably very simular.... I have DK...
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#
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# It has atmel at91rm9200 chip.
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source [find target/at91rm9200.cfg]
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$_TARGETNAME configure -event gdb-attach { reset init }
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$_TARGETNAME configure -event reset-init { at91rm9200_dk_init }
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#flash bank <driver> <base> <size> <chip_width> <bus_width>
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flash_bank cfi 0x10000000 0x00200000 2 2 0
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proc at91rm9200_dk_init { } {
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# Try to run at 1khz... Yea, that slow!
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# Chip is really running @ 32khz
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jtag_khz 8
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mww 0xfffffc64 0xffffffff
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## disable all clocks but system clock
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mww 0xfffffc04 0xfffffffe
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## disable all clocks to pioa and piob
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mww 0xfffffc14 0xffffffc3
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## master clock = slow cpu = slow
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## (means the CPU is running at 32khz!)
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mww 0xfffffc30 0
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## main osc enable
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mww 0xfffffc20 0x0000ff01
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## program pllA
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mww 0xfffffc28 0x20263e04
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## program pllB
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mww 0xfffffc2c 0x10483e0e
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## let pll settle... sleep 100msec
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sleep 100
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## switch to fast clock
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mww 0xfffffc30 0x202
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## Sleep some - (go read)
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sleep 100
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#========================================
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# CPU now runs at 180mhz
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# SYS runs at 60mhz.
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jtag_khz 40000
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#========================================
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## set memc for all memories
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mww 0xffffff60 0x02
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## program smc controller
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mww 0xffffff70 0x3284
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## init sdram
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mww 0xffffff98 0x7fffffd0
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## all banks precharge
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mww 0xffffff80 0x02
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## touch sdram chip to make it work
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mww 0x20000000 0
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## sdram controller mode register
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mww 0xffffff90 0x04
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mww 0x20000000 0
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mww 0x20000000 0
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mww 0x20000000 0
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mww 0x20000000 0
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mww 0x20000000 0
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mww 0x20000000 0
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mww 0x20000000 0
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mww 0x20000000 0
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## sdram controller mode register
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## Refresh, etc....
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mww 0xffffff90 0x03
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mww 0x20000080 0
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mww 0xffffff94 0x1f4
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mww 0x20000080 0
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mww 0xffffff90 0x10
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mww 0x20000000 0
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mww 0xffffff00 0x01
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}
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@@ -1,46 +0,0 @@
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# Crossbow Technology iMote2
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME imote2
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}
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if { [info exists ENDIAN] } {
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set _ENDIAN $ENDIAN
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} else {
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set _ENDIAN little
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}
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if { [info exists CPUTAPID ] } {
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set _CPUTAPID $CPUTAPID
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} else {
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# force an error till we get a good number
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set _CPUTAPID 0xffffffff
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}
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# PXA271 and an Intel Strataflash of 32 Megabytes (p30)
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#
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# Marvell/Intel PXA270 Script
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# set jtag_nsrst_delay to the delay introduced by your reset circuit
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# the rest of the needed delays are built into the openocd program
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jtag_nsrst_delay 800
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# set the jtag_ntrst_delay to the delay introduced by a reset circuit
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# the rest of the needed delays are built into the openocd program
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jtag_ntrst_delay 0
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#use combined on interfaces or targets that can't set TRST/SRST separately
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reset_config trst_and_srst separate
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#jtag scan chain
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jtag newtap $_CHIPNAME cpu -irlen 7 -ircapture 0x1 -irmask 0x7f -expected-id $_CPUTAPID
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set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
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target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME -variant pxa27x
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$_TARGETNAME configure -work-area-virt 0x0x5c000000 -work-area-phys 0x0x5c000000 -work-area-size 0x10000 -work-area-backup 1
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# maps to PXA internal RAM. If you are using a PXA255
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# you must initialize SDRAM or leave this option off
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#flash bank <driver> <base> <size> <chip_width> <bus_width>
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# works for P30 flash
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flash bank cfi 0x00000000 0x2000000 2 2 0
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@@ -1,127 +0,0 @@
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######################################
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# Target: DIGI ConnectCore Wi-9C
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######################################
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reset_config trst_and_srst
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME ns9360
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}
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if { [info exists ENDIAN] } {
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set _ENDIAN $ENDIAN
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} else {
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# This config file was defaulting to big endian..
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set _ENDIAN big
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}
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# What's a good fallback frequency for this board if RCLK is
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# not available??
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jtag_rclk 1000
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if { [info exists CPUTAPID ] } {
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set _CPUTAPID $CPUTAPID
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} else {
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set _CPUTAPID 0xFFFFFFFF
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}
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set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
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jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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jtag_nsrst_delay 200
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jtag_ntrst_delay 0
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######################
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# Target configuration
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######################
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target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
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$_TARGETNAME configure -event reset-init {
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mww 0x90600104 0x33313333
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mww 0xA0700000 0x00000001 # Enable the memory controller.
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mww 0xA0700024 0x00000006 # Set the refresh counter 6
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mww 0xA0700028 0x00000001 #
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mww 0xA0700030 0x00000001 # Set the precharge period
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mww 0xA0700034 0x00000004 # Active to precharge command period is 16 clock cycles
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mww 0xA070003C 0x00000001 # tAPR
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mww 0xA0700040 0x00000005 # tDAL
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mww 0xA0700044 0x00000001 # tWR
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mww 0xA0700048 0x00000006 # tRC 32 clock cycles
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mww 0xA070004C 0x00000006 # tRFC 32 clock cycles
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mww 0xA0700054 0x00000001 # tRRD
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mww 0xA0700058 0x00000001 # tMRD
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mww 0xA0700100 0x00004280 # Dynamic Config 0 (cs4)
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mww 0xA0700120 0x00004280 # Dynamic Config 1 (cs5)
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mww 0xA0700140 0x00004280 # Dynamic Config 2 (cs6)
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mww 0xA0700160 0x00004280 # Dynamic Config 3 (cs7)
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#
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mww 0xA0700104 0x00000203 # CAS latency is 2 at 100 MHz
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mww 0xA0700124 0x00000203 # CAS latency is 2 at 100 MHz
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mww 0xA0700144 0x00000203 # CAS latency is 2 at 100 MHz
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mww 0xA0700164 0x00000203 # CAS latency is 2 at 100 MHz
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#
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mww 0xA0700020 0x00000103 # issue SDRAM PALL command
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#
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mww 0xA0700024 0x00000001 # Set the refresh counter to be as small as possible
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#
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# Add some dummy writes to give the SDRAM time to settle, it needs two
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# AHB clock cycles, here we poke in the debugger flag, this lets
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# the software know that we are in the debugger
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mww 0xA0900000 0x00000002
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mww 0xA0900000 0x00000002
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mww 0xA0900000 0x00000002
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mww 0xA0900000 0x00000002
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mww 0xA0900000 0x00000002
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#
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mdw 0xA0900000
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mdw 0xA0900000
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mdw 0xA0900000
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mdw 0xA0900000
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mdw 0xA0900000
|
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#
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||||
mww 0xA0700024 0x00000030 # Set the refresh counter to 30
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mww 0xA0700020 0x00000083 # Issue SDRAM MODE command
|
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#
|
||||
# Next we perform a read of RAM.
|
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# mw = move word.
|
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mdw 0x00022000
|
||||
# mw 0x00022000:P, r3 # 22000 for cas2 latency, 32000 for cas 3
|
||||
#
|
||||
mww 0xA0700020 0x00000003 # issue SDRAM NORMAL command
|
||||
mww 0xA0700100 0x00084280 # Enable buffer access
|
||||
mww 0xA0700120 0x00084280 # Enable buffer access
|
||||
mww 0xA0700140 0x00084280 # Enable buffer access
|
||||
mww 0xA0700160 0x00084280 # Enable buffer access
|
||||
|
||||
#Set byte lane state (static mem 1)"
|
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mww 0xA0700220, 0x00000082
|
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#Flash Start
|
||||
mww 0xA09001F8, 0x50000000
|
||||
#Flash Mask Reg
|
||||
mww 0xA09001FC, 0xFF000001
|
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mww 0xA0700028, 0x00000001
|
||||
|
||||
# RAMAddr = 0x00020000
|
||||
# RAMSize = 0x00004000
|
||||
|
||||
# Set the processor mode
|
||||
reg cpsr 0xd3
|
||||
}
|
||||
|
||||
$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00000000 -work-area-size 0x1000 -work-area-backup 1
|
||||
|
||||
#####################
|
||||
# Flash configuration
|
||||
#####################
|
||||
|
||||
#M29DW323DB - not working
|
||||
#flash bank cfi <base> <size> <chip width> <bus width> <target#>
|
||||
flash bank cfi 0x50000000 0x0400000 2 2 0
|
||||
|
||||
|
||||
|
||||
@@ -1,119 +0,0 @@
|
||||
#
|
||||
# DM355 EVM board
|
||||
# http://focus.ti.com/docs/toolsw/folders/print/tmdsevm355.html
|
||||
# http://c6000.spectrumdigital.com/evmdm355/
|
||||
|
||||
source [find target/ti_dm355.cfg]
|
||||
|
||||
reset_config trst_and_srst separate
|
||||
|
||||
# NOTE: disable or replace this call to dm355evm_init if you're
|
||||
# debugging new UBL code from SRAM.
|
||||
$_TARGETNAME configure -event reset-init { dm355evm_init }
|
||||
|
||||
#
|
||||
# This post-reset init is called when the MMU isn't active, all IRQs
|
||||
# are disabled, etc. It should do most of what a UBL does, except for
|
||||
# loading code (like U-Boot) into DRAM and running it.
|
||||
#
|
||||
proc dm355evm_init {} {
|
||||
global dm355
|
||||
|
||||
puts "Initialize DM355 EVM board"
|
||||
|
||||
# CLKIN = 24 MHz ... can't talk quickly to ARM yet
|
||||
jtag_khz 1500
|
||||
|
||||
########################
|
||||
# PLL1 = 432 MHz (/8, x144)
|
||||
# ...SYSCLK1 = 216 MHz (/2) ... ARM, MJCP
|
||||
# ...SYSCLK2 = 108 MHz (/4) ... Peripherals
|
||||
# ...SYSCLK3 = 27 MHz (/16) ... VPBE, DAC
|
||||
# ...SYSCLK4 = 108 MHz (/4) ... VPSS
|
||||
# pll1.{prediv,div1,div2} are fixed
|
||||
# pll1.postdiv set in MISC (for *this* speed grade)
|
||||
|
||||
set addr [dict get $dm355 pllc1]
|
||||
set pll_divs [dict create]
|
||||
dict set pll_divs div3 16
|
||||
dict set pll_divs div4 8
|
||||
pll_setup $addr 144 $pll_divs
|
||||
|
||||
# ARM is now running at 216 MHz, so JTAG can go faster
|
||||
jtag_khz 20000
|
||||
|
||||
########################
|
||||
# PLL2 = 342 MHz (/8, x114)
|
||||
# ....SYSCLK1 = 342 MHz (/1) ... DDR PHY at 171 MHz, 2x clock
|
||||
# pll2.{postdiv,div1} are fixed
|
||||
|
||||
set addr [dict get $dm355 pllc2]
|
||||
set pll_divs [dict create]
|
||||
dict set pll_divs prediv 8
|
||||
pll_setup $addr 114 $pll_divs
|
||||
|
||||
########################
|
||||
# PINMUX
|
||||
|
||||
# All Video Inputs
|
||||
davinci_pinmux $dm355 0 0x00007f55
|
||||
# All Video Outputs
|
||||
davinci_pinmux $dm355 1 0x00145555
|
||||
# EMIFA (NOTE: more could be set up for use as GPIOs)
|
||||
davinci_pinmux $dm355 2 0x00000c08
|
||||
# SPI0, SPI1, UART1, I2C, SD0, SD1, McBSP0, CLKOUTs
|
||||
davinci_pinmux $dm355 3 0x1bff55ff
|
||||
# MMC/SD0 instead of MS; SPI0
|
||||
davinci_pinmux $dm355 4 0x00000000
|
||||
|
||||
########################
|
||||
# PSC setup (minimal)
|
||||
|
||||
# DDR EMIF/13, AEMIF/14, UART0/19
|
||||
psc_enable 13
|
||||
psc_enable 14
|
||||
psc_enable 19
|
||||
psc_go
|
||||
|
||||
########################
|
||||
# DDR2 EMIF
|
||||
|
||||
# FIXME setup
|
||||
|
||||
########################
|
||||
# ASYNC EMIF
|
||||
|
||||
set addr [dict get $dm355 a_emif]
|
||||
|
||||
# slow/pessimistic timings
|
||||
set nand_timings 0x40400204
|
||||
# fast (25% faster page reads)
|
||||
#set nand_timings 0x0400008c
|
||||
|
||||
# AWCCR
|
||||
mww [expr $addr + 0x04] 0xff
|
||||
# CS0 == socketed NAND (default MT29F16G08FAA, 2GByte)
|
||||
mww [expr $addr + 0x10] $nand_timings
|
||||
# CS1 == dm9000 Ethernet
|
||||
mww [expr $addr + 0x14] 0x00a00505
|
||||
# NANDFCR -- only CS0 has NAND
|
||||
mww [expr $addr + 0x60] 0x01
|
||||
|
||||
########################
|
||||
# UART0
|
||||
|
||||
# FIXME setup
|
||||
}
|
||||
|
||||
# NAND -- socket has two chipselects, MT29F16G08FAA puts 1GByte on each one.
|
||||
#
|
||||
# NOTE: "hwecc4" here presumes that if you're using the standard 2GB NAND
|
||||
# you either (a) have 'new' DM355 chips, with boot ROMs that don't need to
|
||||
# use "hwecc4_infix" for the UBL; or else (b) aren't updating anything that
|
||||
# needs infix layout ... like an old UBL, old U-Boot, old MVL kernel, etc.
|
||||
nand device davinci 0 0x02000000 hwecc4 0x01e10000
|
||||
nand device davinci 0 0x02004000 hwecc4 0x01e10000
|
||||
|
||||
# FIXME
|
||||
# - support writing UBL with its header (new layout only with new ROMs)
|
||||
# - support writing ABL/U-Boot with its header (new layout)
|
||||
@@ -1,94 +0,0 @@
|
||||
# Elector Internet Radio board
|
||||
# http://www.ethernut.de/en/hardware/eir/index.html
|
||||
|
||||
source [find target/sam7se512.cfg]
|
||||
|
||||
$_TARGETNAME configure -event reset-init {
|
||||
# WDT_MR, disable watchdog
|
||||
mww 0xFFFFFD44 0x00008000
|
||||
|
||||
# RSTC_MR, enable user reset
|
||||
mww 0xfffffd08 0xa5000001
|
||||
|
||||
# CKGR_MOR
|
||||
mww 0xFFFFFC20 0x00000601
|
||||
sleep 10
|
||||
|
||||
# CKGR_PLLR
|
||||
mww 0xFFFFFC2C 0x00481c0e
|
||||
sleep 10
|
||||
|
||||
# PMC_MCKR
|
||||
mww 0xFFFFFC30 0x00000007
|
||||
sleep 10
|
||||
|
||||
# PMC_IER
|
||||
mww 0xFFFFFF60 0x00480100
|
||||
|
||||
#
|
||||
# Enable SDRAM interface.
|
||||
#
|
||||
|
||||
# Enable SDRAM control at PIO A.
|
||||
mww 0xfffff474 0x3f800000 # PIO_BSR_OFF
|
||||
mww 0xfffff404 0x3f800000 # PIO_PDR_OFF
|
||||
|
||||
# Enable address bus (A0, A2-A11, A13-A17) at PIO B
|
||||
mww 0xfffff674 0x0003effd # PIO_BSR_OFF
|
||||
mww 0xfffff604 0x0003effd # PIO_PDR_OFF
|
||||
|
||||
# Enable 16 bit data bus at PIO C
|
||||
mww 0xfffff870 0x0000ffff # PIO_ASR_OFF
|
||||
mww 0xfffff804 0x0000ffff # PIO_PDR_OFF
|
||||
|
||||
# Enable SDRAM chip select
|
||||
mww 0xffffff80 0x00000002 # EBI_CSA_OFF
|
||||
|
||||
# Set SDRAM characteristics in configuration register.
|
||||
# Hard coded values for MT48LC32M16A2 with 48MHz CPU.
|
||||
mww 0xffffffb8 0x2192215a # SDRAMC_CR_OFF
|
||||
sleep 10
|
||||
|
||||
# Issue 16 bit SDRAM command: NOP
|
||||
mww 0xffffffb0 0x00000011 # SDRAMC_MR_OFF
|
||||
mww 0x20000000 0x00000000
|
||||
|
||||
# Issue 16 bit SDRAM command: Precharge all
|
||||
mww 0xffffffb0 0x00000012 # SDRAMC_MR_OFF
|
||||
mww 0x20000000 0x00000000
|
||||
|
||||
# Issue 8 auto-refresh cycles
|
||||
mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
|
||||
mww 0x20000000 0x00000000
|
||||
mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
|
||||
mww 0x20000000 0x00000000
|
||||
mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
|
||||
mww 0x20000000 0x00000000
|
||||
mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
|
||||
mww 0x20000000 0x00000000
|
||||
mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
|
||||
mww 0x20000000 0x00000000
|
||||
mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
|
||||
mww 0x20000000 0x00000000
|
||||
mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
|
||||
mww 0x20000000 0x00000000
|
||||
mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
|
||||
mww 0x20000000 0x00000000
|
||||
|
||||
# Issue 16 bit SDRAM command: Set mode register
|
||||
mww 0xffffffb0 0x00000013 # SDRAMC_MR_OFF
|
||||
mww 0x20000014 0xcafedede
|
||||
|
||||
# Set refresh rate count ???
|
||||
mww 0xffffffb4 0x00000013 # SDRAMC_TR_OFF
|
||||
|
||||
# Issue 16 bit SDRAM command: Normal mode
|
||||
mww 0xffffffb0 0x00000010 # SDRAMC_MR_OFF
|
||||
mww 0x20000000 0x00000180
|
||||
|
||||
#
|
||||
# Enable external reset key.
|
||||
#
|
||||
mww 0xfffffd08 0xa5000001
|
||||
}
|
||||
|
||||
@@ -1,36 +0,0 @@
|
||||
# Target Configuration for the TinCanTools S3C2410 Based Hammer Module
|
||||
# http://www.tincantools.com
|
||||
|
||||
source [find target/samsung_s3c2410.cfg]
|
||||
|
||||
$_TARGETNAME configure -event reset-init {
|
||||
# Reset Script for the TinCanTools S3C2410 Based Hammer Module
|
||||
# http://www.tincantools.com
|
||||
#
|
||||
# Setup primary clocks and initialize the SDRAM
|
||||
mww 0x53000000 0x00000000
|
||||
mww 0x4a000008 0xffffffff
|
||||
mww 0x4a00000c 0x000007ff
|
||||
mww 0x4c000000 0x00ffffff
|
||||
mww 0x4c000014 0x00000003
|
||||
mww 0x4c000004 0x000a1031
|
||||
mww 0x48000000 0x11111122
|
||||
mww 0x48000004 0x00000700
|
||||
mww 0x48000008 0x00000700
|
||||
mww 0x4800000c 0x00000700
|
||||
mww 0x48000010 0x00000700
|
||||
mww 0x48000014 0x00000700
|
||||
mww 0x48000018 0x00000700
|
||||
mww 0x4800001c 0x00018005
|
||||
mww 0x48000020 0x00018005
|
||||
mww 0x48000024 0x009c0459
|
||||
mww 0x48000028 0x000000b2
|
||||
mww 0x4800002c 0x00000030
|
||||
mww 0x48000030 0x00000030
|
||||
flash probe 0
|
||||
}
|
||||
|
||||
|
||||
#flash configuration
|
||||
#flash bank <driver> <base> <size> <chip_width> <bus_width> [driver_options ...]
|
||||
flash bank cfi 0x00000000 0x1000000 2 2 0
|
||||
@@ -1,50 +0,0 @@
|
||||
# Hitex stm32 performance stick
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME stm32_hitex
|
||||
}
|
||||
|
||||
if { [info exists ENDIAN] } {
|
||||
set _ENDIAN $ENDIAN
|
||||
} else {
|
||||
set _ENDIAN little
|
||||
}
|
||||
|
||||
# set jtag speed
|
||||
jtag_khz 500
|
||||
|
||||
jtag_nsrst_delay 100
|
||||
jtag_ntrst_delay 100
|
||||
|
||||
#use combined on interfaces or targets that can't set TRST/SRST separately
|
||||
reset_config trst_and_srst
|
||||
|
||||
#jtag scan chain
|
||||
# The CPU
|
||||
if { [info exists CPUTAPID ] } {
|
||||
set _CPUTAPID $CPUTAPID
|
||||
} else {
|
||||
# See STM Document RM0008
|
||||
# Section 26.6.3
|
||||
set _CPUTAPID 0x3ba00477
|
||||
}
|
||||
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
|
||||
|
||||
# The boundery scan register, leave the "expected-id" undefined.
|
||||
jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1
|
||||
|
||||
# configure str750 connected to jtag chain
|
||||
jtag newtap $_CHIPNAME unknown -irlen 4 -ircapture 0x1 -irmask 0x0f
|
||||
|
||||
set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
|
||||
target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
|
||||
|
||||
$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 16384 -work-area-backup 0
|
||||
|
||||
#
|
||||
flash bank stm32x 0 0 0 0 0
|
||||
|
||||
# For more information about the configuration files, take a look at:
|
||||
# openocd.texi
|
||||
@@ -1,72 +0,0 @@
|
||||
# Hitex STR9-comStick
|
||||
# http://www.hitex.com/index.php?id=383
|
||||
# This works for the STR9-comStick revisions STR912CS-A1 and STR912CS-A2.
|
||||
|
||||
source [find interface/hitex_str9-comstick.cfg]
|
||||
|
||||
# set jtag speed
|
||||
jtag_khz 3000
|
||||
|
||||
jtag_nsrst_delay 100
|
||||
jtag_ntrst_delay 100
|
||||
#use combined on interfaces or targets that can't set TRST/SRST separately
|
||||
reset_config trst_and_srst
|
||||
#jtag scan chain
|
||||
#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
|
||||
|
||||
if { [info exists CHIPNAME] } {
|
||||
set _CHIPNAME $CHIPNAME
|
||||
} else {
|
||||
set _CHIPNAME str912
|
||||
}
|
||||
|
||||
if { [info exists ENDIAN] } {
|
||||
set _ENDIAN $ENDIAN
|
||||
} else {
|
||||
set _ENDIAN little
|
||||
}
|
||||
|
||||
if { [info exists FLASHTAPID ] } {
|
||||
set _FLASHTAPID $FLASHTAPID
|
||||
} else {
|
||||
set _FLASHTAPID 0x04570041
|
||||
}
|
||||
jtag newtap $_CHIPNAME flash -irlen 8 -ircapture 0x1 -irmask 0x1 -expected-id $_FLASHTAPID
|
||||
|
||||
if { [info exists CPUTAPID ] } {
|
||||
set _CPUTAPID $CPUTAPID
|
||||
} else {
|
||||
set _CPUTAPID 0x25966041
|
||||
}
|
||||
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
|
||||
|
||||
if { [info exists BSTAPID ] } {
|
||||
set _BSTAPID $BSTAPID
|
||||
} else {
|
||||
# Found on STR9-comStick, revision STR912CS-A1
|
||||
set _BSTAPID1 0x1457f041
|
||||
# Found on STR9-comStick, revision STR912CS-A2
|
||||
set _BSTAPID2 0x2457f041
|
||||
}
|
||||
jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID1 -expected-id $_BSTAPID2
|
||||
|
||||
set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
|
||||
target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm966e
|
||||
|
||||
$_TARGETNAME configure -event reset-init {
|
||||
# We can increase speed now that we know the target is halted.
|
||||
#jtag_rclk 3000
|
||||
|
||||
# -- Enable 96K RAM
|
||||
# PFQBC enabled / DTCM & AHB wait-states disabled
|
||||
mww 0x5C002034 0x0191
|
||||
|
||||
str9x flash_config 0 4 2 0 0x80000
|
||||
flash protect 0 0 7 off
|
||||
}
|
||||
|
||||
$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x50000000 -work-area-size 16384 -work-area-backup 0
|
||||
|
||||
#flash bank <driver> <base> <size> <chip_width> <bus_width>
|
||||
flash bank str9x 0x00000000 0x00080000 0 0 0
|
||||
flash bank str9x 0x00080000 0x00008000 0 0 0
|
||||
@@ -1,3 +0,0 @@
|
||||
# The IAR str912-sk evaluation kick start board has an str912
|
||||
|
||||
source [find target/str912.cfg]
|
||||
@@ -1,75 +0,0 @@
|
||||
# The IMX27 ADS eval board has a single IMX27 chip
|
||||
# Note: tested on IMX27ADS Board REV-2.6 and REV-2.8
|
||||
source [find target/imx27.cfg]
|
||||
$_TARGETNAME configure -event gdb-attach { reset init }
|
||||
$_TARGETNAME configure -event reset-init { imx27ads_init }
|
||||
|
||||
# The IMX27 ADS board has a NOR flash on CS0
|
||||
flash_bank cfi 0xc0000000 0x00200000 2 2 0
|
||||
|
||||
proc imx27ads_init { } {
|
||||
# This setup puts RAM at 0xA0000000
|
||||
|
||||
# reset the board correctly
|
||||
reset run
|
||||
reset halt
|
||||
|
||||
mww 0x10000000 0x20040304
|
||||
mww 0x10020000 0x00000000
|
||||
mww 0x10000004 0xDFFBFCFB
|
||||
mww 0x10020004 0xFFFFFFFF
|
||||
|
||||
sleep 100
|
||||
|
||||
# ========================================
|
||||
# Configure DDR on CSD0 -- initial reset
|
||||
# ========================================
|
||||
mww 0xD8001010 0x00000008
|
||||
|
||||
# ========================================
|
||||
# Configure PSRAM on CS5
|
||||
# ========================================
|
||||
mww 0xd8002050 0x0000dcf6
|
||||
mww 0xd8002054 0x444a4541
|
||||
mww 0xd8002058 0x44443302
|
||||
|
||||
# ========================================
|
||||
# Configure16 bit NorFlash on CS0
|
||||
# ========================================
|
||||
mww 0xd8002000 0x0000CC03
|
||||
mww 0xd8002004 0xa0330D01
|
||||
mww 0xd8002008 0x00220800
|
||||
|
||||
# ========================================
|
||||
# Configure CPLD on CS4
|
||||
# ========================================
|
||||
mww 0xd8002040 0x0000DCF6
|
||||
mww 0xd8002044 0x444A4541
|
||||
mww 0xd8002048 0x44443302
|
||||
|
||||
# ========================================
|
||||
# Configure DDR on CSD0 -- wait 5000 cycle
|
||||
# ========================================
|
||||
mww 0x10027828 0x55555555
|
||||
mww 0x10027830 0x55555555
|
||||
mww 0x10027834 0x55555555
|
||||
mww 0x10027838 0x00005005
|
||||
mww 0x1002783C 0x15555555
|
||||
|
||||
mww 0xD8001010 0x00000004
|
||||
|
||||
mww 0xD8001004 0x00795729
|
||||
|
||||
mww 0xD8001000 0x92200000
|
||||
mww 0xA0000F00 0x0
|
||||
|
||||
mww 0xD8001000 0xA2200000
|
||||
mww 0xA0000F00 0x0
|
||||
mww 0xA0000F00 0x0
|
||||
|
||||
mww 0xD8001000 0xB2200000
|
||||
mwb 0xA0000033 0xFF
|
||||
mwb 0xA1000000 0xAA
|
||||
|
||||
mww 0xD8001000 0x82228085
|
||||
}
|
||||
@@ -1,59 +0,0 @@
|
||||
# The Linuxstamp-mx27 is board has a single IMX27 chip
|
||||
# For further info see http://opencircuits.com/Linuxstamp_mx27#OpenOCD
|
||||
source [find target/imx27.cfg]
|
||||
$_TARGETNAME configure -event gdb-attach { reset init }
|
||||
$_TARGETNAME configure -event reset-init { imx27lnst_init }
|
||||
|
||||
proc imx27lnst_init { } {
|
||||
# This setup puts RAM at 0xA0000000
|
||||
|
||||
# reset the board correctly
|
||||
jtag_khz 500
|
||||
reset run
|
||||
reset halt
|
||||
|
||||
mww 0x10000000 0x20040304
|
||||
mww 0x10020000 0x00000000
|
||||
mww 0x10000004 0xDFFBFCFB
|
||||
mww 0x10020004 0xFFFFFFFF
|
||||
|
||||
sleep 100
|
||||
|
||||
# ========================================
|
||||
# Configure DDR on CSD0 -- initial reset
|
||||
# ========================================
|
||||
mww 0xD8001010 0x00000008
|
||||
|
||||
sleep 100
|
||||
|
||||
# ========================================
|
||||
# Configure DDR on CSD0 -- wait 5000 cycle
|
||||
# ========================================
|
||||
mww 0x10027828 0x55555555
|
||||
mww 0x10027830 0x55555555
|
||||
mww 0x10027834 0x55555555
|
||||
mww 0x10027838 0x00005005
|
||||
mww 0x1002783C 0x15555555
|
||||
|
||||
mww 0xD8001010 0x00000004
|
||||
|
||||
mww 0xD8001004 0x00795729
|
||||
|
||||
#mww 0xD8001000 0x92200000
|
||||
mww 0xD8001000 0x91120000
|
||||
mww 0xA0000F00 0x0
|
||||
|
||||
#mww 0xD8001000 0xA2200000
|
||||
mww 0xD8001000 0xA1120000
|
||||
mww 0xA0000F00 0x0
|
||||
mww 0xA0000F00 0x0
|
||||
|
||||
#mww 0xD8001000 0xB2200000
|
||||
mww 0xD8001000 0xB1120000
|
||||
mwb 0xA0000033 0xFF
|
||||
mwb 0xA1000000 0xAA
|
||||
|
||||
#mww 0xD8001000 0x82228085
|
||||
mww 0xD8001000 0x81128080
|
||||
|
||||
}
|
||||
@@ -1,101 +0,0 @@
|
||||
# The IMX31PDK eval board has a single IMX31 chip
|
||||
source [find target/imx31.cfg]
|
||||
$_TARGETNAME configure -event gdb-attach { reset init }
|
||||
$_TARGETNAME configure -event reset-init { imx31pdk_init }
|
||||
|
||||
proc imx31pdk_init { } {
|
||||
# This setup puts RAM at 0x80000000
|
||||
|
||||
# reset the board correctly
|
||||
reset run
|
||||
reset halt
|
||||
|
||||
# ========================================
|
||||
# Init CCM
|
||||
# ========================================
|
||||
mww 0x53FC0000 0x040
|
||||
mww 0x53F80000 0x074B0B7D
|
||||
|
||||
sleep 100
|
||||
|
||||
# ========================================
|
||||
# 399MHz - 26MHz input, PD=1,MFI=7, MFN=27, MFD=40
|
||||
# ========================================
|
||||
mww 0x53F80004 0xFF871D50
|
||||
mww 0x53F80010 0x00271C1B
|
||||
|
||||
# ========================================
|
||||
# Configure CPLD on CS5
|
||||
# ========================================
|
||||
mww 0xb8002050 0x0000DCF6
|
||||
mww 0xb8002054 0x444A4541
|
||||
mww 0xb8002058 0x44443302
|
||||
|
||||
# ========================================
|
||||
# SDCLK
|
||||
# ========================================
|
||||
mww 0x43FAC26C 0
|
||||
|
||||
# ========================================
|
||||
# CAS
|
||||
# ========================================
|
||||
mww 0x43FAC270 0
|
||||
|
||||
# ========================================
|
||||
# RAS
|
||||
# ========================================
|
||||
mww 0x43FAC274 0
|
||||
|
||||
# ========================================
|
||||
# CS2 (CSD0)
|
||||
# ========================================
|
||||
mww 0x43FAC27C 0x1000
|
||||
|
||||
# ========================================
|
||||
# DQM3
|
||||
# ========================================
|
||||
mww 0x43FAC284 0
|
||||
|
||||
# ========================================
|
||||
# DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC)
|
||||
# ========================================
|
||||
mww 0x43FAC288 0
|
||||
mww 0x43FAC28C 0
|
||||
mww 0x43FAC290 0
|
||||
mww 0x43FAC294 0
|
||||
mww 0x43FAC298 0
|
||||
mww 0x43FAC29C 0
|
||||
mww 0x43FAC2A0 0
|
||||
mww 0x43FAC2A4 0
|
||||
mww 0x43FAC2A8 0
|
||||
mww 0x43FAC2AC 0
|
||||
mww 0x43FAC2B0 0
|
||||
mww 0x43FAC2B4 0
|
||||
mww 0x43FAC2B8 0
|
||||
mww 0x43FAC2BC 0
|
||||
mww 0x43FAC2C0 0
|
||||
mww 0x43FAC2C4 0
|
||||
mww 0x43FAC2C8 0
|
||||
mww 0x43FAC2CC 0
|
||||
mww 0x43FAC2D0 0
|
||||
mww 0x43FAC2D4 0
|
||||
mww 0x43FAC2D8 0
|
||||
mww 0x43FAC2DC 0
|
||||
|
||||
# ========================================
|
||||
# Initialization script for 32 bit DDR on MX31 PDK
|
||||
# ========================================
|
||||
mww 0xB8001010 0x00000004
|
||||
mww 0xB8001004 0x006ac73a
|
||||
mww 0xB8001000 0x92100000
|
||||
mww 0x80000f00 0x12344321
|
||||
mww 0xB8001000 0xa2100000
|
||||
mww 0x80000000 0x12344321
|
||||
mww 0x80000000 0x12344321
|
||||
mww 0xB8001000 0xb2100000
|
||||
mwb 0x80000033 0xda
|
||||
mwb 0x81000000 0xff
|
||||
mww 0xB8001000 0x82226080
|
||||
mww 0x80000000 0xDEADBEEF
|
||||
mww 0xB8001010 0x0000000c
|
||||
}
|
||||
@@ -1,8 +0,0 @@
|
||||
#
|
||||
# Keil MCB2140 eval board
|
||||
#
|
||||
# http://www.keil.com/mcb2140/picture.asp
|
||||
#
|
||||
|
||||
source [find target/lpc2148.cfg]
|
||||
|
||||
@@ -1,8 +0,0 @@
|
||||
# This is for the LinkSys (CISCO) NSLU2 board
|
||||
# It is an Intel XSCALE IXP420 CPU.
|
||||
|
||||
source [find target/ixp42x.cfg]
|
||||
# The _TARGETNAME is set by the above.
|
||||
|
||||
$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00020000 -work-area-size 0x10000 -work-area-backup 0
|
||||
|
||||
@@ -1,12 +0,0 @@
|
||||
# The LogicPD Eval IMX27 eval board has a single IMX27 chip
|
||||
source [find target/imx27.cfg]
|
||||
|
||||
# The Logic PD board has a NOR flash on CS0
|
||||
flash_bank cfi 0xc0000000 0x00200000 2 2 0
|
||||
|
||||
#
|
||||
# FIX ME, Add support to
|
||||
#
|
||||
# (A) hard reset the board.
|
||||
# (B) Initialize the SDRAM on the board
|
||||
#
|
||||
@@ -1,11 +0,0 @@
|
||||
#####################################################
|
||||
# Olimex LPC2378STK eval board
|
||||
#
|
||||
# http://olimex.com/dev/lpc-2378stk.html
|
||||
#
|
||||
# Author: Sten, debian@sansys-electronic.com
|
||||
#####################################################
|
||||
#
|
||||
|
||||
source [find target/lpc2378.cfg]
|
||||
|
||||
@@ -1,8 +0,0 @@
|
||||
#
|
||||
# Olimex LPC-H2148 eval board
|
||||
#
|
||||
# http://www.olimex.com/dev/lpc-h2148.html
|
||||
#
|
||||
|
||||
source [find target/lpc2148.cfg]
|
||||
|
||||
@@ -1,4 +0,0 @@
|
||||
# Olimex SAM7-EX256 has a single Atmel at91sam7ex256 on it.
|
||||
|
||||
source [find target/sam7x256.cfg]
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user