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- added support for setting JTAG frequency on ASIX PRESTO (thanks to Pavel Chromy)

Browse Source 
- usbprog update (thanks to Benedikt Sauter)
- added embeddedice_send and _handshake functions (thanks to Pavel Chromy)
- added support for 4, 8 and 16 bit ports to etb.c



git-svn-id: svn://svn.berlios.de/openocd/trunk@203 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
drath
2007-08-25 09:59:42 +00:00
parent ecfc1e39a2
commit b930514e2f
6 changed files with 439 additions and 215 deletions
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20
src/jtag/presto.c
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@@ -656,11 +656,26 @@ int presto_bitq_reset(int trst, int srst)
/* -------------------------------------------------------------------------- */
char *presto_speed_text[4] =
{
"3 MHz",
"1.5 MHz",
"750 kHz",
"93.75 kHz"
};
int presto_jtag_speed(int speed)
{
if ((speed < 0) || (speed > 3))
{
INFO("valid speed values: 0 (3 MHz), 1 (1.5 MHz), 2 (750 kHz) and 3 (93.75 kHz)");
return ERROR_INVALID_ARGUMENTS;
}
jtag_speed = speed;
return ERROR_OK;
INFO("setting speed to %d, max. TCK freq. is %s", speed, presto_speed_text[speed]);
return presto_sendbyte(0xA8 | speed);
}
@@ -704,6 +719,9 @@ int presto_jtag_init(void)
}
INFO("PRESTO open, serial number '%s'", presto->serial);
/* use JTAG speed setting from configuration file */
presto_jtag_speed(jtag_speed);
bitq_interface = &presto_bitq;
return ERROR_OK;
}

391
src/jtag/usbprog.c
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File diff suppressed because it is too large Load Diff

5
src/openocd.c
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@@ -18,7 +18,7 @@
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
#define OPENOCD_VERSION "Open On-Chip Debugger (2007-08-21 18:30 CEST)"
#define OPENOCD_VERSION "Open On-Chip Debugger (2007-08-25 12:00 CEST)"
#ifdef HAVE_CONFIG_H
#include "config.h"
@@ -60,7 +60,8 @@ int handle_version_command(struct command_context_s *cmd_ctx, char *cmd, char **
void exit_handler(void)
{
/* close JTAG interface */
if (jtag && jtag->quit) jtag->quit();
if (jtag && jtag->quit)
jtag->quit();
}
int main(int argc, char *argv[])

173
src/target/embeddedice.c
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@@ -214,7 +214,9 @@ int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
embeddedice_reg_t *ice_reg = reg->arch_info;
u8 reg_addr = ice_reg->addr & 0x1f;
scan_field_t fields[3];
u8 field1_out[1];
u8 field2_out[1];
DEBUG("%i", ice_reg->addr);
jtag_add_end_state(TAP_RTI);
@@ -234,7 +236,7 @@ int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
fields[1].device = ice_reg->jtag_info->chain_pos;
fields[1].num_bits = 5;
fields[1].out_value = malloc(1);
fields[1].out_value = field1_out;
buf_set_u32(fields[1].out_value, 0, 5, reg_addr);
fields[1].out_mask = NULL;
fields[1].in_value = NULL;
@@ -245,7 +247,7 @@ int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
fields[2].device = ice_reg->jtag_info->chain_pos;
fields[2].num_bits = 1;
fields[2].out_value = malloc(1);
fields[2].out_value = field2_out;
buf_set_u32(fields[2].out_value, 0, 1, 0);
fields[2].out_mask = NULL;
fields[2].in_value = NULL;
@@ -268,9 +270,6 @@ int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
jtag_add_dr_scan(3, fields, -1, NULL);
free(fields[1].out_value);
free(fields[2].out_value);
return ERROR_OK;
}
@@ -280,9 +279,10 @@ int embeddedice_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask)
*/
int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size)
{
u8 reg_addr = 0x5;
scan_field_t fields[3];
u8 field1_out[1];
u8 field2_out[1];
jtag_add_end_state(TAP_RTI);
arm_jtag_scann(jtag_info, 0x2);
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
@@ -299,8 +299,8 @@ int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size)
fields[1].device = jtag_info->chain_pos;
fields[1].num_bits = 5;
fields[1].out_value = malloc(1);
buf_set_u32(fields[1].out_value, 0, 5, reg_addr);
fields[1].out_value = field1_out;
buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_DATA]);
fields[1].out_mask = NULL;
fields[1].in_value = NULL;
fields[1].in_check_value = NULL;
@@ -310,7 +310,7 @@ int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size)
fields[2].device = jtag_info->chain_pos;
fields[2].num_bits = 1;
fields[2].out_value = malloc(1);
fields[2].out_value = field2_out;
buf_set_u32(fields[2].out_value, 0, 1, 0);
fields[2].out_mask = NULL;
fields[2].in_value = NULL;
@@ -337,9 +337,6 @@ int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size)
size--;
}
free(fields[1].out_value);
free(fields[2].out_value);
return jtag_execute_queue();
}
@@ -380,7 +377,10 @@ int embeddedice_write_reg(reg_t *reg, u32 value)
embeddedice_reg_t *ice_reg = reg->arch_info;
u8 reg_addr = ice_reg->addr & 0x1f;
scan_field_t fields[3];
u8 field0_out[4];
u8 field1_out[1];
u8 field2_out[1];
DEBUG("%i: 0x%8.8x", ice_reg->addr, value);
jtag_add_end_state(TAP_RTI);
@@ -390,7 +390,7 @@ int embeddedice_write_reg(reg_t *reg, u32 value)
fields[0].device = ice_reg->jtag_info->chain_pos;
fields[0].num_bits = 32;
fields[0].out_value = malloc(4);
fields[0].out_value = field0_out;
buf_set_u32(fields[0].out_value, 0, 32, value);
fields[0].out_mask = NULL;
fields[0].in_value = NULL;
@@ -401,7 +401,7 @@ int embeddedice_write_reg(reg_t *reg, u32 value)
fields[1].device = ice_reg->jtag_info->chain_pos;
fields[1].num_bits = 5;
fields[1].out_value = malloc(1);
fields[1].out_value = field1_out;
buf_set_u32(fields[1].out_value, 0, 5, reg_addr);
fields[1].out_mask = NULL;
fields[1].in_value = NULL;
@@ -412,7 +412,7 @@ int embeddedice_write_reg(reg_t *reg, u32 value)
fields[2].device = ice_reg->jtag_info->chain_pos;
fields[2].num_bits = 1;
fields[2].out_value = malloc(1);
fields[2].out_value = field2_out;
buf_set_u32(fields[2].out_value, 0, 1, 1);
fields[2].out_mask = NULL;
fields[2].in_value = NULL;
@@ -423,10 +423,6 @@ int embeddedice_write_reg(reg_t *reg, u32 value)
jtag_add_dr_scan(3, fields, -1, NULL);
free(fields[0].out_value);
free(fields[1].out_value);
free(fields[2].out_value);
return ERROR_OK;
}
@@ -435,3 +431,136 @@ int embeddedice_store_reg(reg_t *reg)
return embeddedice_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
}
/* send <size> words of 32 bit to the DCC
* we pretend the target is always going to be fast enough
* (relative to the JTAG clock), so we don't need to handshake
*/
int embeddedice_send(arm_jtag_t *jtag_info, u32 *data, u32 size)
{
scan_field_t fields[3];
u8 field0_out[4];
u8 field1_out[1];
u8 field2_out[1];
jtag_add_end_state(TAP_RTI);
arm_jtag_scann(jtag_info, 0x2);
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
fields[0].device = jtag_info->chain_pos;
fields[0].num_bits = 32;
fields[0].out_value = field0_out;
fields[0].out_mask = NULL;
fields[0].in_value = NULL;
fields[0].in_check_value = NULL;
fields[0].in_check_mask = NULL;
fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL;
fields[1].device = jtag_info->chain_pos;
fields[1].num_bits = 5;
fields[1].out_value = field1_out;
buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_DATA]);
fields[1].out_mask = NULL;
fields[1].in_value = NULL;
fields[1].in_check_value = NULL;
fields[1].in_check_mask = NULL;
fields[1].in_handler = NULL;
fields[1].in_handler_priv = NULL;
fields[2].device = jtag_info->chain_pos;
fields[2].num_bits = 1;
fields[2].out_value = field2_out;
buf_set_u32(fields[2].out_value, 0, 1, 1);
fields[2].out_mask = NULL;
fields[2].in_value = NULL;
fields[2].in_check_value = NULL;
fields[2].in_check_mask = NULL;
fields[2].in_handler = NULL;
fields[2].in_handler_priv = NULL;
while (size > 0)
{
buf_set_u32(fields[0].out_value, 0, 32, *data);
jtag_add_dr_scan(3, fields, -1, NULL);
data++;
size--;
}
/* call to jtag_execute_queue() intentionally omitted */
return ERROR_OK;
}
/* wait for DCC control register R/W handshake bit to become active
*/
int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, u32 timeout)
{
scan_field_t fields[3];
u8 field0_in[4];
u8 field1_out[1];
u8 field2_out[1];
int retval;
int hsact;
struct timeval lap;
struct timeval now;
if (hsbit == EICE_COMM_CTRL_WBIT)
hsact = 1;
else if (hsbit != EICE_COMM_CTRL_RBIT)
hsact = 0;
else
return ERROR_INVALID_ARGUMENTS;
jtag_add_end_state(TAP_RTI);
arm_jtag_scann(jtag_info, 0x2);
arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
fields[0].device = jtag_info->chain_pos;
fields[0].num_bits = 32;
fields[0].out_value = NULL;
fields[0].out_mask = NULL;
fields[0].in_value = field0_in;
fields[0].in_check_value = NULL;
fields[0].in_check_mask = NULL;
fields[0].in_handler = NULL;
fields[0].in_handler_priv = NULL;
fields[1].device = jtag_info->chain_pos;
fields[1].num_bits = 5;
fields[1].out_value = field1_out;
buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
fields[1].out_mask = NULL;
fields[1].in_value = NULL;
fields[1].in_check_value = NULL;
fields[1].in_check_mask = NULL;
fields[1].in_handler = NULL;
fields[1].in_handler_priv = NULL;
fields[2].device = jtag_info->chain_pos;
fields[2].num_bits = 1;
fields[2].out_value = field2_out;
buf_set_u32(fields[2].out_value, 0, 1, 0);
fields[2].out_mask = NULL;
fields[2].in_value = NULL;
fields[2].in_check_value = NULL;
fields[2].in_check_mask = NULL;
fields[2].in_handler = NULL;
fields[2].in_handler_priv = NULL;
jtag_add_dr_scan(3, fields, -1, NULL);
gettimeofday(&lap, NULL);
do
{
jtag_add_dr_scan(3, fields, -1, NULL);
if ((retval = jtag_execute_queue()) != ERROR_OK)
return retval;
if (buf_get_u32(field0_in, hsbit, 1) == hsact)
return ERROR_OK;
gettimeofday(&now, NULL);
}
while ((now.tv_sec-lap.tv_sec)*1000 + (now.tv_usec-lap.tv_usec)/1000 <= timeout);
return ERROR_TARGET_TIMEOUT;
}

4
src/target/embeddedice.h
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@@ -1,5 +1,5 @@
/***************************************************************************
* Copyright (C) 2005, 2006 by Dominic Rath *
* Copyright (C) 2005, 2006 by Dominic Rath *
* Dominic.Rath@gmx.de *
* *
* This program is free software; you can redistribute it and/or modify *
@@ -98,5 +98,7 @@ extern int embeddedice_store_reg(reg_t *reg);
extern int embeddedice_set_reg(reg_t *reg, u32 value);
extern int embeddedice_set_reg_w_exec(reg_t *reg, u8 *buf);
extern int embeddedice_receive(arm_jtag_t *jtag_info, u32 *data, u32 size);
extern int embeddedice_send(arm_jtag_t *jtag_info, u32 *data, u32 size);
extern int embeddedice_handshake(arm_jtag_t *jtag_info, int hsbit, u32 timeout);
#endif /* EMBEDDED_ICE_H */

61
src/target/etb.c
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@@ -569,17 +569,66 @@ int etb_read_trace(etm_context_t *etm_ctx)
free(etm_ctx->trace_data);
}
if ((etm_ctx->portmode & ETM_PORT_MODE_MASK) == ETM_PORT_DEMUXED)
if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_4BIT)
etm_ctx->trace_depth = num_frames * 3;
else if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
etm_ctx->trace_depth = num_frames * 2;
else
etm_ctx->trace_depth = num_frames;
etm_ctx->trace_data= malloc(sizeof(etmv1_trace_data_t) * etm_ctx->trace_depth);
etm_ctx->trace_data = malloc(sizeof(etmv1_trace_data_t) * etm_ctx->trace_depth);
for (i = 0, j = 0; i < num_frames; i++)
{
if ((etm_ctx->portmode & ETM_PORT_MODE_MASK) == ETM_PORT_DEMUXED)
if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_4BIT)
{
/* trace word j */
etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
etm_ctx->trace_data[j].packet = (trace_data[i] & 0x78) >> 3;
etm_ctx->trace_data[j].flags = 0;
if ((trace_data[i] & 0x80) >> 7)
{
etm_ctx->trace_data[j].flags |= ETMV1_TRACESYNC_CYCLE;
}
if (etm_ctx->trace_data[j].pipestat == STAT_TR)
{
etm_ctx->trace_data[j].pipestat = etm_ctx->trace_data[j].packet & 0x7;
etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
}
/* trace word j+1 */
etm_ctx->trace_data[j+1].pipestat = (trace_data[i] & 0x100) >> 8;
etm_ctx->trace_data[j+1].packet = (trace_data[i] & 0x7800) >> 11;
etm_ctx->trace_data[j+1].flags = 0;
if ((trace_data[i] & 0x8000) >> 15)
{
etm_ctx->trace_data[j+1].flags |= ETMV1_TRACESYNC_CYCLE;
}
if (etm_ctx->trace_data[j+1].pipestat == STAT_TR)
{
etm_ctx->trace_data[j+1].pipestat = etm_ctx->trace_data[j+1].packet & 0x7;
etm_ctx->trace_data[j+1].flags |= ETMV1_TRIGGER_CYCLE;
}
/* trace word j+2 */
etm_ctx->trace_data[j+2].pipestat = (trace_data[i] & 0x10000) >> 16;
etm_ctx->trace_data[j+2].packet = (trace_data[i] & 0x780000) >> 19;
etm_ctx->trace_data[j+2].flags = 0;
if ((trace_data[i] & 0x800000) >> 23)
{
etm_ctx->trace_data[j+2].flags |= ETMV1_TRACESYNC_CYCLE;
}
if (etm_ctx->trace_data[j+2].pipestat == STAT_TR)
{
etm_ctx->trace_data[j+2].pipestat = etm_ctx->trace_data[j+2].packet & 0x7;
etm_ctx->trace_data[j+2].flags |= ETMV1_TRIGGER_CYCLE;
}
j += 3;
}
else if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
{
/* trace word j */
etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
etm_ctx->trace_data[j].packet = (trace_data[i] & 0x7f8) >> 3;
etm_ctx->trace_data[j].flags = 0;
@@ -593,6 +642,7 @@ int etb_read_trace(etm_context_t *etm_ctx)
etm_ctx->trace_data[j].flags |= ETMV1_TRIGGER_CYCLE;
}
/* trace word j+1 */
etm_ctx->trace_data[j+1].pipestat = (trace_data[i] & 0x7000) >> 12;
etm_ctx->trace_data[j+1].packet = (trace_data[i] & 0x7f8000) >> 15;
etm_ctx->trace_data[j+1].flags = 0;
@@ -610,6 +660,7 @@ int etb_read_trace(etm_context_t *etm_ctx)
}
else
{
/* trace word j */
etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
etm_ctx->trace_data[j].packet = (trace_data[i] & 0x7fff8) >> 3;
etm_ctx->trace_data[j].flags = 0;
@@ -640,9 +691,9 @@ int etb_start_capture(etm_context_t *etm_ctx)
if ((etm_ctx->portmode & ETM_PORT_MODE_MASK) == ETM_PORT_DEMUXED)
{
if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_16BIT)
if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) != ETM_PORT_8BIT)
{
DEBUG("ETB can't run in demultiplexed mode with a 16-bit port");
ERROR("ETB can't run in demultiplexed mode with a 4 or 16 bit port");
return ERROR_ETM_PORTMODE_NOT_SUPPORTED;
}
etb_ctrl_value |= 0x2;