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target: add Espressif ESP32 basic support

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ESP32 is a dual core Xtensa SoC
Not full featured yet. Some of the missing functionality:
-Semihosting
-Flash breakpoints
-Flash loader
-Apptrace
-FreeRTOS

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I76fb184aa38ab9f4e30290c038b5ff8850060750
Reviewed-on: https://review.openocd.org/c/openocd/+/6989
Tested-by: jenkins
Reviewed-by: Ian Thompson <ianst@cadence.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Erhan Kurubas
2022-05-21 23:49:54 +02:00
committed by Antonio Borneo
parent 52fbb85d2e
commit 77287b8d47
18 changed files with 1950 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

51
contrib/loaders/reset/espressif/common.mk Normal file
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@@ -0,0 +1,51 @@
# ESP32 Makefile to compile the SoC reset program
# Copyright (C) 2022 Espressif Systems Ltd.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>
# Pass V=1 to see the commands being executed by make
ifneq ("$(V)","1")
Q = @
endif
BIN2C = ../../../../../src/helper/bin2char.sh
APP = cpu_reset_handler
BUILD_DIR = build
APP_OBJ = $(BUILD_DIR)/$(APP).o
APP_BIN = $(BUILD_DIR)/$(APP)_code.bin
APP_CODE = $(APP)_code.inc
CFLAGS += -mtext-section-literals
.PHONY: all cleanxten
all: $(BUILD_DIR) $(APP_OBJ) $(APP_CODE)
$(BUILD_DIR):
$(Q) mkdir $@
$(APP_OBJ): $(SRCS)
@echo " CC $^ -> $@"
$(Q) $(CROSS)gcc -c $(CFLAGS) -o $@ $^
$(APP_CODE): $(APP_OBJ)
@echo " CC $^ -> $@"
$(Q) $(CROSS)objcopy -O binary -j.text $^ $(APP_BIN)
$(Q) $(BIN2C) < $(APP_BIN) > $@
clean:
$(Q) rm -rf $(BUILD_DIR)

31
contrib/loaders/reset/espressif/esp32/Makefile Normal file
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@@ -0,0 +1,31 @@
# ESP32 Makefile to compile the SoC reset program
# Copyright (C) 2022 Espressif Systems Ltd.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>
# Prefix for ESP32 cross compilers (can include a directory path)
CROSS ?= xtensa-esp32-elf-
APP_ARCH := xtensa
APP_CHIP := ESP32
APP_CHIP_PATH := $(shell pwd)
SRCS := $(APP_CHIP_PATH)/esp32_cpu_reset_handler.S
CFLAGS :=
LDFLAGS :=
INCLUDES :=
DEFINES :=
include ../common.mk

15
contrib/loaders/reset/espressif/esp32/cpu_reset_handler_code.inc Normal file
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@@ -0,0 +1,15 @@
/* Autogenerated with ../../../../../src/helper/bin2char.sh */
0x06,0x1e,0x00,0x00,0x06,0x14,0x00,0x00,0x34,0x80,0xf4,0x3f,0xb0,0x80,0xf4,0x3f,
0xb4,0x80,0xf4,0x3f,0x70,0x80,0xf4,0x3f,0x10,0x22,0x00,0x00,0x00,0x20,0x49,0x9c,
0x00,0x80,0xf4,0x3f,0xa1,0x3a,0xd8,0x50,0xa4,0x80,0xf4,0x3f,0x64,0xf0,0xf5,0x3f,
0x64,0x00,0xf6,0x3f,0x8c,0x80,0xf4,0x3f,0x48,0xf0,0xf5,0x3f,0x48,0x00,0xf6,0x3f,
0xfc,0xa1,0xf5,0x3f,0x38,0x00,0xf0,0x3f,0x30,0x00,0xf0,0x3f,0x2c,0x00,0xf0,0x3f,
0x34,0x80,0xf4,0x3f,0x00,0x30,0x00,0x00,0x50,0x55,0x30,0x41,0xeb,0xff,0x59,0x04,
0x41,0xeb,0xff,0x59,0x04,0x41,0xea,0xff,0x59,0x04,0x41,0xea,0xff,0x31,0xea,0xff,
0x39,0x04,0x31,0xea,0xff,0x41,0xea,0xff,0x39,0x04,0x00,0x00,0x60,0xeb,0x03,0x60,
0x61,0x04,0x56,0x66,0x04,0x50,0x55,0x30,0x31,0xe7,0xff,0x41,0xe7,0xff,0x39,0x04,
0x41,0xe7,0xff,0x39,0x04,0x41,0xe6,0xff,0x39,0x04,0x41,0xe6,0xff,0x59,0x04,0x41,
0xe6,0xff,0x59,0x04,0x41,0xe6,0xff,0x59,0x04,0x41,0xe5,0xff,0x59,0x04,0x41,0xe5,
0xff,0x59,0x04,0x41,0xe5,0xff,0x0c,0x13,0x39,0x04,0x41,0xe4,0xff,0x0c,0x13,0x39,
0x04,0x59,0x04,0x41,0xe3,0xff,0x31,0xe3,0xff,0x32,0x64,0x00,0x00,0x70,0x00,0x46,
0xfe,0xff,

145
contrib/loaders/reset/espressif/esp32/esp32_cpu_reset_handler.S Normal file
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@@ -0,0 +1,145 @@
/***************************************************************************
* Reset stub used by esp32 target *
* Copyright (C) 2017 Espressif Systems Ltd. *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
#define RTC_CNTL_RESET_STATE_REG 0x3ff48034
#define RTC_CNTL_RESET_STATE_DEF 0x3000
#define RTC_CNTL_CLK_CONF_REG 0x3ff48070
#define RTC_CNTL_CLK_CONF_DEF 0x2210
#define RTC_CNTL_STORE4_REG 0x3ff480b0
#define RTC_CNTL_STORE5_REG 0x3ff480b4
#define WDT_WKEY_VALUE 0x50D83AA1
#define TIMG0_WDTWPROTECT_REG 0x3ff5f064
#define TIMG0_WDTCONFIG0_REG 0x3ff5f048
#define TIMG1_WDTWPROTECT_REG 0x3FF60064
#define TIMG1_WDTCONFIG0_REG 0x3ff60048
#define RTC_CNTL_WDTCONFIG0_REG 0x3ff4808c
#define RTC_CNTL_WDTWPROTECT_REG 0x3ff480a4
#define JTAG_ENABLE_REG 0x3ff5a1fc
#define RTC_CNTL_OPTIONS0_REG 0x3ff48000
#define RTC_CNTL_OPTIONS0_DEF 0x1c492000
#define RTC_CNTL_SW_SYS_RST 0x80000000
#define DPORT_APPCPU_CTRL_A_REG 0x3ff0002c
#define DPORT_APPCPU_RST_EN 0x1
#define DPORT_APPCPU_CTRL_B_REG 0x3ff00030
#define DPORT_APPCPU_CLKGATE_EN 0x1
#define DPORT_APPCPU_CTRL_C_REG 0x3ff00034
#define DPORT_APPCPU_CTRL_D_REG 0x3ff00038
/* This stub is copied to RTC_SLOW_MEM by OpenOCD, and the CPU starts executing
* it instead of the ROM code (0x40000400). This stub disables watchdogs and
* goes into a loop.
* OpenOCD will then halt the target and perform CPU reset using OCD.
*/
/* Has to be at offset 0. This is the entry point of the CPU, once
* RTC_CNTL_PROCPU_STAT_VECTOR_SEL is cleared.
* CPU will come here after the system reset, triggered by RTC_CNTL_SW_SYS_RST.
*/
.global cpu_at_start_handler
.type cpu_at_start_handler,@function
.align 4
cpu_at_start_handler:
j start
/* Has to be at offset 4. Once the stub code has been uploaded into RTC Slow
* memory, OpenOCD will set the PC to this address, and resume execution.
* The stub will then jump to 'reset' label and perform the reset.
*/
.global cpu_reset_handler
.type cpu_reset_handler,@function
.align 4
cpu_reset_handler:
j reset
.align 4
.literal_position
.align 4
reset:
/* Use a5 as a zero register */
xor a5, a5, a5
/* Select static reset vector 0 (XCHAL_RESET_VECTOR0_VADDR, 0x50000000) */
movi a4, RTC_CNTL_RESET_STATE_REG
s32i a5, a4, 0
/* Set some clock-related RTC registers to the default values */
movi a4, RTC_CNTL_STORE4_REG
s32i a5, a4, 0
movi a4, RTC_CNTL_STORE5_REG
s32i a5, a4, 0
movi a4, RTC_CNTL_CLK_CONF_REG
movi a3, RTC_CNTL_CLK_CONF_DEF
s32i a3, a4, 0
/* Reset the digital part of the chip (RTC controller doesn't get reset) */
movi a3, (RTC_CNTL_OPTIONS0_DEF | RTC_CNTL_SW_SYS_RST)
movi a4, RTC_CNTL_OPTIONS0_REG
s32i a3, a4, 0
/* Doesn't reach beyond this instruction */
.align 4
start:
/* If running on the APP CPU, skip directly to the parking loop */
rsr.prid a6
extui a6, a6, 1, 1
bnez a6, parking_loop
/* Use a5 as a zero register */
xor a5, a5, a5
/* Disable the watchdogs */
movi a3, WDT_WKEY_VALUE
movi a4, RTC_CNTL_WDTWPROTECT_REG
s32i.n a3, a4, 0
movi a4, TIMG0_WDTWPROTECT_REG
s32i.n a3, a4, 0
movi a4, TIMG1_WDTWPROTECT_REG
s32i.n a3, a4, 0
movi a4, RTC_CNTL_WDTCONFIG0_REG
s32i.n a5, a4, 0
movi a4, TIMG0_WDTCONFIG0_REG
s32i.n a5, a4, 0
movi a4, TIMG1_WDTCONFIG0_REG
s32i.n a5, a4, 0
/* Enable JTAG (needed since rev. 3) */
movi a4, JTAG_ENABLE_REG
s32i.n a5, a4, 0
/* Clear APP_CPU boot address */
movi a4, DPORT_APPCPU_CTRL_D_REG
s32i.n a5, a4, 0
/* Clear APP_CPU clock gating */
movi a4, DPORT_APPCPU_CTRL_B_REG
movi a3, DPORT_APPCPU_CLKGATE_EN
s32i.n a3, a4, 0
/* Set and clear APP_CPU reset */
movi a4, DPORT_APPCPU_CTRL_A_REG
movi a3, DPORT_APPCPU_RST_EN
s32i.n a3, a4, 0
s32i.n a5, a4, 0
/* Restore the reset vector to ROM */
movi a4, RTC_CNTL_RESET_STATE_REG
movi a3, RTC_CNTL_RESET_STATE_DEF
s32i.n a3, a4, 0
parking_loop:
/* PRO and APP CPU will be in this loop, until OpenOCD
* finds the JTAG taps and puts the CPUs into debug mode.
*/
waiti 0
j parking_loop

1
doc/openocd.texi
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@@ -4913,6 +4913,7 @@ compact Thumb2 instruction set. Supports also ARMv6-M and ARMv8-M cores
@item @code{dsp5680xx} -- implements Freescale's 5680x DSP.
@item @code{esirisc} -- this is an EnSilica eSi-RISC core.
The current implementation supports eSi-32xx cores.
@item @code{esp32} -- this is an Espressif SoC with dual Xtensa cores.
@item @code{esp32s2} -- this is an Espressif SoC with single Xtensa core.
@item @code{fa526} -- resembles arm920 (w/o Thumb).
@item @code{feroceon} -- resembles arm926.

6
src/target/espressif/Makefile.am
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@@ -2,5 +2,9 @@ noinst_LTLIBRARIES += %D%/libespressif.la
%C%_libespressif_la_SOURCES = \
%D%/esp_xtensa.c \
%D%/esp_xtensa.h \
%D%/esp_xtensa_smp.c \
%D%/esp_xtensa_smp.h \
%D%/esp32s2.c \
%D%/esp32s2.h
%D%/esp32s2.h \
%D%/esp32.c \
%D%/esp32.h

704
src/target/espressif/esp32.c Normal file
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File diff suppressed because it is too large Load Diff

42
src/target/espressif/esp32.h Normal file
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@@ -0,0 +1,42 @@
/***************************************************************************
* ESP32 target for OpenOCD *
* Copyright (C) 2017 Espressif Systems Ltd. *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
#ifndef OPENOCD_TARGET_ESP32_H
#define OPENOCD_TARGET_ESP32_H
#include <target/xtensa/xtensa_regs.h>
#define ESP32_DROM_LOW 0x3F400000
#define ESP32_DROM_HIGH 0x3F800000
#define ESP32_IROM_LOW 0x400D0000
#define ESP32_IROM_HIGH 0x40400000
/* Number of registers returned directly by the G command
* Corresponds to the amount of regs listed in regformats/reg-xtensa.dat in the gdb source */
#define ESP32_NUM_REGS_G_COMMAND 105
enum esp32_reg_id {
/* chip specific registers that extend ISA go after ISA-defined ones */
ESP32_REG_IDX_EXPSTATE = XT_USR_REG_START,
ESP32_REG_IDX_F64R_LO,
ESP32_REG_IDX_F64R_HI,
ESP32_REG_IDX_F64S,
ESP32_NUM_REGS,
};
#endif /* OPENOCD_TARGET_ESP32_H */

2
src/target/espressif/esp32s2.c
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@@ -474,7 +474,7 @@ static int esp32s2_soc_reset(struct target *target)
res = esp32s2_set_peri_reg_mask(target,
ESP32_S2_OPTIONS0,
ESP32_S2_SW_SYS_RST_M,
1U << ESP32_S2_SW_SYS_RST_S);
BIT(ESP32_S2_SW_SYS_RST_S));
xtensa->suppress_dsr_errors = false;
if (res != ERROR_OK) {
LOG_ERROR("Failed to write ESP32_S2_OPTIONS0 (%d)!", res);

716
src/target/espressif/esp_xtensa_smp.c Normal file
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File diff suppressed because it is too large Load Diff

65
src/target/espressif/esp_xtensa_smp.h Normal file
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@@ -0,0 +1,65 @@
/***************************************************************************
* ESP Xtensa SMP target for OpenOCD *
* Copyright (C) 2020 Espressif Systems Ltd. Co *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
#ifndef OPENOCD_TARGET_XTENSA_ESP_SMP_H
#define OPENOCD_TARGET_XTENSA_ESP_SMP_H
#include "esp_xtensa.h"
struct esp_xtensa_smp_chip_ops {
int (*poll)(struct target *target);
int (*reset)(struct target *target);
int (*on_halt)(struct target *target);
};
struct esp_xtensa_smp_common {
struct esp_xtensa_common esp_xtensa;
const struct esp_xtensa_smp_chip_ops *chip_ops;
bool other_core_does_resume;
/* number of attempts to examine other SMP cores, attempts are made after reset on target poll */
int examine_other_cores;
};
int esp_xtensa_smp_poll(struct target *target);
int esp_xtensa_smp_resume(struct target *target,
int current,
target_addr_t address,
int handle_breakpoints,
int debug_execution);
int esp_xtensa_smp_step(struct target *target,
int current,
target_addr_t address,
int handle_breakpoints);
int esp_xtensa_smp_assert_reset(struct target *target);
int esp_xtensa_smp_deassert_reset(struct target *target);
int esp_xtensa_smp_soft_reset_halt(struct target *target);
int esp_xtensa_smp_watchpoint_add(struct target *target, struct watchpoint *watchpoint);
int esp_xtensa_smp_watchpoint_remove(struct target *target, struct watchpoint *watchpoint);
int esp_xtensa_smp_handle_target_event(struct target *target, enum target_event event, void *priv);
int esp_xtensa_smp_target_init(struct command_context *cmd_ctx, struct target *target);
int esp_xtensa_smp_init_arch_info(struct target *target,
struct esp_xtensa_smp_common *esp_xtensa_smp,
const struct xtensa_config *xtensa_cfg,
struct xtensa_debug_module_config *dm_cfg,
const struct esp_xtensa_smp_chip_ops *chip_ops);
extern const struct command_registration esp_xtensa_smp_command_handlers[];
extern const struct command_registration esp_xtensa_smp_xtensa_command_handlers[];
extern const struct command_registration esp_xtensa_smp_esp_command_handlers[];
#endif /* OPENOCD_TARGET_XTENSA_ESP_SMP_H */

4
src/target/target.c
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@@ -105,6 +105,7 @@ extern struct target_type hla_target;
extern struct target_type nds32_v2_target;
extern struct target_type nds32_v3_target;
extern struct target_type nds32_v3m_target;
extern struct target_type esp32_target;
extern struct target_type esp32s2_target;
extern struct target_type or1k_target;
extern struct target_type quark_x10xx_target;
@@ -142,6 +143,7 @@ static struct target_type *target_types[] = {
&nds32_v2_target,
&nds32_v3_target,
&nds32_v3m_target,
&esp32_target,
&esp32s2_target,
&or1k_target,
&quark_x10xx_target,
@@ -3336,7 +3338,7 @@ COMMAND_HANDLER(handle_soft_reset_halt_command)
{
struct target *target = get_current_target(CMD_CTX);
LOG_USER("requesting target halt and executing a soft reset");
LOG_TARGET_INFO(target, "requesting target halt and executing a soft reset");
target_soft_reset_halt(target);

10
src/target/xtensa/xtensa.h
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@@ -302,6 +302,16 @@ int xtensa_fetch_user_regs_u32(struct target *target);
int xtensa_queue_write_dirty_user_regs_u32(struct target *target);
const char *xtensa_get_gdb_arch(struct target *target);
COMMAND_HELPER(xtensa_cmd_permissive_mode_do, struct xtensa *xtensa);
COMMAND_HELPER(xtensa_cmd_mask_interrupts_do, struct xtensa *xtensa);
COMMAND_HELPER(xtensa_cmd_smpbreak_do, struct target *target);
COMMAND_HELPER(xtensa_cmd_perfmon_dump_do, struct xtensa *xtensa);
COMMAND_HELPER(xtensa_cmd_perfmon_enable_do, struct xtensa *xtensa);
COMMAND_HELPER(xtensa_cmd_tracestart_do, struct xtensa *xtensa);
COMMAND_HELPER(xtensa_cmd_tracestop_do, struct xtensa *xtensa);
COMMAND_HELPER(xtensa_cmd_tracedump_do, struct xtensa *xtensa, const char *fname);
extern const struct reg_arch_type xtensa_user_reg_u32_type;
extern const struct reg_arch_type xtensa_user_reg_u128_type;
extern const struct command_registration xtensa_command_handlers[];

22
tcl/board/esp32-ethernet-kit-3.3v.cfg Normal file
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@@ -0,0 +1,22 @@
# SPDX-License-Identifier: GPL-2.0-or-later
#
# Example OpenOCD configuration file for ESP32-ETHERNET-KIT board.
#
# For example, OpenOCD can be started for ESP32 debugging on
#
# openocd -f board/esp32-ethernet-kit-3.3v.cfg
#
# Source the JTAG interface configuration file
source [find interface/ftdi/esp32_devkitj_v1.cfg]
set ESP32_FLASH_VOLTAGE 3.3
# Source the ESP32 configuration file
source [find target/esp32.cfg]
# The speed of the JTAG interface, in kHz. If you get DSR/DIR errors (and they
# do not relate to OpenOCD trying to read from a memory range without physical
# memory being present there), you can try lowering this.
#
# On DevKit-J, this can go as high as 20MHz if CPU frequency is 80MHz, or 26MHz
# if CPU frequency is 160MHz or 240MHz.
adapter speed 20000

22
tcl/board/esp32-wrover-kit-1.8v.cfg Normal file
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@@ -0,0 +1,22 @@
# SPDX-License-Identifier: GPL-2.0-or-later
#
# Example OpenOCD configuration file for ESP32-WROVER-KIT board.
#
# For example, OpenOCD can be started for ESP32 debugging on
#
# openocd -f board/esp32-wrover-kit-1.8v.cfg
#
# Source the JTAG interface configuration file
source [find interface/ftdi/esp32_devkitj_v1.cfg]
set ESP32_FLASH_VOLTAGE 1.8
# Source the ESP32 configuration file
source [find target/esp32.cfg]
# The speed of the JTAG interface, in kHz. If you get DSR/DIR errors (and they
# do not relate to OpenOCD trying to read from a memory range without physical
# memory being present there), you can try lowering this.
#
# On DevKit-J, this can go as high as 20MHz if CPU frequency is 80MHz, or 26MHz
# if CPU frequency is 160MHz or 240MHz.
adapter speed 20000

22
tcl/board/esp32-wrover-kit-3.3v.cfg Normal file
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@@ -0,0 +1,22 @@
# SPDX-License-Identifier: GPL-2.0-or-later
#
# Example OpenOCD configuration file for ESP32-WROVER-KIT board.
#
# For example, OpenOCD can be started for ESP32 debugging on
#
# openocd -f board/esp32-wrover-kit-3.3v.cfg
#
# Source the JTAG interface configuration file
source [find interface/ftdi/esp32_devkitj_v1.cfg]
set ESP32_FLASH_VOLTAGE 3.3
# Source the ESP32 configuration file
source [find target/esp32.cfg]
# The speed of the JTAG interface, in kHz. If you get DSR/DIR errors (and they
# do not relate to OpenOCD trying to read from a memory range without physical
# memory being present there), you can try lowering this.
#
# On DevKit-J, this can go as high as 20MHz if CPU frequency is 80MHz, or 26MHz
# if CPU frequency is 160MHz or 240MHz.
adapter speed 20000

25
tcl/interface/ftdi/esp32_devkitj_v1.cfg Normal file
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@@ -0,0 +1,25 @@
# SPDX-License-Identifier: GPL-2.0-or-later
#
# Driver for the FT2232H JTAG chip on the Espressif DevkitJ board
# (and most other FT2232H and FT232H based boards)
#
adapter driver ftdi
ftdi vid_pid 0x0403 0x6010 0x0403 0x6014
# interface 1 is the uart
ftdi channel 0
# TCK, TDI, TDO, TMS: ADBUS0-3
# LEDs: ACBUS4-7
ftdi layout_init 0x0008 0xf00b
ftdi layout_signal LED -data 0x1000
ftdi layout_signal LED2 -data 0x2000
ftdi layout_signal LED3 -data 0x4000
ftdi layout_signal LED4 -data 0x8000
# ESP32 series chips do not have a TRST input, and the SRST line is connected to the EN pin.
# The target code doesn't handle SRST reset properly yet, so this is commented out:
# ftdi_layout_signal nSRST -oe 0x0020
# reset_config srst_only

70
tcl/target/esp32.cfg Normal file
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# SPDX-License-Identifier: GPL-2.0-or-later
#
# The ESP32 only supports JTAG.
transport select jtag
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME esp32
}
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
set _CPUTAPID 0x120034e5
}
if { [info exists ESP32_ONLYCPU] } {
set _ONLYCPU $ESP32_ONLYCPU
} else {
set _ONLYCPU 2
}
if { [info exists ESP32_FLASH_VOLTAGE] } {
set _FLASH_VOLTAGE $ESP32_FLASH_VOLTAGE
} else {
set _FLASH_VOLTAGE 3.3
}
set _CPU0NAME cpu0
set _CPU1NAME cpu1
set _TARGETNAME_0 $_CHIPNAME.$_CPU0NAME
set _TARGETNAME_1 $_CHIPNAME.$_CPU1NAME
jtag newtap $_CHIPNAME $_CPU0NAME -irlen 5 -expected-id $_CPUTAPID
if { $_ONLYCPU != 1 } {
jtag newtap $_CHIPNAME $_CPU1NAME -irlen 5 -expected-id $_CPUTAPID
} else {
jtag newtap $_CHIPNAME $_CPU1NAME -irlen 5 -disable -expected-id $_CPUTAPID
}
# PRO-CPU
target create $_TARGETNAME_0 $_CHIPNAME -endian little -chain-position $_TARGETNAME_0 -coreid 0
# APP-CPU
if { $_ONLYCPU != 1 } {
target create $_TARGETNAME_1 $_CHIPNAME -endian little -chain-position $_TARGETNAME_1 -coreid 1
target smp $_TARGETNAME_0 $_TARGETNAME_1
}
$_TARGETNAME_0 esp32 flashbootstrap $_FLASH_VOLTAGE
$_TARGETNAME_0 xtensa maskisr on
$_TARGETNAME_0 xtensa smpbreak BreakIn BreakOut
$_TARGETNAME_0 configure -event reset-assert-post { soft_reset_halt }
$_TARGETNAME_0 configure -event gdb-attach {
$_TARGETNAME_0 xtensa smpbreak BreakIn BreakOut
# necessary to auto-probe flash bank when GDB is connected
halt 1000
}
if { $_ONLYCPU != 1 } {
$_TARGETNAME_1 configure -event gdb-attach {
$_TARGETNAME_1 xtensa smpbreak BreakIn BreakOut
# necessary to auto-probe flash bank when GDB is connected
halt 1000
}
$_TARGETNAME_1 configure -event reset-assert-post { soft_reset_halt }
}
gdb_breakpoint_override hard