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mips: Add MIPS64 support
The patch adds support for processors implementing MIPS64 instruction set. Change-Id: I79a983dfdead81553457a0f3e9e739a9785afaac Signed-off-by: Konstantin Kostyukhin <kost@niisi.msk.ru> Signed-off-by: Andrey Sidorov <anysidorov@gmail.com> Signed-off-by: Aleksey Kuleshov <rndfax@yandex.ru> Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Signed-off-by: Peter Mamonov <pmamonov@gmail.com> Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> CC: Dongxue Zhang <elta.era@gmail.com> CC: Paul Fertser <fercerpav@gmail.com> CC: Salvador Arroyo <sarroyofdez@yahoo.es> CC: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/2321 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
This commit is contained in:
Peter Mamonov
committed by
Paul Fertser
Paul Fertser
parent
20a310deb7
commit
1fbe8450a9
@@ -32,6 +32,7 @@ noinst_LTLIBRARIES += %D%/libtarget.la
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if TARGET64
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%C%_libtarget_la_SOURCES +=$(ARMV8_SRC)
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%C%_libtarget_la_SOURCES +=$(MIPS64_SRC)
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endif
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TARGET_CORE_SRC = \
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@@ -120,6 +121,13 @@ MIPS32_SRC = \
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%D%/mips32_dmaacc.c \
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%D%/mips_ejtag.c
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MIPS64_SRC = \
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%D%/mips64.c \
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%D%/mips32_pracc.c \
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%D%/mips64_pracc.c \
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%D%/trace.c \
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%D%/mips_ejtag.c
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NDS32_SRC = \
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%D%/nds32.c \
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%D%/nds32_reg.c \
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@@ -193,10 +201,12 @@ ESIRISC_SRC = \
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%D%/etm_dummy.h \
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%D%/image.h \
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%D%/mips32.h \
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%D%/mips64.h \
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%D%/mips_m4k.h \
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%D%/mips_ejtag.h \
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%D%/mips32_pracc.h \
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%D%/mips32_dmaacc.h \
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%D%/mips64_pracc.h \
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%D%/oocd_trace.h \
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%D%/register.h \
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%D%/target.h \
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627
src/target/mips64.c
Normal file
627
src/target/mips64.c
Normal file
File diff suppressed because it is too large
Load Diff
226
src/target/mips64.h
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226
src/target/mips64.h
Normal file
@@ -0,0 +1,226 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Support for processors implementing MIPS64 instruction set
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*
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* Copyright (C) 2014 by Andrey Sidorov <anysidorov@gmail.com>
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* Copyright (C) 2014 by Aleksey Kuleshov <rndfax@yandex.ru>
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* Copyright (C) 2014-2019 by Peter Mamonov <pmamonov@gmail.com>
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*
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* Based on the work of:
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* Copyright (C) 2008 by Spencer Oliver
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* Copyright (C) 2008 by David T.L. Wong
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* Copyright (C) 2010 by Konstantin Kostyukhin, Nikolay Shmyrev
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*/
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#ifndef OPENOCD_TARGET_MIPS64_H
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#define OPENOCD_TARGET_MIPS64_H
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#include "target.h"
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#include "register.h"
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#include "mips64_pracc.h"
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#define MIPS64_COMMON_MAGIC 0xB640B640
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/* MIPS64 CP0 registers */
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#define MIPS64_C0_INDEX 0
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#define MIPS64_C0_RANDOM 1
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#define MIPS64_C0_ENTRYLO0 2
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#define MIPS64_C0_ENTRYLO1 3
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#define MIPS64_C0_CONTEXT 4
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#define MIPS64_C0_PAGEMASK 5
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#define MIPS64_C0_WIRED 6
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#define MIPS64_C0_BADVADDR 8
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#define MIPS64_C0_COUNT 9
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#define MIPS64_C0_ENTRYHI 10
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#define MIPS64_C0_COMPARE 11
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#define MIPS64_C0_STATUS 12
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#define MIPS64_C0_CAUSE 13
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#define MIPS64_C0_EPC 14
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#define MIPS64_C0_PRID 15
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#define MIPS64_C0_CONFIG 16
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#define MIPS64_C0_LLA 17
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#define MIPS64_C0_WATCHLO 18
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#define MIPS64_C0_WATCHHI 19
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#define MIPS64_C0_XCONTEXT 20
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#define MIPS64_C0_MEMCTRL 22
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#define MIPS64_C0_DEBUG 23
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#define MIPS64_C0_DEPC 24
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#define MIPS64_C0_PERFCOUNT 25
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#define MIPS64_C0_ECC 26
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#define MIPS64_C0_CACHERR 27
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#define MIPS64_C0_TAGLO 28
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#define MIPS64_C0_TAGHI 29
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#define MIPS64_C0_DATAHI 29
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#define MIPS64_C0_EEPC 30
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/* MIPS64 CP1 registers */
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#define MIPS64_C1_FIR 0
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#define MIPS64_C1_FCONFIG 24
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#define MIPS64_C1_FCSR 31
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#define MIPS64_C1_FCCR 25
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#define MIPS64_C1_FEXR 26
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#define MIPS64_C1_FENR 28
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/* offsets into mips64 register cache */
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#define MIPS64_NUM_CORE_REGS 34
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#define MIPS64_NUM_C0_REGS 34
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#define MIPS64_NUM_FP_REGS 38
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#define MIPS64_NUM_REGS (MIPS64_NUM_CORE_REGS + \
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MIPS64_NUM_C0_REGS + \
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MIPS64_NUM_FP_REGS)
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#define MIPS64_NUM_CORE_C0_REGS (MIPS64_NUM_CORE_REGS + MIPS64_NUM_C0_REGS)
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#define MIPS64_PC MIPS64_NUM_CORE_REGS
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struct mips64_comparator {
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bool used;
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uint64_t bp_value;
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uint64_t reg_address;
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};
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struct mips64_common {
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uint32_t common_magic;
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void *arch_info;
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struct reg_cache *core_cache;
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struct mips_ejtag ejtag_info;
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uint64_t core_regs[MIPS64_NUM_REGS];
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struct working_area *fast_data_area;
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bool bp_scanned;
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int num_inst_bpoints;
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int num_data_bpoints;
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int num_inst_bpoints_avail;
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int num_data_bpoints_avail;
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struct mips64_comparator *inst_break_list;
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struct mips64_comparator *data_break_list;
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/* register cache to processor synchronization */
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int (*read_core_reg)(struct target *target, int num);
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int (*write_core_reg)(struct target *target, int num);
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bool mips64mode32;
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};
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struct mips64_core_reg {
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uint32_t num;
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struct target *target;
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struct mips64_common *mips64_common;
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uint8_t value[8];
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struct reg_feature feature;
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struct reg_data_type reg_data_type;
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};
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#define MIPS64_OP_SRL 0x02
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#define MIPS64_OP_BEQ 0x04
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#define MIPS64_OP_BNE 0x05
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#define MIPS64_OP_ADDI 0x08
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#define MIPS64_OP_ANDI 0x0c
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#define MIPS64_OP_DADDI 0x18
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#define MIPS64_OP_DADDIU 0x19
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#define MIPS64_OP_AND 0x24
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#define MIPS64_OP_LUI 0x0F
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#define MIPS64_OP_LW 0x23
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#define MIPS64_OP_LD 0x37
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#define MIPS64_OP_LBU 0x24
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#define MIPS64_OP_LHU 0x25
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#define MIPS64_OP_MFHI 0x10
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#define MIPS64_OP_MTHI 0x11
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#define MIPS64_OP_MFLO 0x12
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#define MIPS64_OP_MTLO 0x13
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#define MIPS64_OP_SB 0x28
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#define MIPS64_OP_SH 0x29
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#define MIPS64_OP_SW 0x2B
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#define MIPS64_OP_SD 0x3F
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#define MIPS64_OP_ORI 0x0D
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#define MIPS64_OP_JR 0x08
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#define MIPS64_OP_COP0 0x10
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#define MIPS64_OP_COP1 0x11
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#define MIPS64_OP_COP2 0x12
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#define MIPS64_COP_MF 0x00
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#define MIPS64_COP_DMF 0x01
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#define MIPS64_COP_MT 0x04
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#define MIPS64_COP_DMT 0x05
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#define MIPS64_COP_CF 0x02
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#define MIPS64_COP_CT 0x06
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#define MIPS64_R_INST(opcode, rs, rt, rd, shamt, funct) \
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(((opcode) << 26) | ((rs) << 21) | ((rt) << 16) | ((rd) << 11) | ((shamt) << 6) | (funct))
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#define MIPS64_I_INST(opcode, rs, rt, immd) (((opcode) << 26) | ((rs) << 21) | ((rt) << 16) | (immd))
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#define MIPS64_J_INST(opcode, addr) (((opcode) << 26) | (addr))
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#define MIPS64_NOP 0
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#define MIPS64_ADDI(tar, src, val) MIPS64_I_INST(MIPS64_OP_ADDI, src, tar, val)
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#define MIPS64_DADDI(tar, src, val) MIPS64_I_INST(MIPS64_OP_DADDI, src, tar, val)
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#define MIPS64_DADDIU(tar, src, val) MIPS64_I_INST(MIPS64_OP_DADDIU, src, tar, val)
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#define MIPS64_AND(reg, off, val) MIPS64_R_INST(0, off, val, reg, 0, MIPS64_OP_AND)
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#define MIPS64_ANDI(d, s, im) MIPS64_I_INST(MIPS64_OP_ANDI, s, d, im)
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#define MIPS64_SRL(d, w, sh) MIPS64_R_INST(0, 0, w, d, sh, MIPS64_OP_SRL)
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#define MIPS64_B(off) MIPS64_BEQ(0, 0, off)
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#define MIPS64_BEQ(src, tar, off) MIPS64_I_INST(MIPS64_OP_BEQ, src, tar, off)
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#define MIPS64_BNE(src, tar, off) MIPS64_I_INST(MIPS64_OP_BNE, src, tar, off)
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#define MIPS64_MFC0(gpr, cpr, sel) MIPS64_R_INST(MIPS64_OP_COP0, MIPS64_COP_MF, gpr, cpr, 0, sel)
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#define MIPS64_DMFC0(gpr, cpr, sel) MIPS64_R_INST(MIPS64_OP_COP0, MIPS64_COP_DMF, gpr, cpr, 0, sel)
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#define MIPS64_MTC0(gpr, cpr, sel) MIPS64_R_INST(MIPS64_OP_COP0, MIPS64_COP_MT, gpr, cpr, 0, sel)
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#define MIPS64_DMTC0(gpr, cpr, sel) MIPS64_R_INST(MIPS64_OP_COP0, MIPS64_COP_DMT, gpr, cpr, 0, sel)
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#define MIPS64_MFC1(gpr, cpr, sel) MIPS64_R_INST(MIPS64_OP_COP1, MIPS64_COP_MF, gpr, cpr, 0, 0)
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#define MIPS64_DMFC1(gpr, cpr, sel) MIPS64_R_INST(MIPS64_OP_COP1, MIPS64_COP_DMF, gpr, cpr, 0, 0)
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#define MIPS64_MTC1(gpr, cpr, sel) MIPS64_R_INST(MIPS64_OP_COP1, MIPS64_COP_MT, gpr, cpr, 0, 0)
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#define MIPS64_DMTC1(gpr, cpr, sel) MIPS64_R_INST(MIPS64_OP_COP1, MIPS64_COP_DMT, gpr, cpr, 0, 0)
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#define MIPS64_MFC2(gpr, cpr, sel) MIPS64_R_INST(MIPS64_OP_COP2, MIPS64_COP_MF, gpr, cpr, 0, sel)
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#define MIPS64_MTC2(gpr, cpr, sel) MIPS64_R_INST(MIPS64_OP_COP2, MIPS64_COP_MT, gpr, cpr, 0, sel)
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#define MIPS64_CFC1(gpr, cpr, sel) MIPS64_R_INST(MIPS64_OP_COP1, MIPS64_COP_CF, gpr, cpr, 0, 0)
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#define MIPS64_CTC1(gpr, cpr, sel) MIPS64_R_INST(MIPS64_OP_COP1, MIPS64_COP_CT, gpr, cpr, 0, 0)
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#define MIPS64_CFC2(gpr, cpr, sel) MIPS64_R_INST(MIPS64_OP_COP2, MIPS64_COP_CF, gpr, cpr, 0, sel)
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#define MIPS64_CTC2(gpr, cpr, sel) MIPS64_R_INST(MIPS64_OP_COP2, MIPS64_COP_CT, gpr, cpr, 0, sel)
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#define MIPS64_LBU(reg, off, base) MIPS64_I_INST(MIPS64_OP_LBU, base, reg, off)
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#define MIPS64_LHU(reg, off, base) MIPS64_I_INST(MIPS64_OP_LHU, base, reg, off)
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#define MIPS64_LUI(reg, val) MIPS64_I_INST(MIPS64_OP_LUI, 0, reg, val)
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#define MIPS64_LW(reg, off, base) MIPS64_I_INST(MIPS64_OP_LW, base, reg, off)
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#define MIPS64_LD(reg, off, base) MIPS64_I_INST(MIPS64_OP_LD, base, reg, off)
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#define MIPS64_MFLO(reg) MIPS64_R_INST(0, 0, 0, reg, 0, MIPS64_OP_MFLO)
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#define MIPS64_MFHI(reg) MIPS64_R_INST(0, 0, 0, reg, 0, MIPS64_OP_MFHI)
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#define MIPS64_MTLO(reg) MIPS64_R_INST(0, reg, 0, 0, 0, MIPS64_OP_MTLO)
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#define MIPS64_MTHI(reg) MIPS64_R_INST(0, reg, 0, 0, 0, MIPS64_OP_MTHI)
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#define MIPS64_ORI(src, tar, val) MIPS64_I_INST(MIPS64_OP_ORI, src, tar, val)
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#define MIPS64_SB(reg, off, base) MIPS64_I_INST(MIPS64_OP_SB, base, reg, off)
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#define MIPS64_SH(reg, off, base) MIPS64_I_INST(MIPS64_OP_SH, base, reg, off)
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#define MIPS64_SW(reg, off, base) MIPS64_I_INST(MIPS64_OP_SW, base, reg, off)
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#define MIPS64_SD(reg, off, base) MIPS64_I_INST(MIPS64_OP_SD, base, reg, off)
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#define MIPS64_CACHE(op, reg, off) (47 << 26 | (reg) << 21 | (op) << 16 | (off))
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#define MIPS64_SYNCI(reg, off) (1 << 26 | (reg) << 21 | 0x1f << 16 | (off))
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#define MIPS64_JR(reg) MIPS64_R_INST(0, reg, 0, 0, 0, MIPS64_OP_JR)
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/* ejtag specific instructions */
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#define MIPS64_DRET 0x4200001F
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#define MIPS64_SDBBP 0x7000003F
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#define MIPS64_SDBBP_LE 0x3f000007
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#define MIPS64_SDBBP_SIZE 4
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#define MIPS16_SDBBP_SIZE 2
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#define MIPS64_SYNC 0x0000000F
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int mips64_arch_state(struct target *target);
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int mips64_init_arch_info(struct target *target, struct mips64_common *mips64, struct jtag_tap *tap);
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int mips64_restore_context(struct target *target);
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int mips64_save_context(struct target *target);
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int mips64_build_reg_cache(struct target *target);
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int mips64_run_algorithm(struct target *target, int num_mem_params, struct mem_param *mem_params,
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int num_reg_params, struct reg_param *reg_params,
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target_addr_t entry_point, target_addr_t exit_point,
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int timeout_ms, void *arch_info);
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int mips64_configure_break_unit(struct target *target);
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int mips64_enable_interrupts(struct target *target, bool enable);
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int mips64_examine(struct target *target);
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int mips64_register_commands(struct command_context *cmd_ctx);
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int mips64_invalidate_core_regs(struct target *target);
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int mips64_get_gdb_reg_list(struct target *target,
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struct reg **reg_list[], int *reg_list_size,
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enum target_register_class reg_class);
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#endif /* OPENOCD_TARGET_MIPS64_H */
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1431
src/target/mips64_pracc.c
Normal file
1431
src/target/mips64_pracc.c
Normal file
File diff suppressed because it is too large
Load Diff
59
src/target/mips64_pracc.h
Normal file
59
src/target/mips64_pracc.h
Normal file
@@ -0,0 +1,59 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Support for processors implementing MIPS64 instruction set
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*
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* Copyright (C) 2014 by Andrey Sidorov <anysidorov@gmail.com>
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* Copyright (C) 2014 by Aleksey Kuleshov <rndfax@yandex.ru>
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* Copyright (C) 2014-2019 by Peter Mamonov <pmamonov@gmail.com>
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*
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* Based on the work of:
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* Copyright (C) 2008 by Spencer Oliver
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* Copyright (C) 2008 by David T.L. Wong
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* Copyright (C) 2010 by Konstantin Kostyukhin, Nikolay Shmyrev
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*/
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#ifndef OPENOCD_TARGET_MIPS64_PRACC_H
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#define OPENOCD_TARGET_MIPS64_PRACC_H
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#include "mips_ejtag.h"
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#define MIPS64_PRACC_TEXT 0xffffffffFF200200ull
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#define MIPS64_PRACC_STACK 0xffffffffFF204000ull
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#define MIPS64_PRACC_PARAM_IN 0xffffffffFF201000ull
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#define MIPS64_PRACC_PARAM_IN_SIZE 0x1000
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#define MIPS64_PRACC_PARAM_OUT (MIPS64_PRACC_PARAM_IN + MIPS64_PRACC_PARAM_IN_SIZE)
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#define MIPS64_PRACC_PARAM_OUT_SIZE 0x1000
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#undef UPPER16
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#undef LOWER16
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#define UPPER16(v) ((uint32_t)((v >> 16) & 0xFFFF))
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#define LOWER16(v) ((uint32_t)(v & 0xFFFF))
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#define MIPS64_PRACC_FASTDATA_AREA 0xffffffffFF200000
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#define MIPS64_PRACC_FASTDATA_SIZE 16
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#define MIPS64_FASTDATA_HANDLER_SIZE 0x80
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/* FIXME: 16-bit NEG */
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#undef NEG16
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#define NEG16(v) ((uint32_t)(((~(v)) + 1) & 0xFFFF))
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#define MIPS64_PRACC_ADDR_STEP 4
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#define MIPS64_PRACC_DATA_STEP 8
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int mips64_pracc_read_mem(struct mips_ejtag *ejtag_info, uint64_t addr, unsigned size, unsigned count, void *buf);
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int mips64_pracc_write_mem(struct mips_ejtag *ejtag_info, uint64_t addr, unsigned size, unsigned count, void *buf);
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int mips64_pracc_read_regs(struct mips_ejtag *ejtag_info, uint64_t *regs);
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int mips64_pracc_write_regs(struct mips_ejtag *ejtag_info, uint64_t *regs);
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int mips64_pracc_exec(struct mips_ejtag *ejtag_info,
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unsigned code_len, const uint32_t *code,
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unsigned num_param_in, uint64_t *param_in,
|
||||
unsigned num_param_out, uint64_t *param_out);
|
||||
|
||||
int mips64_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info,
|
||||
struct working_area *source,
|
||||
bool write_t, uint64_t addr,
|
||||
unsigned count, uint64_t *buf);
|
||||
|
||||
#endif /* OPENOCD_TARGET_MIPS64_PRACC_H */
|
||||
@@ -28,6 +28,11 @@
|
||||
#include "mips_ejtag.h"
|
||||
#include "mips32_dmaacc.h"
|
||||
|
||||
#if BUILD_TARGET64 == 1
|
||||
#include "mips64.h"
|
||||
#include "mips64_pracc.h"
|
||||
#endif
|
||||
|
||||
void mips_ejtag_set_instr(struct mips_ejtag *ejtag_info, uint32_t new_instr)
|
||||
{
|
||||
assert(ejtag_info->tap != NULL);
|
||||
@@ -87,6 +92,36 @@ void mips_ejtag_add_scan_96(struct mips_ejtag *ejtag_info, uint32_t ctrl, uint32
|
||||
keep_alive();
|
||||
}
|
||||
|
||||
int mips_ejtag_drscan_64(struct mips_ejtag *ejtag_info, uint64_t *data)
|
||||
{
|
||||
struct jtag_tap *tap;
|
||||
tap = ejtag_info->tap;
|
||||
|
||||
if (tap == NULL)
|
||||
return ERROR_FAIL;
|
||||
struct scan_field field;
|
||||
uint8_t t[8], r[8];
|
||||
int retval;
|
||||
|
||||
field.num_bits = 64;
|
||||
field.out_value = t;
|
||||
buf_set_u64(t, 0, field.num_bits, *data);
|
||||
field.in_value = r;
|
||||
|
||||
jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
|
||||
retval = jtag_execute_queue();
|
||||
if (retval != ERROR_OK) {
|
||||
LOG_ERROR("register read failed");
|
||||
return retval;
|
||||
}
|
||||
|
||||
*data = buf_get_u64(field.in_value, 0, 64);
|
||||
|
||||
keep_alive();
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
void mips_ejtag_drscan_32_queued(struct mips_ejtag *ejtag_info, uint32_t data_out, uint8_t *data_in)
|
||||
{
|
||||
assert(ejtag_info->tap != NULL);
|
||||
@@ -422,3 +457,112 @@ int mips_ejtag_fastdata_scan(struct mips_ejtag *ejtag_info, int write_t, uint32_
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
#if BUILD_TARGET64 == 1
|
||||
|
||||
int mips64_ejtag_config_step(struct mips_ejtag *ejtag_info, bool enable_step)
|
||||
{
|
||||
const uint32_t code_enable[] = {
|
||||
MIPS64_MTC0(1, 31, 0), /* move $1 to COP0 DeSave */
|
||||
MIPS64_MFC0(1, 23, 0), /* move COP0 Debug to $1 */
|
||||
MIPS64_ORI(1, 1, 0x0100), /* set SSt bit in debug reg */
|
||||
MIPS64_MTC0(1, 23, 0), /* move $1 to COP0 Debug */
|
||||
MIPS64_B(NEG16(5)),
|
||||
MIPS64_MFC0(1, 31, 0), /* move COP0 DeSave to $1 */
|
||||
MIPS64_NOP,
|
||||
MIPS64_NOP,
|
||||
MIPS64_NOP,
|
||||
MIPS64_NOP,
|
||||
MIPS64_NOP,
|
||||
MIPS64_NOP,
|
||||
MIPS64_NOP,
|
||||
MIPS64_NOP,
|
||||
};
|
||||
|
||||
const uint32_t code_disable[] = {
|
||||
MIPS64_MTC0(15, 31, 0), /* move $15 to COP0 DeSave */
|
||||
MIPS64_LUI(15, UPPER16(MIPS64_PRACC_STACK)), /* $15 = MIPS64_PRACC_STACK */
|
||||
MIPS64_ORI(15, 15, LOWER16(MIPS64_PRACC_STACK)),
|
||||
MIPS64_SD(1, 0, 15), /* sw $1,($15) */
|
||||
MIPS64_SD(2, 0, 15), /* sw $2,($15) */
|
||||
MIPS64_MFC0(1, 23, 0), /* move COP0 Debug to $1 */
|
||||
MIPS64_LUI(2, 0xFFFF), /* $2 = 0xfffffeff */
|
||||
MIPS64_ORI(2, 2, 0xFEFF),
|
||||
MIPS64_AND(1, 1, 2),
|
||||
MIPS64_MTC0(1, 23, 0), /* move $1 to COP0 Debug */
|
||||
MIPS64_LD(2, 0, 15),
|
||||
MIPS64_LD(1, 0, 15),
|
||||
MIPS64_SYNC,
|
||||
MIPS64_B(NEG16(14)),
|
||||
MIPS64_MFC0(15, 31, 0), /* move COP0 DeSave to $15 */
|
||||
MIPS64_NOP,
|
||||
MIPS64_NOP,
|
||||
MIPS64_NOP,
|
||||
MIPS64_NOP,
|
||||
MIPS64_NOP,
|
||||
MIPS64_NOP,
|
||||
MIPS64_NOP,
|
||||
MIPS64_NOP,
|
||||
};
|
||||
const uint32_t *code = enable_step ? code_enable : code_disable;
|
||||
unsigned code_len = enable_step ? ARRAY_SIZE(code_enable) :
|
||||
ARRAY_SIZE(code_disable);
|
||||
|
||||
return mips64_pracc_exec(ejtag_info,
|
||||
code_len, code, 0, NULL, 0, NULL);
|
||||
}
|
||||
|
||||
int mips64_ejtag_exit_debug(struct mips_ejtag *ejtag_info)
|
||||
{
|
||||
const uint32_t code[] = {
|
||||
MIPS64_DRET,
|
||||
MIPS64_NOP,
|
||||
MIPS64_NOP,
|
||||
MIPS64_NOP,
|
||||
MIPS64_NOP,
|
||||
MIPS64_NOP,
|
||||
MIPS64_NOP,
|
||||
MIPS64_NOP,
|
||||
};
|
||||
LOG_DEBUG("enter mips64_pracc_exec");
|
||||
return mips64_pracc_exec(ejtag_info,
|
||||
ARRAY_SIZE(code), code, 0, NULL, 0, NULL);
|
||||
}
|
||||
|
||||
int mips64_ejtag_fastdata_scan(struct mips_ejtag *ejtag_info, bool write_t, uint64_t *data)
|
||||
{
|
||||
struct jtag_tap *tap;
|
||||
|
||||
tap = ejtag_info->tap;
|
||||
assert(tap != NULL);
|
||||
|
||||
struct scan_field fields[2];
|
||||
uint8_t spracc = 0;
|
||||
uint8_t t[8] = {0, 0, 0, 0, 0, 0, 0, 0};
|
||||
|
||||
/* fastdata 1-bit register */
|
||||
fields[0].num_bits = 1;
|
||||
fields[0].out_value = &spracc;
|
||||
fields[0].in_value = NULL;
|
||||
|
||||
/* processor access data register 64 bit */
|
||||
fields[1].num_bits = 64;
|
||||
fields[1].out_value = t;
|
||||
|
||||
if (write_t) {
|
||||
fields[1].in_value = NULL;
|
||||
buf_set_u64(t, 0, 64, *data);
|
||||
} else
|
||||
fields[1].in_value = (uint8_t *) data;
|
||||
|
||||
jtag_add_dr_scan(tap, 2, fields, TAP_IDLE);
|
||||
|
||||
if (!write_t && data)
|
||||
jtag_add_callback(mips_le_to_h_u64,
|
||||
(jtag_callback_data_t) data);
|
||||
keep_alive();
|
||||
|
||||
return ERROR_OK;
|
||||
}
|
||||
|
||||
#endif /* BUILD_TARGET64 */
|
||||
|
||||
@@ -182,6 +182,20 @@
|
||||
#define EJTAG_VERSION_41 4
|
||||
#define EJTAG_VERSION_51 5
|
||||
|
||||
/*
|
||||
* Additional defines for MIPS64 EJTAG
|
||||
*/
|
||||
#define EJTAG64_DCR 0xFFFFFFFFFF300000ull
|
||||
#define EJTAG64_DCR_ENM (1llu << 29)
|
||||
#define EJTAG64_DCR_DB (1llu << 17)
|
||||
#define EJTAG64_DCR_IB (1llu << 16)
|
||||
#define EJTAG64_DCR_INTE (1llu << 4)
|
||||
#define EJTAG64_DCR_MP (1llu << 2)
|
||||
#define EJTAG64_V25_DBA0 0xFFFFFFFFFF302100ull
|
||||
#define EJTAG64_V25_DBS 0xFFFFFFFFFF302000ull
|
||||
#define EJTAG64_V25_IBA0 0xFFFFFFFFFF301100ull
|
||||
#define EJTAG64_V25_IBS 0xFFFFFFFFFF301000ull
|
||||
|
||||
struct mips_ejtag {
|
||||
struct jtag_tap *tap;
|
||||
uint32_t impcode;
|
||||
@@ -224,17 +238,21 @@ struct mips_ejtag {
|
||||
void mips_ejtag_set_instr(struct mips_ejtag *ejtag_info, uint32_t new_instr);
|
||||
int mips_ejtag_enter_debug(struct mips_ejtag *ejtag_info);
|
||||
int mips_ejtag_exit_debug(struct mips_ejtag *ejtag_info);
|
||||
int mips64_ejtag_exit_debug(struct mips_ejtag *ejtag_info);
|
||||
int mips_ejtag_get_idcode(struct mips_ejtag *ejtag_info);
|
||||
void mips_ejtag_add_scan_96(struct mips_ejtag *ejtag_info,
|
||||
uint32_t ctrl, uint32_t data, uint8_t *in_scan_buf);
|
||||
int mips_ejtag_drscan_64(struct mips_ejtag *ejtag_info, uint64_t *data);
|
||||
void mips_ejtag_drscan_32_out(struct mips_ejtag *ejtag_info, uint32_t data);
|
||||
int mips_ejtag_drscan_32(struct mips_ejtag *ejtag_info, uint32_t *data);
|
||||
void mips_ejtag_drscan_8_out(struct mips_ejtag *ejtag_info, uint8_t data);
|
||||
int mips_ejtag_drscan_8(struct mips_ejtag *ejtag_info, uint8_t *data);
|
||||
int mips_ejtag_fastdata_scan(struct mips_ejtag *ejtag_info, int write_t, uint32_t *data);
|
||||
int mips64_ejtag_fastdata_scan(struct mips_ejtag *ejtag_info, bool write_t, uint64_t *data);
|
||||
|
||||
int mips_ejtag_init(struct mips_ejtag *ejtag_info);
|
||||
int mips_ejtag_config_step(struct mips_ejtag *ejtag_info, int enable_step);
|
||||
int mips64_ejtag_config_step(struct mips_ejtag *ejtag_info, bool enable_step);
|
||||
|
||||
static inline void mips_le_to_h_u32(jtag_callback_data_t arg)
|
||||
{
|
||||
@@ -242,4 +260,10 @@ static inline void mips_le_to_h_u32(jtag_callback_data_t arg)
|
||||
*((uint32_t *)arg) = le_to_h_u32(in);
|
||||
}
|
||||
|
||||
static inline void mips_le_to_h_u64(jtag_callback_data_t arg)
|
||||
{
|
||||
uint8_t *in = (uint8_t *)arg;
|
||||
*((uint64_t *)arg) = le_to_h_u64(in);
|
||||
}
|
||||
|
||||
#endif /* OPENOCD_TARGET_MIPS_EJTAG_H */
|
||||
|
||||
Reference in New Issue
Block a user