mirror of
https://github.com/linux-msm/openocd.git
synced 2026-02-25 13:15:07 -08:00
- merged support for Cortex-M3 from cortex-m3 branch (thanks to Magnus Lundin)
git-svn-id: svn://svn.berlios.de/openocd/trunk@170 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
drath
@@ -1,5 +1,5 @@
|
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INCLUDES = -I$(top_srcdir)/src/helper -I$(top_srcdir)/src/jtag -I$(top_srcdir)/src/target $(all_includes)
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METASOURCES = AUTO
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noinst_LIBRARIES = libflash.a
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libflash_a_SOURCES = flash.c lpc2000.c cfi.c non_cfi.c at91sam7.c str7x.c str9x.c nand.c lpc3180_nand_controller.c
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noinst_HEADERS = flash.h lpc2000.h cfi.h non_cfi.h at91sam7.h str7x.h str9x.h nand.h lpc3180_nand_controller.h
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libflash_a_SOURCES = flash.c lpc2000.c cfi.c non_cfi.c at91sam7.c str7x.c str9x.c nand.c lpc3180_nand_controller.c stellaris.c
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noinst_HEADERS = flash.h lpc2000.h cfi.h non_cfi.h at91sam7.h str7x.h str9x.h nand.h lpc3180_nand_controller.h stellaris.h
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@@ -55,6 +55,7 @@ extern flash_driver_t cfi_flash;
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extern flash_driver_t at91sam7_flash;
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extern flash_driver_t str7x_flash;
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extern flash_driver_t str9x_flash;
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extern flash_driver_t stellaris_flash;
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flash_driver_t *flash_drivers[] =
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{
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@@ -63,6 +64,7 @@ flash_driver_t *flash_drivers[] =
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&at91sam7_flash,
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&str7x_flash,
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&str9x_flash,
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&stellaris_flash,
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NULL,
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};
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@@ -3,7 +3,7 @@ METASOURCES = AUTO
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noinst_LIBRARIES = libtarget.a
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libtarget_a_SOURCES = target.c register.c breakpoints.c armv4_5.c embeddedice.c etm.c arm7tdmi.c arm9tdmi.c \
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arm_jtag.c arm7_9_common.c algorithm.c arm920t.c arm720t.c armv4_5_mmu.c armv4_5_cache.c arm_disassembler.c \
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arm966e.c arm926ejs.c etb.c xscale.c arm_simulator.c image.c
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arm966e.c arm926ejs.c etb.c xscale.c arm_simulator.c image.c armv7m.c cortex_m3.c cortex_swjdp.c
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noinst_HEADERS = target.h register.h armv4_5.h embeddedice.h etm.h arm7tdmi.h arm9tdmi.h \
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arm_jtag.h arm7_9_common.h arm920t.h arm720t.h armv4_5_mmu.h armv4_5_cache.h breakpoints.h algorithm.h \
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arm_disassembler.h arm966e.h arm926ejs.h etb.h xscale.h arm_simulator.h image.h
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arm_disassembler.h arm966e.h arm926ejs.h etb.h xscale.h arm_simulator.h image.h armv7m.h cortex_m3.h cortex_swjdp.h
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590
src/target/armv7m.c
Normal file
590
src/target/armv7m.c
Normal file
File diff suppressed because it is too large
Load Diff
248
src/target/armv7m.h
Normal file
248
src/target/armv7m.h
Normal file
@@ -0,0 +1,248 @@
|
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/***************************************************************************
|
||||
* Copyright (C) 2005 by Dominic Rath *
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||||
* Dominic.Rath@gmx.de *
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||||
* Copyright (C) 2006 by Magnus Lundin *
|
||||
* lundin@mlu.mine.nu *
|
||||
* *
|
||||
* This program is free software; you can redistribute it and/or modify *
|
||||
* it under the terms of the GNU General Public License as published by *
|
||||
* the Free Software Foundation; either version 2 of the License, or *
|
||||
* (at your option) any later version. *
|
||||
* *
|
||||
* This program is distributed in the hope that it will be useful, *
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
|
||||
* GNU General Public License for more details. *
|
||||
* *
|
||||
* You should have received a copy of the GNU General Public License *
|
||||
* along with this program; if not, write to the *
|
||||
* Free Software Foundation, Inc., *
|
||||
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
|
||||
***************************************************************************/
|
||||
#ifndef ARMV7M_COMMON_H
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#define ARMV7M_COMMON_H
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#include "register.h"
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#include "target.h"
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#include "arm_jtag.h"
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enum armv7m_mode
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{
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ARMV7M_MODE_HANDLER = 0,
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ARMV7M_MODE_THREAD = 1,
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ARMV7M_MODE_ANY = -1
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};
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extern char* armv7m_mode_strings[];
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enum armv7m_state
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{
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ARMV7M_STATE_THUMB,
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ARMV7M_STATE_DEBUG,
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};
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enum armv7m_regtype
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{
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ARMV7M_REGISTER_CORE_GP,
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ARMV7M_REGISTER_CORE_SP,
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ARMV7M_REGISTER_MEMMAP
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};
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enum armv7m_runcontext
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{
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ARMV7M_PROCESS_CONTEXT,
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ARMV7M_DEBUG_CONTEXT
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};
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extern char* armv7m_state_strings[];
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//#define ARMV7NUMCOREREGS 23
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/* offsets into armv7m core register cache */
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enum
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{
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ARMV7M_PC = 15,
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ARMV7M_xPSR = 16,
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ARMV7M_MSP ,
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ARMV7M_PSP ,
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ARMV7M_PRIMASK ,
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ARMV7M_BASEPRI,
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ARMV7M_FAULTMASK,
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ARMV7M_CONTROL,
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ARMV7NUMCOREREGS
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};
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#define ARMV7M_COMMON_MAGIC 0x2A452A45
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typedef struct armv7m_common_s
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{
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int common_magic;
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reg_cache_t *core_cache;
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reg_cache_t *process_context;
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reg_cache_t *debug_context;
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enum armv7m_mode core_mode;
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enum armv7m_state core_state;
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int exception_number;
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int (*full_context)(struct target_s *target);
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/* Direct processor core register read and writes */
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int (*load_core_reg_u32)(struct target_s *target, enum armv7m_regtype type, u32 num, u32 *value);
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int (*store_core_reg_u32)(struct target_s *target, enum armv7m_regtype type, u32 num, u32 value);
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/* register cache to processor synchronization */
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int (*read_core_reg)(struct target_s *target, int num);
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int (*write_core_reg)(struct target_s *target, int num);
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/* get or set register through cache, return error if target is running and synchronisation is impossible */
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int (*get_core_reg_32)(struct target_s *target, int num, u32* value);
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int (*set_core_reg_32)(struct target_s *target, int num, u32 value);
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arm_jtag_t jtag_info;
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reg_cache_t *eice_cache;
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reg_cache_t *etm_cache;
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int (*examine_debug_reason)(target_t *target);
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void (*change_to_arm)(target_t *target, u32 *r0, u32 *pc);
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// void (*read_core_regs)(target_t *target, u32 mask, u32 *core_regs[16]);
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// void (*read_core_regs_target_buffer)(target_t *target, u32 mask, void *buffer, int size);
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// void (*write_core_regs)(target_t *target, u32 mask, u32 core_regs[16]);
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/*
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void (*write_xpsr_im8)(target_t *target, u8 xpsr_im, int rot, int spsr);
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void (*load_word_regs)(target_t *target, u32 mask);
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void (*load_hword_reg)(target_t *target, int num);
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void (*load_byte_reg)(target_t *target, int num);
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void (*store_word_regs)(target_t *target, u32 mask);
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void (*store_hword_reg)(target_t *target, int num);
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void (*store_byte_reg)(target_t *target, int num);
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void (*write_pc)(target_t *target, u32 pc);
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void (*branch_resume)(target_t *target);
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*/
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void (*pre_debug_entry)(target_t *target);
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void (*post_debug_entry)(target_t *target);
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void (*pre_restore_context)(target_t *target);
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void (*post_restore_context)(target_t *target);
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void *arch_info;
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} armv7m_common_t;
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typedef struct armv7m_algorithm_s
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{
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int common_magic;
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enum armv7m_mode core_mode;
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enum armv7m_state core_state;
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} armv7m_algorithm_t;
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typedef struct armv7m_core_reg_s
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{
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u32 num;
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enum armv7m_regtype type;
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enum armv7m_mode mode;
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target_t *target;
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armv7m_common_t *armv7m_common;
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} armv7m_core_reg_t;
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extern reg_cache_t *armv7m_build_reg_cache(target_t *target);
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extern enum armv7m_mode armv7m_number_to_mode(int number);
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extern int armv7m_mode_to_number(enum armv7m_mode mode);
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extern int armv7m_arch_state(struct target_s *target, char *buf, int buf_size);
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extern int armv7m_get_gdb_reg_list(target_t *target, reg_t **reg_list[], int *reg_list_size);
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extern int armv7m_invalidate_core_regs(target_t *target);
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extern int armv7m_register_commands(struct command_context_s *cmd_ctx);
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extern int armv7m_init_arch_info(target_t *target, armv7m_common_t *armv7m);
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extern int armv7m_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info);
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extern int armv7m_invalidate_core_regs(target_t *target);
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/* Thumb mode instructions
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*/
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/* Move to Register from Special Register (Thumb mode) 32 bit Thumb2 instruction
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* Rd: destination register
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* SYSm: source special register
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*/
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#define ARMV7M_T_MRS(Rd, SYSm) ((0xF3EF) | ((0x8000 | (Rd<<8) | SYSm) << 16))
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/* Move from Register from Special Register (Thumb mode) 32 bit Thumb2 instruction
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* Rd: source register
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* SYSm: destination special register
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*/
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#define ARMV7M_T_MSR(SYSm, Rn) ((0xF380 | ( Rn<<8 )) | ((0x8800 | SYSm) << 16))
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/* Change Processor State. The instruction modifies the PRIMASK and FAULTMASK
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* special-purpose register values (Thumb mode) 16 bit Thumb2 instruction
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* Rd: source register
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* IF:
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*/
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#define I_FLAG 2
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#define F_FLAG 1
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#define ARMV7M_T_CPSID(IF) ((0xB660 | (1<<8) | (IF&0x3)) | ((0xB660 | (1<<8) | (IF&0x3)) << 16))
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#define ARMV7M_T_CPSIE(IF) ((0xB660 | (0<<8) | (IF&0x3)) | ((0xB660 | (0<<8) | (IF&0x3)) << 16))
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/* Breakpoint (Thumb mode) v5 onwards
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* Im: immediate value used by debugger
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*/
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#define ARMV7M_T_BKPT(Im) ((0xBE00 | Im ) | ((0xBE00 | Im ) << 16))
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|
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/* Store register (Thumb mode)
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* Rd: source register
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||||
* Rn: base register
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||||
*/
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||||
#define ARMV7M_T_STR(Rd, Rn) ((0x6000 | Rd | (Rn << 3)) | ((0x6000 | Rd | (Rn << 3)) << 16))
|
||||
|
||||
/* Load register (Thumb state)
|
||||
* Rd: destination register
|
||||
* Rn: base register
|
||||
*/
|
||||
#define ARMV7M_T_LDR(Rd, Rn) ((0x6800 | (Rn << 3) | Rd) | ((0x6800 | (Rn << 3) | Rd) << 16))
|
||||
|
||||
/* Load multiple (Thumb state)
|
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* Rn: base register
|
||||
* List: for each bit in list: store register
|
||||
*/
|
||||
#define ARMV7M_T_LDMIA(Rn, List) ((0xc800 | (Rn << 8) | List) | ((0xc800 | (Rn << 8) | List) << 16))
|
||||
|
||||
/* Load register with PC relative addressing
|
||||
* Rd: register to load
|
||||
*/
|
||||
#define ARMV7M_T_LDR_PCREL(Rd) ((0x4800 | (Rd << 8)) | ((0x4800 | (Rd << 8)) << 16))
|
||||
|
||||
/* Move hi register (Thumb mode)
|
||||
* Rd: destination register
|
||||
* Rm: source register
|
||||
*/
|
||||
#define ARMV7M_T_MOV(Rd, Rm) ((0x4600 | (Rd & 0x7) | ((Rd & 0x8) << 4) | ((Rm & 0x7) << 3) | ((Rm & 0x8) << 3)) | ((0x4600 | (Rd & 0x7) | ((Rd & 0x8) << 4) | ((Rm & 0x7) << 3) | ((Rm & 0x8) << 3)) << 16))
|
||||
|
||||
/* No operation (Thumb mode)
|
||||
*/
|
||||
#define ARMV7M_T_NOP (0x46c0 | (0x46c0 << 16))
|
||||
|
||||
/* Move immediate to register (Thumb state)
|
||||
* Rd: destination register
|
||||
* Im: 8-bit immediate value
|
||||
*/
|
||||
#define ARMV7M_T_MOV_IM(Rd, Im) ((0x2000 | (Rd << 8) | Im) | ((0x2000 | (Rd << 8) | Im) << 16))
|
||||
|
||||
/* Branch and Exchange
|
||||
* Rm: register containing branch target
|
||||
*/
|
||||
#define ARMV7M_T_BX(Rm) ((0x4700 | (Rm << 3)) | ((0x4700 | (Rm << 3)) << 16))
|
||||
|
||||
/* Branch (Thumb state)
|
||||
* Imm: Branch target
|
||||
*/
|
||||
#define ARMV7M_T_B(Imm) ((0xe000 | Imm) | ((0xe000 | Imm) << 16))
|
||||
|
||||
#endif /* ARMV7M_H */
|
||||
1413
src/target/cortex_m3.c
Normal file
1413
src/target/cortex_m3.c
Normal file
File diff suppressed because it is too large
Load Diff
218
src/target/cortex_m3.h
Normal file
218
src/target/cortex_m3.h
Normal file
@@ -0,0 +1,218 @@
|
||||
/***************************************************************************
|
||||
* Copyright (C) 2005 by Dominic Rath *
|
||||
* Dominic.Rath@gmx.de *
|
||||
* Copyright (C) 2006 by Magnus Lundin *
|
||||
* lundin@mlu.mine.nu *
|
||||
* *
|
||||
* This program is free software; you can redistribute it and/or modify *
|
||||
* it under the terms of the GNU General Public License as published by *
|
||||
* the Free Software Foundation; either version 2 of the License, or *
|
||||
* (at your option) any later version. *
|
||||
* *
|
||||
* This program is distributed in the hope that it will be useful, *
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
|
||||
* GNU General Public License for more details. *
|
||||
* *
|
||||
* You should have received a copy of the GNU General Public License *
|
||||
* along with this program; if not, write to the *
|
||||
* Free Software Foundation, Inc., *
|
||||
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
|
||||
***************************************************************************/
|
||||
#ifndef CORTEX_M3_H
|
||||
#define CORTEX_M3_H
|
||||
|
||||
#include "register.h"
|
||||
#include "target.h"
|
||||
#include "armv7m.h"
|
||||
#include "cortex_swjdp.h"
|
||||
|
||||
extern char* cortex_m3_state_strings[];
|
||||
|
||||
#define CORTEX_M3_COMMON_MAGIC 0x1A451A45
|
||||
|
||||
#define SYSTEM_CONTROL_BASE 0x400FE000
|
||||
|
||||
#define CPUID 0xE000ED00
|
||||
/* Debug Control Block */
|
||||
#define DCB_DHCSR 0xE000EDF0
|
||||
#define DCB_DCRSR 0xE000EDF4
|
||||
#define DCB_DCRDR 0xE000EDF8
|
||||
#define DCB_DEMCR 0xE000EDFC
|
||||
|
||||
|
||||
#define DCRSR_WnR (1<<16)
|
||||
|
||||
#define DWT_CTRL 0xE0001000
|
||||
#define DWT_COMP0 0xE0001020
|
||||
#define DWT_MASK0 0xE0001024
|
||||
#define DWT_FUNCTION0 0xE0001028
|
||||
|
||||
#define FP_CTRL 0xE0002000
|
||||
#define FP_REMAP 0xE0002004
|
||||
#define FP_COMP0 0xE0002008
|
||||
#define FP_COMP1 0xE000200C
|
||||
#define FP_COMP2 0xE0002010
|
||||
#define FP_COMP3 0xE0002014
|
||||
#define FP_COMP4 0xE0002018
|
||||
#define FP_COMP5 0xE000201C
|
||||
#define FP_COMP6 0xE0002020
|
||||
#define FP_COMP7 0xE0002024
|
||||
|
||||
#define DWT_CTRL 0xE0001000
|
||||
|
||||
/* DCB_DHCSR bit and field definitions */
|
||||
#define DBGKEY (0xA05F<<16)
|
||||
#define C_DEBUGEN (1<<0)
|
||||
#define C_HALT (1<<1)
|
||||
#define C_STEP (1<<2)
|
||||
#define C_MASKINTS (1<<3)
|
||||
#define S_REGRDY (1<<16)
|
||||
#define S_HALT (1<<17)
|
||||
#define S_SLEEP (1<<18)
|
||||
#define S_LOCKUP (1<<19)
|
||||
#define S_RETIRE_ST (1<<24)
|
||||
#define S_RESET_ST (1<<25)
|
||||
|
||||
/* DCB_DEMCR bit and field definitions */
|
||||
#define TRCENA (1<<24)
|
||||
#define VC_HARDERR (1<<10)
|
||||
#define VC_BUSERR (1<<8)
|
||||
#define VC_CORERESET (1<<0)
|
||||
|
||||
#define NVIC_ICTR 0xE000E004
|
||||
#define NVIC_ISE0 0xE000E100
|
||||
#define NVIC_ICSR 0xE000ED04
|
||||
#define NVIC_AIRCR 0xE000ED0C
|
||||
#define NVIC_SHCSR 0xE000ED24
|
||||
#define NVIC_CFSR 0xE000ED28
|
||||
#define NVIC_MMFSRb 0xE000ED28
|
||||
#define NVIC_BFSRb 0xE000ED29
|
||||
#define NVIC_USFSRh 0xE000ED2A
|
||||
#define NVIC_HFSR 0xE000ED2C
|
||||
#define NVIC_DFSR 0xE000ED30
|
||||
#define NVIC_MMFAR 0xE000ED34
|
||||
#define NVIC_BFAR 0xE000ED38
|
||||
|
||||
/* NVIC_AIRCR bits */
|
||||
#define AIRCR_VECTKEY (0x5FA<<16)
|
||||
#define AIRCR_SYSRESETREQ (1<<2)
|
||||
#define AIRCR_VECTCLRACTIVE (1<<1)
|
||||
#define AIRCR_VECTRESET (1<<0)
|
||||
/* NVIC_SHCSR bits */
|
||||
#define SHCSR_BUSFAULTENA (1<<17)
|
||||
/* NVIC_DFSR bits */
|
||||
#define DFSR_HALTED 1
|
||||
#define DFSR_BKPT 2
|
||||
#define DFSR_DWTTRAP 4
|
||||
#define DFSR_VCATCH 8
|
||||
|
||||
|
||||
#define FPCR_CODE 0
|
||||
#define FPCR_LITERAL 1
|
||||
#define FPCR_REPLACE_REMAP (0<<30)
|
||||
#define FPCR_REPLACE_BKPT_LOW (1<<30)
|
||||
#define FPCR_REPLACE_BKPT_HIGH (2<<30)
|
||||
#define FPCR_REPLACE_BKPT_BOTH (3<<30)
|
||||
|
||||
typedef struct cortex_m3_fp_comparator_s
|
||||
{
|
||||
int used;
|
||||
int type;
|
||||
u32 fpcr_value;
|
||||
u32 fpcr_address;
|
||||
} cortex_m3_fp_comparator_t;
|
||||
|
||||
typedef struct cortex_m3_dwt_comparator_s
|
||||
{
|
||||
int used;
|
||||
u32 comp;
|
||||
u32 mask;
|
||||
u32 function;
|
||||
u32 dwt_comparator_address;
|
||||
} cortex_m3_dwt_comparator_t;
|
||||
|
||||
typedef struct cortex_m3_common_s
|
||||
{
|
||||
int common_magic;
|
||||
// int (*full_context)(struct target_s *target);
|
||||
|
||||
arm_jtag_t jtag_info;
|
||||
|
||||
/* Context information */
|
||||
u32 dcb_dhcsr;
|
||||
u32 nvic_dfsr; /* Debug Fault Status Register - shows reason for debug halt */
|
||||
u32 nvic_icsr; /* Interrupt Control State Register - shows active and pending IRQ */
|
||||
|
||||
/* Flash Patch and Breakpoint */
|
||||
int fp_num_lit;
|
||||
int fp_num_code;
|
||||
int fp_code_available;
|
||||
int auto_bp_type;
|
||||
cortex_m3_fp_comparator_t * fp_comparator_list;
|
||||
|
||||
/* DWT */
|
||||
int dwt_num_comp;
|
||||
int dwt_comp_available;
|
||||
cortex_m3_dwt_comparator_t * dwt_comparator_list;
|
||||
|
||||
/* Interrupts */
|
||||
int intlinesnum;
|
||||
u32 * intsetenable;
|
||||
|
||||
/*
|
||||
u32 arm_bkpt;
|
||||
u16 thumb_bkpt;
|
||||
int sw_bkpts_use_wp;
|
||||
int wp_available;
|
||||
int wp0_used;
|
||||
int wp1_used;
|
||||
|
||||
int force_hw_bkpts;
|
||||
int dbgreq_adjust_pc;
|
||||
int use_dbgrq;
|
||||
int has_etm;
|
||||
|
||||
int reinit_embeddedice;
|
||||
|
||||
struct working_area_s *dcc_working_area;
|
||||
|
||||
int fast_memory_access;
|
||||
int dcc_downloads;
|
||||
*/
|
||||
/* breakpoint use map */
|
||||
int sw_bkpts_enabled;
|
||||
|
||||
armv7m_common_t armv7m;
|
||||
swjdp_common_t swjdp_info;
|
||||
|
||||
void *arch_info;
|
||||
} cortex_m3_common_t;
|
||||
|
||||
|
||||
extern void cortex_m3_build_reg_cache(target_t *target);
|
||||
|
||||
enum target_state cortex_m3_poll(target_t *target);
|
||||
int cortex_m3_halt(target_t *target);
|
||||
int cortex_m3_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution);
|
||||
int cortex_m3_step(struct target_s *target, int current, u32 address, int handle_breakpoints);
|
||||
|
||||
int cortex_m3_assert_reset(target_t *target);
|
||||
int cortex_m3_deassert_reset(target_t *target);
|
||||
int cortex_m3_soft_reset_halt(struct target_s *target);
|
||||
|
||||
int cortex_m3_read_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
|
||||
int cortex_m3_write_memory(struct target_s *target, u32 address, u32 size, u32 count, u8 *buffer);
|
||||
int cortex_m3_bulk_write_memory(target_t *target, u32 address, u32 count, u8 *buffer);
|
||||
|
||||
int cortex_m3_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
|
||||
int cortex_m3_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
|
||||
int cortex_m3_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
|
||||
int cortex_m3_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
|
||||
int cortex_m3_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
|
||||
int cortex_m3_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
|
||||
|
||||
extern int cortex_m3_register_commands(struct command_context_s *cmd_ctx);
|
||||
extern int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, int chain_pos, char *variant);
|
||||
|
||||
#endif /* CORTEX_M3_H */
|
||||
665
src/target/cortex_swjdp.c
Normal file
665
src/target/cortex_swjdp.c
Normal file
File diff suppressed because it is too large
Load Diff
130
src/target/cortex_swjdp.h
Normal file
130
src/target/cortex_swjdp.h
Normal file
@@ -0,0 +1,130 @@
|
||||
/***************************************************************************
|
||||
* Copyright (C) 2006 by Magnus Lundin *
|
||||
* lundin@mlu.mine.nu *
|
||||
* *
|
||||
* This program is free software; you can redistribute it and/or modify *
|
||||
* it under the terms of the GNU General Public License as published by *
|
||||
* the Free Software Foundation; either version 2 of the License, or *
|
||||
* (at your option) any later version. *
|
||||
* *
|
||||
* This program is distributed in the hope that it will be useful, *
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
|
||||
* GNU General Public License for more details. *
|
||||
* *
|
||||
* You should have received a copy of the GNU General Public License *
|
||||
* along with this program; if not, write to the *
|
||||
* Free Software Foundation, Inc., *
|
||||
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
|
||||
***************************************************************************/
|
||||
#ifndef CORTEX_SWJDP_H
|
||||
#define CORTEX_SWJDP_H
|
||||
|
||||
#include "target.h"
|
||||
#include "register.h"
|
||||
#include "arm_jtag.h"
|
||||
|
||||
#define SWJDP_IR_DPACC 0xA
|
||||
#define SWJDP_IR_APACC 0xB
|
||||
|
||||
#define DPAP_WRITE 0
|
||||
#define DPAP_READ 1
|
||||
#define DP_ZERO 0
|
||||
#define DP_CTRL_STAT 0x4
|
||||
#define DP_SELECT 0x8
|
||||
#define DP_RDBUFF 0xC
|
||||
|
||||
#define CORUNDETECT (1<<0)
|
||||
#define SSTICKYORUN (1<<1)
|
||||
#define SSTICKYERR (1<<5)
|
||||
#define CDBGRSTREQ (1<<26)
|
||||
#define CDBGRSTACK (1<<27)
|
||||
#define CDBGPWRUPREQ (1<<28)
|
||||
#define CDBGPWRUPACK (1<<29)
|
||||
#define CSYSPWRUPREQ (1<<30)
|
||||
#define CSYSPWRUPACK (1<<31)
|
||||
|
||||
|
||||
|
||||
#define AHBAP_CSW 0x00
|
||||
#define AHBAP_TAR 0x04
|
||||
#define AHBAP_DRW 0x0C
|
||||
#define AHBAP_BD0 0x10
|
||||
#define AHBAP_BD1 0x14
|
||||
#define AHBAP_BD2 0x18
|
||||
#define AHBAP_BD3 0x1C
|
||||
#define AHBAP_DBGROMA 0xF8
|
||||
#define AHBAP_IDR 0xFC
|
||||
|
||||
|
||||
#define CSW_8BIT 0
|
||||
#define CSW_16BIT 1
|
||||
#define CSW_32BIT 2
|
||||
|
||||
#define CSW_ADDRINC_MASK (3<<4)
|
||||
#define CSW_ADDRINC_OFF 0
|
||||
#define CSW_ADDRINC_SINGLE (1<<4)
|
||||
#define CSW_ADDRINC_PACKED (2<<4)
|
||||
#define CSW_HPROT (1<<25)
|
||||
#define CSW_MASTER_DEBUG (1<<29)
|
||||
#define CSW_DBGSWENABLE (1<<31)
|
||||
#define TRANS_MODE_NONE 0
|
||||
|
||||
/* Transaction waits for previous to complete */
|
||||
#define TRANS_MODE_ATOMIC 1
|
||||
/* Freerunning transactions with delays and overrun checking */
|
||||
#define TRANS_MODE_COMPOSITE 2
|
||||
|
||||
|
||||
typedef struct swjdp_reg_s
|
||||
{
|
||||
int addr;
|
||||
arm_jtag_t *jtag_info;
|
||||
} swjdp_reg_t;
|
||||
|
||||
typedef struct swjdp_common_s
|
||||
{
|
||||
arm_jtag_t *jtag_info;
|
||||
/* Control config */
|
||||
u32 dp_ctrl_stat;
|
||||
/* Register select cache */
|
||||
u32 dp_select_value;
|
||||
u32 ap_csw_value;
|
||||
u32 ap_tar_value;
|
||||
u8 prev_ack;
|
||||
/* information about current pending SWjDP-AHBAP transaction */
|
||||
u8 trans_mode;
|
||||
u8 trans_rw;
|
||||
u8 ack;
|
||||
u32 * trans_value;
|
||||
} swjdp_common_t;
|
||||
|
||||
/* Internal functions used in the module, partial transactions, use with caution */
|
||||
extern int swjdp_write_dpacc(swjdp_common_t *swjdp, u32 value, u8 reg_addr);
|
||||
//extern int swjdp_write_apacc(swjdp_common_t *swjdp, u32 value, u8 reg_addr);
|
||||
extern int swjdp_read_dpacc(swjdp_common_t *swjdp, u32 *value, u8 reg_addr);
|
||||
//extern int swjdp_read_apacc(swjdp_common_t *swjdp, u32 *value, u8 reg_addr);
|
||||
extern int ahbap_write_reg(swjdp_common_t *swjdp, u32 reg_addr, u8* out_value_buf);
|
||||
extern int ahbap_read_reg(swjdp_common_t *swjdp, u32 reg_addr, u8 *in_value_buf);
|
||||
|
||||
/* External interface, partial operations must be completed with swjdp_transaction_endcheck() */
|
||||
extern int ahbap_read_system_u32(swjdp_common_t *swjdp, u32 address, u32 *value);
|
||||
extern int ahbap_write_system_u32(swjdp_common_t *swjdp, u32 address, u32 value);
|
||||
extern int swjdp_transaction_endcheck(swjdp_common_t *swjdp);
|
||||
|
||||
|
||||
/* External interface, complete atomic operations */
|
||||
/* Host endian word transfer of single memory and system registers */
|
||||
extern int ahbap_read_system_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 *value);
|
||||
extern int ahbap_write_system_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 value);
|
||||
/* Target endian (u8*) buffer transfers of blocks of memory and system registers */
|
||||
extern int ahbap_read_block(swjdp_common_t *swjdp, u8 *buffer, int bytecount, u32 address);
|
||||
extern int ahbap_write_block(swjdp_common_t *swjdp, u8 *buffer, int bytecount, u32 address);
|
||||
/* Host endian word transfers of processor core registers */
|
||||
extern int ahbap_read_coreregister_u32(swjdp_common_t *swjdp, u32 *value, int regnum);
|
||||
extern int ahbap_write_coreregister_u32(swjdp_common_t *swjdp, u32 value, int regnum);
|
||||
|
||||
/* Initialisation of the debug system, power domains and registers */
|
||||
extern int ahbap_debugport_init(swjdp_common_t *swjdp);
|
||||
|
||||
#endif
|
||||
@@ -81,6 +81,7 @@ extern target_type_t arm920t_target;
|
||||
extern target_type_t arm966e_target;
|
||||
extern target_type_t arm926ejs_target;
|
||||
extern target_type_t xscale_target;
|
||||
extern target_type_t cortexm3_target;
|
||||
|
||||
target_type_t *target_types[] =
|
||||
{
|
||||
@@ -91,6 +92,7 @@ target_type_t *target_types[] =
|
||||
&arm966e_target,
|
||||
&arm926ejs_target,
|
||||
&xscale_target,
|
||||
&cortexm3_target,
|
||||
NULL,
|
||||
};
|
||||
|
||||
|
||||
Reference in New Issue
Block a user