# SPDX-License-Identifier: GPL-2.0-or-later

#
# Freescale i.MX6UltraLite series: 6UL 6ULL 6ULZ
#

if { [info exists CHIPNAME] } {
    set _CHIPNAME $CHIPNAME
} else {
    set _CHIPNAME imx6ul
}

# CoreSight Debug Access Port
if { [info exists DAP_TAPID] } {
    set _DAP_TAPID $DAP_TAPID
} else {
    set _DAP_TAPID 0x4ba00477
}

jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \
        -expected-id $_DAP_TAPID

# SDMA / no IDCODE
jtag newtap $_CHIPNAME sdma -irlen 4 -ircapture 0x00 -irmask 0x0f

# System JTAG Controller
set _SJC_TAPID_6UL  0x0891d01d
set _SJC_TAPID_6ULL 0x0891e01d
set _SJC_TAPID_6ULZ 0x1891e01d

# Allow external override of the first SJC TAPID
if { [info exists SJC_TAPID] } {
    set _SJC_TAPID $SJC_TAPID
} else {
    set _SJC_TAPID $_SJC_TAPID_6UL
}

jtag newtap $_CHIPNAME sjc -irlen 5 -ircapture 0x01 -irmask 0x1f \
        -ignore-version \
        -expected-id $_SJC_TAPID \
        -expected-id $_SJC_TAPID_6ULL \
        -expected-id $_SJC_TAPID_6ULZ \

# Create DAP
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu

# Main AHB bus
target create $_CHIPNAME.ahb mem_ap -dap $_CHIPNAME.dap -ap-num 0

# Cortex-A7 single core
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap -dbgbase 0x82130000
