mirror of
https://github.com/linux-msm/laptops-kernel.git
synced 2026-08-13 14:19:53 -07:00
Dmitry BaryshkovandHans Verkuil
3e0b205375
Follow the commitbfe1326573("venus: Fix for H265 decoding failure.") and increase H265D_MAX_SLICE following firmware requirements on that platform. Otherwise decoding of the H.265 streams fails with the "insufficient scratch_1 buffer size" from the firmware. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com> Reviewed-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> [bod: Fixed commit log withthe => with the] Fixes:e1f5d32608("media: iris: Add internal buffer calculation for HEVC and VP9 decoders") Cc: stable@vger.kernel.org Signed-off-by: Bryan O'Donoghue <bod@kernel.org> Signed-off-by: Hans Verkuil <hverkuil+cisco@kernel.org>
294 lines
9.6 KiB
C
294 lines
9.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef __IRIS_VPU_BUFFER_H__
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#define __IRIS_VPU_BUFFER_H__
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struct iris_inst;
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#define MIN_BUFFERS 4
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#define DMA_ALIGNMENT 256
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#define HFI_ALIGNMENT_4096 4096
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#define NUM_HW_PIC_BUF 32
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#define LCU_MAX_SIZE_PELS 64
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#define LCU_MIN_SIZE_PELS 16
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#define HDR10_HIST_EXTRADATA_SIZE (4 * 1024)
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#define SIZE_HW_PIC(size_per_buf) (NUM_HW_PIC_BUF * (size_per_buf))
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#define MAX_TILE_COLUMNS 32
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#define BIN_BUFFER_THRESHOLD (1280 * 736)
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#define VPP_CMD_MAX_SIZE (BIT(20))
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#define H264D_MAX_SLICE 1800
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#define SIZE_H264D_BUFTAB_T 256
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#define SIZE_H264D_BSE_CMD_PER_BUF (32 * 4)
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#define SIZE_H264D_VPP_CMD_PER_BUF 512
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#define NUM_SLIST_BUF_H264 (256 + 32)
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#define SIZE_SLIST_BUF_H264 512
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#define H264_DISPLAY_BUF_SIZE 3328
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#define H264_NUM_FRM_INFO 66
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#define H265_NUM_TILE_COL 32
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#define H265_NUM_TILE_ROW 128
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#define H265_NUM_TILE (H265_NUM_TILE_ROW * H265_NUM_TILE_COL + 1)
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#define SIZE_H265D_BSE_CMD_PER_BUF (16 * sizeof(u32))
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#define NUM_SLIST_BUF_H265 (80 + 20)
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#define SIZE_SLIST_BUF_H265 (BIT(10))
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#define H265_DISPLAY_BUF_SIZE (3072)
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#define H265_NUM_FRM_INFO (48)
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#define SIZE_ONE_SLICE_BUF 256
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#define VP9_NUM_FRAME_INFO_BUF 32
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#define VP9_NUM_PROBABILITY_TABLE_BUF (VP9_NUM_FRAME_INFO_BUF + 4)
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#define VP9_PROB_TABLE_SIZE (3840)
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#define VP9_FRAME_INFO_BUF_SIZE (6144)
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#define VP9_FRAME_INFO_BUF_SIZE_VPU4X (6400)
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#define BUFFER_ALIGNMENT_16_BYTES 16
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#define BUFFER_ALIGNMENT_32_BYTES 32
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#define BUFFER_ALIGNMENT_64_BYTES 64
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#define BUFFER_ALIGNMENT_256_BYTES 256
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#define BUFFER_ALIGNMENT_512_BYTES 512
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#define CCE_TILE_OFFSET_SIZE ALIGN(32 * 4 * 4, BUFFER_ALIGNMENT_32_BYTES)
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#define MAX_SUPERFRAME_HEADER_LEN (34)
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#define MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE 64
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#define MAX_FE_NBR_CTRL_LCU32_LINE_BUFFER_SIZE 64
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#define MAX_FE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE 64
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#define MAX_SE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE (128 / 8)
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#define MAX_SE_NBR_CTRL_LCU32_LINE_BUFFER_SIZE (128 / 8)
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#define VP9_UDC_HEADER_BUF_SIZE (3 * 128)
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#define SIZE_SEI_USERDATA 4096
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#define SIZE_DOLBY_RPU_METADATA (41 * 1024)
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#define H264_CABAC_HDR_RATIO_HD_TOT 1
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#define H264_CABAC_RES_RATIO_HD_TOT 3
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#define H265D_MAX_SLICE 3600
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#define SIZE_H265D_HW_PIC_T SIZE_H264D_HW_PIC_T
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#define H265_CABAC_HDR_RATIO_HD_TOT 2
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#define H265_CABAC_RES_RATIO_HD_TOT 2
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#define SIZE_H265D_VPP_CMD_PER_BUF (256)
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#define SIZE_THREE_DIMENSION_USERDATA 768
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#define SIZE_H265D_ARP 9728
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#define VPX_DECODER_FRAME_CONCURENCY_LVL (2)
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#define VPX_DECODER_FRAME_BIN_HDR_BUDGET 1
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#define VPX_DECODER_FRAME_BIN_RES_BUDGET 3
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#define VPX_DECODER_FRAME_BIN_DENOMINATOR 2
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#define VPX_DECODER_FRAME_BIN_RES_BUDGET_RATIO (3 / 2)
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#define SIZE_H264D_HW_PIC_T (BIT(11))
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#define FE_LFT_CTRL_LINE_NUMBERS 4
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#define FE_LFT_DB_DATA_LINE_NUMBERS 2
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#define FE_LFT_LR_DATA_LINE_NUMBERS 4
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#define FE_TOP_CTRL_LINE_NUMBERS 3
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#define FE_TOP_DATA_LUMA_LINE_NUMBERS 2
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#define FE_TOP_DATA_CHROMA_LINE_NUMBERS 3
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#define FE_SDC_DATA_PER_BLOCK 16
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#define SE_CTRL_DATA_PER_BLOCK 2020
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#define MAX_PE_NBR_DATA_LCU16_LINE_BUFFER_SIZE 96
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#define MAX_PE_NBR_DATA_LCU32_LINE_BUFFER_SIZE 192
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#define MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE 64
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#define MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE 16
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#define MAX_PE_NBR_DATA_LCU64_LINE_BUFFER_SIZE 384
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#define MAX_FE_NBR_DATA_LUMA_LINE_BUFFER_SIZE 640
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#define AV1_CABAC_HDR_RATIO_HD_TOT 2
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#define AV1_CABAC_RES_RATIO_HD_TOT 2
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#define AV1D_LCU_MAX_SIZE_PELS 128
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#define AV1D_LCU_MIN_SIZE_PELS 64
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#define AV1D_MAX_TILE_COLS 64
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#define MAX_PE_NBR_DATA_LCU32_LINE_BUFFER_SIZE 192
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#define MAX_PE_NBR_DATA_LCU16_LINE_BUFFER_SIZE 96
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#define AV1D_NUM_HW_PIC_BUF 16
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#define AV1D_NUM_FRAME_HEADERS 16
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#define SIZE_AV1D_SEQUENCE_HEADER 768
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#define SIZE_AV1D_METADATA 512
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#define SIZE_AV1D_FRAME_HEADER 1280
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#define SIZE_AV1D_TILE_OFFSET 65536
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#define SIZE_AV1D_QM 3328
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#define SIZE_AV1D_PROB_TABLE 22784
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#define SIZE_SLICE_CMD_BUFFER (ALIGN(20480, 256))
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#define SIZE_SPS_PPS_SLICE_HDR (2048 + 4096)
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#define SIZE_BSE_SLICE_CMD_BUF ((((8192 << 2) + 7) & (~7)) * 3)
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#define SIZE_LAMBDA_LUT (256 * 11)
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#define HFI_COL_FMT_NV12C_Y_TILE_HEIGHT (8)
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#define HFI_COL_FMT_NV12C_Y_TILE_WIDTH (32)
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#define HFI_COL_FMT_TP10C_Y_TILE_HEIGHT (4)
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#define HFI_COL_FMT_TP10C_Y_TILE_WIDTH (48)
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#define IRIS_METADATA_STRIDE_MULTIPLE 64
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#define IRIS_METADATA_HEIGHT_MULTIPLE 16
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#define HFI_BUFFER_ARP_ENC 204800
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#define LOG2_16 4
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#define LOG2_32 5
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#define LLB_UNIT_SIZE 16
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#define MAX_WIDTH 4096
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#define MAX_HEIGHT 2304
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#define NUM_MBS_4K (DIV_ROUND_UP(MAX_WIDTH, 16) * DIV_ROUND_UP(MAX_HEIGHT, 16))
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#define NUM_MBS_720P (((ALIGN(1280, 16)) >> 4) * ((ALIGN(736, 16)) >> 4))
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#define BITS_PER_PIX 16
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#define NUM_LINES_LUMA 10
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#define NUM_LINES_CHROMA 6
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#define AV1D_LCU_MAX_SIZE_PELS 128
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#define AV1D_LCU_MIN_SIZE_PELS 64
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#define AV1D_MAX_TILE_COLS 64
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#define BITS_PER_CTRL_PACK 128
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#define NUM_CTRL_PACK_LCU 10
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static inline u32 size_h264d_lb_fe_top_data(u32 frame_width)
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{
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return MAX_FE_NBR_DATA_LUMA_LINE_BUFFER_SIZE * ALIGN(frame_width, 16) * 3;
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}
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static inline u32 size_h264d_lb_fe_top_ctrl(u32 frame_width)
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{
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return MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE * DIV_ROUND_UP(frame_width, 16);
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}
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static inline u32 size_h264d_lb_fe_left_ctrl(u32 frame_height)
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{
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return MAX_FE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE * DIV_ROUND_UP(frame_height, 16);
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}
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static inline u32 size_h264d_lb_se_top_ctrl(u32 frame_width)
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{
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return MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE * DIV_ROUND_UP(frame_width, 16);
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}
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static inline u32 size_h264d_lb_se_left_ctrl(u32 frame_height)
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{
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return MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE * DIV_ROUND_UP(frame_height, 16);
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}
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static inline u32 size_h264d_lb_pe_top_data(u32 frame_width)
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{
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return MAX_PE_NBR_DATA_LCU64_LINE_BUFFER_SIZE * DIV_ROUND_UP(frame_width, 16);
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}
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static inline u32 size_h264d_lb_vsp_top(u32 frame_width)
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{
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return (DIV_ROUND_UP(frame_width, 16) << 7);
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}
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static inline u32 size_h264d_lb_recon_dma_metadata_wr(u32 frame_height)
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{
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return ALIGN(frame_height, 16) * 32;
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}
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static inline u32 size_h264d_qp(u32 frame_width, u32 frame_height)
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{
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return DIV_ROUND_UP(frame_width, 64) * DIV_ROUND_UP(frame_height, 64) * 128;
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}
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static inline u32 size_av1d_lb_fe_top_data(u32 frame_width, u32 frame_height)
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{
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return (ALIGN(frame_width, AV1D_LCU_MAX_SIZE_PELS) *
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((BITS_PER_PIX * NUM_LINES_LUMA) >> 3) +
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ALIGN(frame_width, AV1D_LCU_MAX_SIZE_PELS) / 2 *
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((BITS_PER_PIX * NUM_LINES_CHROMA) >> 3) * 2);
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}
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static inline u32 size_av1d_lb_fe_left_data(u32 frame_width, u32 frame_height)
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{
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return (32 * (ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) +
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ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) /
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AV1D_LCU_MIN_SIZE_PELS * 16) +
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16 * (ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / 2 +
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ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) /
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AV1D_LCU_MIN_SIZE_PELS * 8) * 2 +
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24 * (ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) +
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ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) /
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AV1D_LCU_MIN_SIZE_PELS * 16) +
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24 * (ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / 2 +
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ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) /
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AV1D_LCU_MIN_SIZE_PELS * 12) * 2 +
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24 * (ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) +
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ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) /
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AV1D_LCU_MIN_SIZE_PELS * 16) +
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16 * (ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) +
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ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) /
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AV1D_LCU_MIN_SIZE_PELS * 16) +
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16 * (ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / 2 +
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ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) /
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AV1D_LCU_MIN_SIZE_PELS * 12) * 2);
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}
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static inline u32 size_av1d_lb_fe_top_ctrl(u32 frame_width, u32 frame_height)
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{
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return (NUM_CTRL_PACK_LCU * ((frame_width + AV1D_LCU_MIN_SIZE_PELS - 1) /
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AV1D_LCU_MIN_SIZE_PELS) * BITS_PER_CTRL_PACK / 8);
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}
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static inline u32 size_av1d_lb_fe_left_ctrl(u32 frame_width, u32 frame_height)
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{
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return (16 * ((ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) / 16) +
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(ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) /
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AV1D_LCU_MIN_SIZE_PELS)) +
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3 * 16 * (ALIGN(frame_height, AV1D_LCU_MAX_SIZE_PELS) /
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AV1D_LCU_MIN_SIZE_PELS));
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}
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static inline u32 size_av1d_lb_se_top_ctrl(u32 frame_width, u32 frame_height)
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{
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return (((frame_width + 7) / 8) * MAX_SE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE);
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}
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static inline u32 size_av1d_lb_se_left_ctrl(u32 frame_width, u32 frame_height)
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{
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return (max(((frame_height + 15) / 16) *
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MAX_SE_NBR_CTRL_LCU16_LINE_BUFFER_SIZE,
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max(((frame_height + 31) / 32) *
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MAX_SE_NBR_CTRL_LCU32_LINE_BUFFER_SIZE,
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((frame_height + 63) / 64) *
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MAX_SE_NBR_CTRL_LCU64_LINE_BUFFER_SIZE)));
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}
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static inline u32 size_av1d_lb_pe_top_data(u32 frame_width, u32 frame_height)
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{
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return (max(((frame_width + 15) / 16) *
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MAX_PE_NBR_DATA_LCU16_LINE_BUFFER_SIZE,
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max(((frame_width + 31) / 32) *
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MAX_PE_NBR_DATA_LCU32_LINE_BUFFER_SIZE,
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((frame_width + 63) / 64) *
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MAX_PE_NBR_DATA_LCU64_LINE_BUFFER_SIZE)));
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}
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static inline u32 size_av1d_lb_vsp_top(u32 frame_width, u32 frame_height)
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{
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return (max(((frame_width + 63) / 64) * 1280,
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((frame_width + 127) / 128) * MAX_HEIGHT));
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}
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static inline u32 size_av1d_lb_recon_dma_metadata_wr(u32 frame_width,
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u32 frame_height)
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{
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return ((ALIGN(frame_height, 8) / (4 / 2)) * 64);
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}
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static inline u32 size_av1d_qp(u32 frame_width, u32 frame_height)
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{
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return size_h264d_qp(frame_width, frame_height);
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}
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u32 iris_vpu_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type);
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u32 iris_vpu33_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type);
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u32 iris_vpu4x_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer_type);
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int iris_vpu_buf_count(struct iris_inst *inst, enum iris_buffer_type buffer_type);
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#endif
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