mirror of
https://github.com/linux-msm/laptops-kernel.git
synced 2026-08-13 14:19:53 -07:00
Alexandre Courbot
1a8f58c5e1
Convert all FUSE registers to use the kernel's register macro and update the code accordingly. Reviewed-by: Eliot Courtney <ecourtney@nvidia.com> Reviewed-by: Gary Guo <gary@garyguo.net> Acked-by: Danilo Krummrich <dakr@kernel.org> Link: https://patch.msgid.link/20260325-b4-nova-register-v4-6-bdf172f0f6ca@nvidia.com Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
73 lines
1.9 KiB
Rust
73 lines
1.9 KiB
Rust
// SPDX-License-Identifier: GPL-2.0
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use kernel::{
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io::Io,
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num::Bounded,
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prelude::*, //
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};
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use crate::{
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driver::Bar0,
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fb::hal::FbHal,
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regs, //
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};
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use super::tu102::FLUSH_SYSMEM_ADDR_SHIFT;
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struct Ga100;
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pub(super) fn read_sysmem_flush_page_ga100(bar: &Bar0) -> u64 {
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u64::from(bar.read(regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR).adr_39_08()) << FLUSH_SYSMEM_ADDR_SHIFT
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| u64::from(bar.read(regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR_HI).adr_63_40())
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<< FLUSH_SYSMEM_ADDR_SHIFT_HI
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}
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pub(super) fn write_sysmem_flush_page_ga100(bar: &Bar0, addr: u64) {
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bar.write_reg(
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regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR_HI::zeroed().with_adr_63_40(
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Bounded::<u64, _>::from(addr)
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.shr::<FLUSH_SYSMEM_ADDR_SHIFT_HI, _>()
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.cast(),
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),
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);
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bar.write_reg(
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regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR::zeroed()
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// CAST: `as u32` is used on purpose since we want to strip the upper bits that have
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// been written to `NV_PFB_NISO_FLUSH_SYSMEM_ADDR_HI`.
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.with_adr_39_08((addr >> FLUSH_SYSMEM_ADDR_SHIFT) as u32),
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);
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}
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pub(super) fn display_enabled_ga100(bar: &Bar0) -> bool {
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!bar.read(regs::ga100::NV_FUSE_STATUS_OPT_DISPLAY)
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.display_disabled()
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}
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/// Shift applied to the sysmem address before it is written into
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/// `NV_PFB_NISO_FLUSH_SYSMEM_ADDR_HI`,
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const FLUSH_SYSMEM_ADDR_SHIFT_HI: u32 = 40;
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impl FbHal for Ga100 {
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fn read_sysmem_flush_page(&self, bar: &Bar0) -> u64 {
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read_sysmem_flush_page_ga100(bar)
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}
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fn write_sysmem_flush_page(&self, bar: &Bar0, addr: u64) -> Result {
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write_sysmem_flush_page_ga100(bar, addr);
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Ok(())
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}
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fn supports_display(&self, bar: &Bar0) -> bool {
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display_enabled_ga100(bar)
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}
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fn vidmem_size(&self, bar: &Bar0) -> u64 {
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super::tu102::vidmem_size_gp102(bar)
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}
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}
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const GA100: Ga100 = Ga100;
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pub(super) const GA100_HAL: &dyn FbHal = &GA100;
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