Rodrigo SiqueiraandAlex Deucher d68ba530ec Documentation/gpu: Expand generic block information ...

This commit expands the overall explanation about AMD GPU IPs by adding
more details about their interconnection. Note that this commit includes
a diagram that provides additional information.

v2: fix up TMR - Trusted Memory Region

Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian König <christian.koenig@amd.com>
Cc: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2025-12-08 13:56:32 -05:00

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config_example.svg

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dc_pipeline_overview.svg

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dc-arch-overview.svg

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dc-components.svg

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dc-debug.rst

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dc-glossary.rst

Documentation/gpu: Expand generic block information

2025-12-08 13:56:32 -05:00

dcn2_cm_drm_current.svg

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dcn3_cm_drm_current.svg

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dcn-blocks.rst

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dcn-overview.rst

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display-contributing.rst

Documentation/amdgpu: fix 'in the amdgfx' formulation

2025-07-28 16:40:32 -04:00

display-manager.rst

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global_sync_vblank.svg

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index.rst

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mpo-cursor.svg

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mpo-overview.rst

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multi-display-hdcp-mpo-less-pipe-ex.svg

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multi-display-hdcp-mpo.svg

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pipeline_4k_no_split.svg

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pipeline_4k_split.svg

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programming-model-dcn.rst

docs: gpu: amdgpu: Fix spelling in amdgpu documentation

2025-08-27 13:57:48 -04:00

single-display-mpo-multi-video.svg

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single-display-mpo.svg

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trace-groups-table.csv

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