81 Commits
Author SHA1 Message Date
Arnd Bergmann 6333f2974c Merge tag 'riscv-sophgo-soc-for-v6.16' of https://github.com/sophgo/linux into soc/drivers
RISC-V SoC for v6.16

Sophgo:

Add support for SG2044 TOP syscon device. The SG2044 TOP
device provide PLL clock function in its area.

Add RTC support for CV1800 series SoC. The device
is called RTC, but contains control registers of other
HW blocks in its address space, most notably of
Power-on-Reset (PoR) module, DW8051 IP (MCU core),
accompanying SRAM, hence putting it in SoC subsystem.

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>

* tag 'riscv-sophgo-soc-for-v6.16' of https://github.com/sophgo/linux:
  soc: sophgo: cv1800: rtcsys: New driver (handling RTC only)
  dt-bindings: soc: sophgo: add RTC support for Sophgo CV1800 series
  soc: sophgo: sg2044: Add support for SG2044 TOP syscon device

Link: https://lore.kernel.org/r/MA0P287MB2262B041A26A0F5EAD1E296CFE91A@MA0P287MB2262.INDP287.PROD.OUTLOOK.COM
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2025-05-21 19:25:08 +02:00
Inochi Amaoto f18198c0de soc: sophgo: sg2044: Add support for SG2044 TOP syscon device
The SG2044 TOP device provide PLL clock function in its area.
Add a mfd definition for it.

Link: https://lore.kernel.org/r/20250418020325.421257-3-inochiama@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
2025-05-07 07:48:34 +08:00
Alexey CharkovandKrzysztof Kozlowski 96f94587d7 soc: Add VIA/WonderMedia SoC identification driver
Add a small SOC bus driver to parse the chip ID and revision made
available on VIA/WonderMedia SoCs via their system configuration
controller's SCC_ID register.

This is intended to select appropriate sets of on-chip device quirks
at runtime, as it has been found that even within the same SoC
version there can be register-incompatible differences, such as
with the SDMMC controller on WM8505 rev. A0-A1 vs. rev. A2.

The list of SoC versions is compiled from various vendor source dumps
and not all of them have corresponding mainline driver support.
Some of them also have been seen with varying on-chip markings while
sharing the same hardware chip ID's (as is the case with e.g. WM8850
vs. WM8950). In such cases the selection of names to use here among
those seen in various source dumps and chip markings was arbitrary.

Suggested by Krzysztof at [1] - thanks a lot!

[1] https://lore.kernel.org/all/14de236b-e2a7-4bde-986d-1e5ffddd01b4@kernel.org/

Signed-off-by: Alexey Charkov <alchark@gmail.com>
Link: https://lore.kernel.org/r/20250503-wmt-soc-driver-v3-2-2daa9056fa10@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
2025-05-04 19:27:01 +02:00
Linus Torvalds 075dbe9f6e Merge tag 'soc-ep93xx-dt-6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC update from Arnd Bergmann:
 "Convert ep93xx to devicetree

  This concludes a long journey towards replacing the old board files
  with devictree description on the Cirrus Logic EP93xx platform.

  Nikita Shubin has been working on this for a long time, for details
  see the last post on

    https://lore.kernel.org/lkml/20240909-ep93xx-v12-0-e86ab2423d4b@maquefel.me/"

* tag 'soc-ep93xx-dt-6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (47 commits)
  dt-bindings: gpio: ep9301: Add missing "#interrupt-cells" to examples
  MAINTAINERS: Update EP93XX ARM ARCHITECTURE maintainer
  soc: ep93xx: drop reference to removed EP93XX_SOC_COMMON config
  net: cirrus: use u8 for addr to calm down sparse
  dmaengine: cirrus: use snprintf() to calm down gcc 13.3.0
  dmaengine: ep93xx: Fix a NULL vs IS_ERR() check in probe()
  pinctrl: ep93xx: Fix raster pins typo
  spi: ep93xx: update kerneldoc comments for ep93xx_spi
  clk: ep93xx: Fix off by one in ep93xx_div_recalc_rate()
  clk: ep93xx: add module license
  dmaengine: cirrus: remove platform code
  ASoC: cirrus: edb93xx: Delete driver
  ARM: ep93xx: soc: drop defines
  ARM: ep93xx: delete all boardfiles
  ata: pata_ep93xx: remove legacy pinctrl use
  pwm: ep93xx: drop legacy pinctrl
  ARM: ep93xx: DT for the Cirrus ep93xx SoC platforms
  ARM: dts: ep93xx: Add EDB9302 DT
  ARM: dts: ep93xx: add ts7250 board
  ARM: dts: add Cirrus EP93XX SoC .dtsi
  ...
2024-09-26 12:00:25 -07:00
Nikita ShubinandArnd Bergmann 6eab0ce6e1 soc: Add SoC driver for Cirrus ep93xx
Add an SoC driver for the ep93xx. Currently there is only one thing
not fitting into any other framework, and that is the swlock setting.

Used for clock settings, pinctrl and restart.

Signed-off-by: Nikita Shubin <nikita.shubin@maquefel.me>
Tested-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Alexander Sverdlin <alexander.sverdlin@gmail.com>
Acked-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2024-09-12 14:33:10 +00:00
Krzysztof KozlowskiandLinus Walleij 2f05726171 soc: versatile: enable compile testing
Enable compile testing for broader build coverage.  None of the drivers
use anything from "asm", so code should build everywhere.
CONFIG_PLAT_VERSATILE is being selected by driver dependencies
(CONFIG_ARCH_INTEGRATOR and CONFIG_ARCH_REALVIEW), so directory can be
always added to Makefile targets without impacting other configurations.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/20240825-soc-dev-fixes-v1-4-ff4b35abed83@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-08-30 15:40:11 +02:00
Yangyu ChenandConor Dooley 915fb0e31c soc: canaan: Deprecate SOC_CANAAN and use SOC_CANAAN_K210 for K210
Since SOC_FOO should be deprecated from patch [1], and cleanup for other
SoCs is already in the mailing list [2,3,4], we remove the use of
SOC_CANAAN and use ARCH_CANAAN for SoCs vendored by Canaan instead from now
on. Thus, we should also change the Makefile here to use ARCH_CANAAN.

Then, since we have introduced SOC_CANAAN_K210 for K210-specific drivers,
we should replace its drivers depends on SOC_CANAAN_K210 and default select
when it has the symbol SOC_CANAAN_K210.

[1] https://lore.kernel.org/linux-riscv/20221121221414.109965-1-conor@kernel.org/
[2] https://lore.kernel.org/linux-riscv/20240305-praying-clad-c4fbcaa7ed0a@spud/
[3] https://lore.kernel.org/linux-riscv/20240305-fled-undrilled-41dc0c46bb29@spud/
[4] https://lore.kernel.org/linux-riscv/20240305-stress-earflap-d7ddb8655a4d@spud/

Signed-off-by: Yangyu Chen <cyy@cyyself.name>
Acked-by: Guo Ren <guoren@kernel.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2024-04-05 16:42:50 +01:00
Conor Dooley 971f128bb2 soc: sifive: shunt ccache driver to drivers/cache
Move the ccache driver over to drivers/cache, out of the drivers/soc
dumping ground, to this new collection point for cache controller
drivers.

Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Tested-by: Samuel Holland <samuel.holland@sifive.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-11-22 11:49:25 +00:00
Arnd Bergmann bb2974ffff Merge tag 'hisi-drivers-for-6.6' of https://github.com/hisilicon/linux-hisi into soc/drivers
HiSilicon driver updates for v6.6

- Add HCCS driver for HiSilicon Kunpeng SoC and document the sysfs description

* tag 'hisi-drivers-for-6.6' of https://github.com/hisilicon/linux-hisi:
  doc: soc: hisilicon: Add Kunpeng HCCS driver documentation
  soc: hisilicon: add sysfs entry to query information of HCCS
  soc: hisilicon: Support HCCS driver on Kunpeng SoC

Link: https://lore.kernel.org/r/64D605DE.2070303@hisilicon.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-08-12 12:10:46 +02:00
Huisong LiandWei Xu 886bdf9c88 soc: hisilicon: Support HCCS driver on Kunpeng SoC
The Huawei Cache Coherence System (HCCS) is a multi-chip interconnection
bus protocol. This driver is aimed to support some features about HCCS on
Kunpeng SoC, like, querying the health status of HCCS.

This patch adds the probing of HCCS driver, and obtains all HCCS port
information by the dimension of chip and die on platform.

Signed-off-by: Huisong Li <lihuisong@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2023-08-08 12:36:29 +00:00
Arnd Bergmann 7ed363cd8d genpd: move owl-sps-helper.c from drivers/soc
Moving only one of the two files in drivers/soc/actions to drivers/genpd
caused a link failure in allmodconfig, as drivers/genpd is entered
for compile testing, but drivers/soc/actions accidentally got skipped:

x86_64-linux-gnu-ld: vmlinux.o: in function `owl_sps_set_power':
owl-sps.c:(.text+0x16e259d): undefined reference to `owl_sps_set_pg'

Move the other one as well to allow build testing to work correctly.

Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-07-26 14:41:01 +02:00
Arnd Bergmann 00eb53b08c soc: starfive: remove stale Makefile entry
After the only starfive driver was moved out to the genpd subsystem, we get
a build failure:

scripts/Makefile.build:41: drivers/soc/starfive/Makefile: No such file or directory

Fixes: f3fb16291f ("soc: starfive: Move the power-domain driver to the genpd dir")
Reported=by: kernel test robot <lkp@intel.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-07-26 14:40:53 +02:00
Jonathan NeuschäferandArnd Bergmann 7dbb4a38bf soc: nuvoton: Add SoC info driver for WPCM450
Add a SoC information driver for Nuvoton WPCM450 SoCs. It provides
information such as the SoC revision.

Usage example:

  # grep . /sys/devices/soc0/*
  /sys/devices/soc0/family:Nuvoton NPCM
  /sys/devices/soc0/revision:A3
  /sys/devices/soc0/soc_id:WPCM450

Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Paul Menzel <pmenzel@molgen.mpg.de>
Link: https://lore.kernel.org/r/20221031223926.241641-1-j.neuschaefer@gmx.net
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://lore.kernel.org/r/20230201051717.1005938-1-joel@jms.id.au
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2023-02-01 17:11:36 +01:00
Conor Dooley f3460326e3 Merge patch series "JH7110 PMU Support"
Walker Chen <walker.chen@starfivetech.com> says:

Add the PMU (Power Management Unit) controller driver for the
StarFive JH7110 SoC. In order to meet low power requirements, PMU is
designed for including multiple PM domains that can be used for power
gating of selected IP blocks for power saving by reduced leakage
current.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-01-20 21:57:00 +00:00
Walker ChenandConor Dooley 08b9a94e86 soc: starfive: Add StarFive JH71XX pmu driver
Add pmu driver for the StarFive JH71XX SoC.

As the power domains provider, the Power Management Unit (PMU) is
designed for including multiple PM domains that can be used for power
gating of selected IP blocks for power saving by reduced leakage
current. It accepts software encourage command to switch the power mode
of SoC.

Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2023-01-20 21:55:59 +00:00
Emil Renner BerthingandConor Dooley 6635e91648 soc: sifive: ccache: Add StarFive JH7110 support
This adds support for the StarFive JH7110 SoC which also
features this SiFive cache controller.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
2022-12-26 22:50:15 +00:00
Yinbo ZhuandArnd Bergmann b82621ac84 soc: loongson: add GUTS driver for loongson-2 platforms
The global utilities block controls PCIE device enabling, alternate
function selection for multiplexed signals, consistency of HDA, USB
and PCIE, configuration of memory controller, rtc controller, lio
controller, and clock control.

This patch adds a driver to manage and access global utilities block
for LoongArch architecture Loongson-2 SoCs. Initially only reading SVR
and registering soc device are supported. Other guts accesses, such
as reading firmware configuration by default, should eventually be
added into this driver as well.

Signed-off-by: Yinbo Zhu <zhuyinbo@loongson.cn>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-11-14 16:01:32 +01:00
Hitomi HasegawaandArnd Bergmann 64f89dfaa4 soc: fujitsu: Add A64FX diagnostic interrupt driver
Register the NMI/IRQ corresponding to the A64FX's device definition
dedicated to diagnostic interrupts, so that when this interrupt is
sent using the BMC, it causes a panic. This can be used to obtain
a kernel dump.

Signed-off-by: Hitomi Hasegawa <hasegawa-hitomi@fujitsu.com>
Link: https://lore.kernel.org/r/20220520074119.3574753-2-hasegawa-hitomi@fujitsu.com'
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-07-18 13:37:08 +02:00
Linus Torvalds 96479c0980 Merge tag 'arm-multiplatform-5.19-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull more ARM multiplatform updates from Arnd Bergmann:
 "The second part of the multiplatform changes now converts the
  Intel/Marvell PXA platform along with the rest. The patches went
  through several rebases before the merge window as bugs were found, so
  they remained separate.

  This has to touch a lot of drivers, in particular the touchscreen,
  pcmcia, sound and clk bits, to detach the driver files from the
  platform and board specific header files"

* tag 'arm-multiplatform-5.19-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (48 commits)
  ARM: pxa/mmp: remove traces of plat-pxa
  ARM: pxa: convert to multiplatform
  ARM: pxa/sa1100: move I/O space to PCI_IOBASE
  ARM: pxa: remove support for MTD_XIP
  ARM: pxa: move mach/*.h to mach-pxa/
  ARM: PXA: fix multi-cpu build of xsc3
  ARM: pxa: move plat-pxa to drivers/soc/
  ARM: mmp: rename pxa_register_device
  ARM: mmp: remove tavorevb board support
  ARM: pxa: remove unused mach/bitfield.h
  ARM: pxa: move clk register definitions to driver
  ARM: pxa: move smemc register access from clk to platform
  cpufreq: pxa3: move clk register access to clk driver
  ARM: pxa: remove get_clk_frequency_khz()
  ARM: pxa: pcmcia: move smemc configuration back to arch
  ASoC: pxa: i2s: use normal MMIO accessors
  ASoC: pxa: ac97: use normal MMIO accessors
  ASoC: pxa: use pdev resource for FIFO regs
  Input: wm97xx - get rid of irq_enable method in wm97xx_mach_ops
  Input: wm97xx - switch to using threaded IRQ
  ...
2022-06-02 15:23:54 -07:00
Arnd Bergmann d4a3b44233 Merge tag 'v5.19-rockchip-drivers1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into arm/drivers
Powerdomain fixes and improvements, some GRF compatible properties
and a rk3566 GRF clocksource default setup.

* tag 'v5.19-rockchip-drivers1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  soc: rockchip: Fix compile-testing SoC drivers
  soc: rockchip: power-domain: Replace dsb() with smb()
  soc: rockchip: Clean up Kconfig whitespace
  soc: rockchip: set dwc3 clock for rk3566
  dt-bindings: soc: rockchip: add rk3566-pipe-grf compatible
  soc: rockchip: pm_domains: Fix typo in comment
  dt-bindings: soc: rockchip: add naneng combo phy register compatible

Link: https://lore.kernel.org/r/3998951.tdWV9SEqCh@phil
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-05-13 11:33:41 +02:00
Arnd Bergmann 64dbc4dd7a ARM: pxa: move plat-pxa to drivers/soc/
There are two drivers in arch/arm/plat-pxa: mfp and ssp. Both
of them should ideally not be needed at all, as there are
proper subsystems to replace them.

OTOH, they are self-contained and can simply be normal
SoC drivers, so move them over there to eliminate one more
of the plat-* directories.

Acked-by: Robert Jarzmik <robert.jarzmik@free.fr> (mach-pxa)
Acked-by: Lubomir Rintel <lkundrak@v3.sk> (mach-mmp)
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2022-05-07 22:56:16 +02:00
Sven Peter cbb0f00131 soc: apple: Always include Makefile
We want to allow the code inside drivers/soc/apple to be compiled with
COMPILE_TEST but this will currently result in linking errors because
ARCH_APPLE is not set and make will never recurse into
drivers/soc/apple.
Let's just unconditionally recurse into apple/ since all drivers
in there are guarded by config options anyways.

Signed-off-by: Sven Peter <sven@svenpeter.dev>
2022-05-01 16:55:05 +02:00
Brian NorrisandHeiko Stuebner add9f6f30e soc: rockchip: Fix compile-testing SoC drivers
Similar to commit 7f94b69ece ("ARM: ixp4xx: fix compile-testing soc
drivers").

drivers/soc/rockchip/Kconfig makes plenty of provision for configuring
drivers either for ARCH_ROCKCHIP or for COMPILE_TEST. But
drivers/soc/Makefile pulls the rug out from under us, by refusing to
build anything if we specified COMPILE_TEST but not ARCH_ROCKCHIP.

Currently, I'm not aware of anything that breaks without this patch, but
it certainly makes for confusing builds (CONFIG_ROCKCHIP_PM_DOMAINS=y,
but we didn't actually compile the driver?) and leaves room for future
error (I have pending patches that break confusingly with COMPILE_TEST=y
even though their Kconfig dependencies seem correct [1]).

Defer to drivers/soc/rockchip/{Makefile,Kconfig} to do the right thing.

[1] e.g.,
https://lore.kernel.org/linux-rockchip/20220405184816.RFC.2.I2d73b403944f0b8b5871a77585b73f31ccc62999@changeid/
[RFC PATCH 2/2] PM / devfreq: rk3399_dmc: Block PMU during transitions

Signed-off-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Link: https://lore.kernel.org/r/20220425184503.v3.3.Id5f16dec920f620120c0a143a97a12e16d401760@changeid
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2022-04-30 15:06:14 +02:00
Conor DooleyandNicolas Ferre d0054a470c soc: add microchip polarfire soc system controller
This driver provides an interface for other drivers to access the
functions of the system controller on the Microchip PolarFire SoC.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20220217101349.2374873-2-conor.dooley@microchip.com
2022-02-25 12:50:59 +01:00
Hector Martin 6df9d38f91 soc: apple: Add driver for Apple PMGR power state controls
Implements genpd and reset providers for downstream devices. Each
instance of the driver binds to a single register and represents a
single SoC power domain.

The driver does not currently implement all features (clockgate-only
state, misc flags), but we declare the respective registers for
documentation purposes. These features will be added as they become
useful for downstream devices.

This also creates the apple/soc tree and Kconfig submenu.

Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Hector Martin <marcan@marcan.st>
2021-12-07 13:13:13 +09:00