Simplifies allocation slightly by removing a kcalloc call and using
struct_size.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
[linusw@kernel.org: Add in count variable and use __counted_by()]
Signed-off-by: Linus Walleij <linusw@kernel.org>
Make the padctl functions a bit simpler by returning void instead of
always '0'. The callers - phy init/exit - still need to return 0, but
these are smaller function without if/branching.
Acked-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Linus Walleij <linusw@kernel.org>
Add csus_mux for further use as the csus clock parent, similar to how the
cdev1 and cdev2 muxes are utilized. Additionally, constify the cdev parent
name lists to resolve checkpatch warnings.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Tegra devices have an 'sfsel' bit field that determines whether a pin
operates in SFIO (Special Function I/O) or GPIO mode. Currently,
tegra_pinctrl_gpio_disable_free() sets this bit when releasing a GPIO.
However, tegra_pinctrl_set_mux() can be called independently in certain
code paths where gpio_disable_free() is not invoked. In such cases, failing
to set the SFIO mode could lead to incorrect pin configurations, resulting
in functional issues for peripherals relying on SFIO.
This patch ensures that whenever set_mux() is called, the SFIO mode is
correctly set in the Mux Register if the 'sfsel' bit is present. This
prevents situations where the pin remains in GPIO mode despite being
configured for SFIO use.
Fixes: 971dac7123 ("pinctrl: add a driver for NVIDIA Tegra")
Signed-off-by: Prathamesh Shete <pshete@nvidia.com>
Link: https://lore.kernel.org/20250306050542.16335-1-pshete@nvidia.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Each pin can be configured as a Special Function IO (SFIO) or GPIO,
where the SFIO enables the pin to operate in alternative modes such as
I2C, SPI, etc.
The current implementation sets all the pins back to SFIO mode
even if they were initially in GPIO mode. This can cause glitches
on the pins when pinctrl_gpio_free() is called.
Avoid these undesired glitches by storing the pin's SFIO/GPIO
state on GPIO request and restoring it on GPIO free.
Signed-off-by: Prathamesh Shete <pshete@nvidia.com>
Link: https://lore.kernel.org/20250305104939.15168-2-pshete@nvidia.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The SFIO/GPIO select bit is a crucial part of Tegra's pin multiplexing
system:
- When set to 1, the pin operates in SFIO mode, controlled by the
pin's assigned special function.
- When set to 0, the pin operates as a general-purpose GPIO.
This SFIO/GPIO select bit that is set for a given pin is not displayed,
adding the support to retrieve this information from the
pinmux set for each pin.
Signed-off-by: Prathamesh Shete <pshete@nvidia.com>
Link: https://lore.kernel.org/20241217153249.5712-1-pshete@nvidia.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The function that a pin is muxed to can be read from the top-level
pinctrl-maps debugfs file. However, this only reflects the values that
were specified in device tree, so they will only show deviations from
the hardware default setting. Display the current pinmux setting in the
per-controller pinconf-groups debugfs file along with the rest of the
per-pin configuration settings.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Tested-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
Link: https://lore.kernel.org/r/20230929122101.466266-1-thierry.reding@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Pull pin control updates from Linus Walleij:
"No pin control core changes this time.
New drivers:
- Realtek RTD family pin control driver and RTD1619B, RTD1319D and
RTD1315E subdrivers
- Nuvoton NPCM8xx combined pin control and GPIO driver
- Amlogic T7 pin control driver
- Renesas RZ/G3S pin control driver
Improvements:
- A number of additional UART groups added to the Mediatek MT7981
driver
- MPM pin maps added for Qualcomm MSM8996, SM6115, SM6125 and SDM660
- Extra GPIO banks for the Sunxi H616
- MLSP I2C6 function support in Qualcomm MSM8226
- Some __counted_by() annotations for dynamic arrays
- Ongoing work to make remove() return void
- LSBC groups and functions in the Renesas R8A7778"
* tag 'pinctrl-v6.7-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (110 commits)
pinctrl: Use device_get_match_data()
dt-bindings: pinctrl: qcom,sa8775p-tlmm: add missing wakeup-parent
dt-bindings: pinctrl: nuvoton,npcm845: Add missing additionalProperties on gpio child nodes
dt-bindings: pinctrl: brcm: Ensure all child node properties are documented
pinctrl: renesas: rzn1: Convert to platform remove callback returning void
pinctrl: renesas: rzg2l: Add RZ/G3S support
dt-bindings: pinctrl: renesas: Document RZ/G3S SoC
pinctrl: renesas: rzg2l: Add support for different DS values on different groups
pinctrl: renesas: rzg2l: Move DS and OI to SoC-specific configuration
pinctrl: renesas: rzg2l: Adapt function number for RZ/G3S
pinctrl: renesas: rzg2l: Adapt for different SD/PWPR register offsets
pinctrl: renesas: rzg2l: Index all registers based on port offset
pinctrl: renesas: rzg2l: Add validation of GPIO pin in rzg2l_gpio_request()
pinctrl: renesas: r8a7778: Add LBSC pins, groups, and functions
pinctrl: intel: fetch community only when we need it
pinctrl: cherryview: reduce scope of PIN_CONFIG_BIAS_HIGH_IMPEDANCE case
pinctrl: cherryview: Convert to platform remove callback returning void
pinctrl: sprd-sc9860: Convert to platform remove callback returning void
pinctrl: qcom/msm: Convert to platform remove callback returning void
pinctrl: qcom/lpi: Convert to platform remove callback returning void
...
intel-pinctrl for v6.6-1
* New library driver for Intel MID to deduplicate code (Raag Jadav)
* Reuse common functions from pinctrl-intel to reduce the code (Raag Jadav)
* Move most of the exported functions to the PINCTRL_INTEL namespace
* Make use of pm_ptr() in Bay Trail and Lynxpoint drivers
* Introduce DEFINE_NOIRQ_DEV_PM_OPS() helper and use it in a few drivers
* Consolidata ACPI dependency in Kconfig (Raag Jadav)
* Fix address_space_handler() argument in Cherryview driver (Raag Jadav)
* Optinmize byt_pin_config_set() to avoid IO in error cases (Raag Jadav)
The following is an automated git shortlog grouped by driver:
at91:
- Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper
baytrail:
- Make use of pm_ptr()
- reuse common functions from pinctrl-intel
- consolidate common mask operation
cherryview:
- fix address_space_handler() argument
- Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper
- reuse common functions from pinctrl-intel
intel:
- consolidate ACPI dependency
- Switch to use exported namespace
- export common pinctrl functions
lynxpoint:
- Make use of pm_ptr()
- reuse common functions from pinctrl-intel
Merge patch series:
- Merge patch series "Introduce Intel Tangier pinctrl driver"
- Merge patch series "Reuse common functions from pinctrl-intel"
merrifield:
- Adapt to Intel Tangier driver
moorefield:
- Adapt to Intel Tangier driver
mvebu:
- Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper
pm:
- Introduce DEFINE_NOIRQ_DEV_PM_OPS() helper
renesas:
- Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper
tangier:
- Introduce Intel Tangier driver
tegra:
- Switch to use DEFINE_NOIRQ_DEV_PM_OPS() helper
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The DT of_device.h and of_platform.h date back to the separate
of_platform_bus_type before it as merged into the regular platform bus.
As part of that merge prepping Arm DT support 13 years ago, they
"temporarily" include each other. They also include platform_device.h
and of.h. As a result, there's a pretty much random mix of those include
files used throughout the tree. In order to detangle these headers and
replace the implicit includes with struct declarations, users need to
explicitly include the correct includes.
Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Damien Le Moal <dlemoal@kernel.org>
Acked-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230714174901.4062397-1-robh@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The drv_reg field is initialized both in the DRV_PINGROUP_ENTRY_N/DRV_PINGROUP_ENTRY_Y
macros and in DRV_PINGROUP_Y. Since each pingroup expands both macros, the are
always duplicate and turning on -Woverride-init (which is disabled by default)
causes a huge amount of warnings like:
drivers/pinctrl/tegra/pinctrl-tegra234.c:1384:27: error: initialized field overwritten [-Werror=override-init]
1384 | #define DRV_PINGROUP_Y(r) ((r))
| ^
drivers/pinctrl/tegra/pinctrl-tegra234.c:1397:28: note: in expansion of macro 'DRV_PINGROUP_Y'
1397 | .drv_reg = DRV_PINGROUP_Y(r), \
| ^~~~~~~~~~~~~~
drivers/pinctrl/tegra/pinctrl-tegra234.c:1447:49: note: in expansion of macro 'DRV_PINGROUP_ENTRY_Y'
1447 | #define drive_soc_gpio08_pb0 DRV_PINGROUP_ENTRY_Y(0x500c, 12, 5, 20, 5, -1, -1, -1, -1, 0)
| ^~~~~~~~~~~~~~~~~~~~
...
Remove the intialization that is never used here.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20230616161603.1127687-1-arnd@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The function table is filled with group information based on other
instance-specific data at runtime. However, the function table can be
shared between multiple instances, causing the ->probe() function for
one instance to overwrite the table of a previously probed instance.
Fix this by sharing only the function names and allocating a separate
function table for each instance.
Fixes: 5a00473607 ("pinctrl: tegra: Separate Tegra194 instances")
Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://lore.kernel.org/r/20230530105308.1292852-1-thierry.reding@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Tegra194 has two separate instances of the pin controller, one called
AON (in the always-on domain) and another called "main". Instead of
treating them as a single pin controller, split them up into two
separate controllers. Doing so allows the mapping between the pinmux
and GPIO controllers to be trivial identity mappings and more cleanly
separates the AON from the main IP blocks.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://lore.kernel.org/r/20221104142345.1562750-4-thierry.reding@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
