558 Commits
Author SHA1 Message Date
Linus Torvalds 32a92f8c89 Convert more 'alloc_obj' cases to default GFP_KERNEL arguments
This converts some of the visually simpler cases that have been split
over multiple lines.  I only did the ones that are easy to verify the
resulting diff by having just that final GFP_KERNEL argument on the next
line.

Somebody should probably do a proper coccinelle script for this, but for
me the trivial script actually resulted in an assertion failure in the
middle of the script.  I probably had made it a bit _too_ trivial.

So after fighting that far a while I decided to just do some of the
syntactically simpler cases with variations of the previous 'sed'
scripts.

The more syntactically complex multi-line cases would mostly really want
whitespace cleanup anyway.

Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2026-02-21 20:03:00 -08:00
Linus Torvalds bf4afc53b7 Convert 'alloc_obj' family to use the new default GFP_KERNEL argument
This was done entirely with mindless brute force, using

    git grep -l '\<k[vmz]*alloc_objs*(.*, GFP_KERNEL)' |
        xargs sed -i 's/\(alloc_objs*(.*\), GFP_KERNEL)/\1)/'

to convert the new alloc_obj() users that had a simple GFP_KERNEL
argument to just drop that argument.

Note that due to the extreme simplicity of the scripting, any slightly
more complex cases spread over multiple lines would not be triggered:
they definitely exist, but this covers the vast bulk of the cases, and
the resulting diff is also then easier to check automatically.

For the same reason the 'flex' versions will be done as a separate
conversion.

Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2026-02-21 17:09:51 -08:00
Kees Cook 69050f8d6d treewide: Replace kmalloc with kmalloc_obj for non-scalar types
This is the result of running the Coccinelle script from
scripts/coccinelle/api/kmalloc_objs.cocci. The script is designed to
avoid scalar types (which need careful case-by-case checking), and
instead replace kmalloc-family calls that allocate struct or union
object instances:

Single allocations:	kmalloc(sizeof(TYPE), ...)
are replaced with:	kmalloc_obj(TYPE, ...)

Array allocations:	kmalloc_array(COUNT, sizeof(TYPE), ...)
are replaced with:	kmalloc_objs(TYPE, COUNT, ...)

Flex array allocations:	kmalloc(struct_size(PTR, FAM, COUNT), ...)
are replaced with:	kmalloc_flex(*PTR, FAM, COUNT, ...)

(where TYPE may also be *VAR)

The resulting allocations no longer return "void *", instead returning
"TYPE *".

Signed-off-by: Kees Cook <kees@kernel.org>
2026-02-21 01:02:28 -08:00
Stephen Boyd 16c3c4e288 Merge branches 'clk-renesas', 'clk-cleanup', 'clk-spacemit' and 'clk-tegra' into clk-next
* clk-renesas: (25 commits)
  dt-bindings: clk: rs9: Fix DIF pattern match
  clk: rs9: Convert to DEFINE_SIMPLE_DEV_PM_OPS()
  clk: rs9: Reserve 8 struct clk_hw slots for for 9FGV0841
  clk: renesas: Add missing log message terminators
  clk: renesas: rzg2l: Remove DSI clock rate restrictions
  clk: renesas: rzv2h: Deassert reset on assert timeout
  clk: renesas: rzg2l: Deassert reset on assert timeout
  clk: renesas: cpg-mssr: Unlock before reset verification
  clk: renesas: r9a09g056: Add entries for CANFD
  clk: renesas: r9a09g057: Add entries for CANFD
  clk: renesas: r9a09g077: Add CANFD clocks
  clk: renesas: cpg-mssr: Handle RZ/T2H register layout in PM callbacks
  dt-bindings: clock: renesas,r9a09g077/87: Add PCLKCAN ID
  clk: renesas: cpg-mssr: Simplify pointer math in cpg_rzt2h_mstp_read()
  clk: renesas: r9a09g056: Add clock and reset entries for TSU
  clk: renesas: r9a09g057: Add entries for RSCIs
  clk: renesas: r9a09g056: Add entries for RSCIs
  clk: renesas: r9a09g056: Add entries for the RSPIs
  clk: renesas: r9a09g056: Add entries for ICU
  clk: renesas: r9a09g056: Add entries for the DMACs
  ...

* clk-cleanup:
  clk: Disable KUNIT_UML_PCI
  clk: zynqmp: pll: Fix zynqmp_clk_divider_determine_rate kerneldoc
  clk: zynqmp: divider: Fix zynqmp_clk_divider_determine_rate kerneldoc
  clk: tegra: tegra124-emc: fix device leak on set_rate()
  clk: Annotate #else and #endif
  clk: Merge prepare and unprepare sections
  clk: Move clk_{save,restore}_context() to COMMON_CLK section
  clk: clk-apple-nco: Add "apple,t8103-nco" compatible
  clk: versatile: impd1: Simplify with scoped for each OF child loop
  clk: scpi: Simplify with scoped for each OF child loop
  clk: lmk04832: Simplify with scoped for each OF child loop

* clk-spacemit:
  clk: spacemit: k3: add the clock tree
  clk: spacemit: k3: extract common header
  clk: spacemit: ccu_pll: add plla type clock
  clk: spacemit: ccu_mix: add inverted enable gate clock
  dt-bindings: soc: spacemit: k3: add clock support
  clk: spacemit: add platform SoC prefix to reset name
  clk: spacemit: extract common ccu functions
  reset: spacemit: fix auxiliary device id
  clk: spacemit: prepare common ccu header
  clk: spacemit: Hide common clock driver from user controller
  clk: spacemit: Respect Kconfig setting when building modules

* clk-tegra:
  clk: tegra30: Add CSI pad clock gates
  clk: tegra: Set CSUS as vi_sensor's gate for Tegra20, Tegra30 and Tegra114
  clk: tegra20: Reparent dsi clock to pll_d_out0
  clk: tegra: tegra124-emc: Simplify with scoped for each OF child loop
  clk: tegra: Adjust callbacks in tegra_clock_pm
  clk: tegra: tegra124-emc: Fix potential memory leak in tegra124_clk_register_emc()
2026-02-14 10:23:04 -08:00
Johan HovoldandStephen Boyd da61439c63 clk: tegra: tegra124-emc: fix device leak on set_rate()
Make sure to drop the reference taken when looking up the EMC device and
its driver data on first set_rate().

Note that holding a reference to a device does not prevent its driver
data from going away so there is no point in keeping the reference.

Fixes: 2db04f16b5 ("clk: tegra: Add EMC clock driver")
Fixes: 6d6ef58c24 ("clk: tegra: tegra124-emc: Fix missing put_device() call in emc_ensure_emc_driver")
Cc: stable@vger.kernel.org	# 4.2: 6d6ef58c24
Cc: Mikko Perttunen <mperttunen@nvidia.com>
Cc: Miaoqian Lin <linmq006@gmail.com>
Signed-off-by: Johan Hovold <johan@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2026-01-22 17:40:29 -08:00
Svyatoslav RyhelandThierry Reding e897e86711 clk: tegra30: Add CSI pad clock gates
Tegra30 has CSI pad bits in both PLLD and PLLD2 clocks that are required
for the correct work of the CSI block. Add CSI pad A and pad B clock gates
with PLLD/PLLD2 parents, respectively. Add a plld2 spinlock, like one plld
uses, to prevent simultaneous access since both the PLLDx and CSIx_PAD
clocks use the same registers

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Tested-by: Luca Ceresoli <luca.ceresoli@bootlin.com> # tegra20, parallel camera
Signed-off-by: Thierry Reding <treding@nvidia.com>
2026-01-17 01:33:18 +01:00
Svyatoslav RyhelandThierry Reding a6d8abf5b4 clk: tegra: Set CSUS as vi_sensor's gate for Tegra20, Tegra30 and Tegra114
The CSUS clock is a clock gate for the output clock signal primarily
sourced from the VI_SENSOR clock. This clock signal is used as an input
MCLK clock for cameras.

Unlike later Tegra SoCs, the Tegra 20 can change its CSUS parent, which is
why csus_mux is added in a similar way to how CDEV1 and CDEV2 are handled.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Tested-by: Luca Ceresoli <luca.ceresoli@bootlin.com> # tegra20, parallel camera
Signed-off-by: Thierry Reding <treding@nvidia.com>
2026-01-17 01:32:18 +01:00
Svyatoslav RyhelandThierry Reding f521678d19 clk: tegra20: Reparent dsi clock to pll_d_out0
Reparent DSI clock to PLLD_OUT0 instead of directly descend from PLLD.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2026-01-17 01:17:42 +01:00
Krzysztof KozlowskiandThierry Reding 2ea99dade5 clk: tegra: tegra124-emc: Simplify with scoped for each OF child loop
Use scoped for-each loop when iterating over device nodes to make code a
bit simpler.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2026-01-17 01:13:46 +01:00
Rafael J. WysockiandThierry Reding 1acce02756 clk: tegra: Adjust callbacks in tegra_clock_pm
System suspend and resume callbacks run after the core has bumped
up the runtime PM usage counters of all devices, so these callbacks
need not worry about runtime PM reference counting.

Accordingly, to eliminate useless overhead related to runtime PM
usage counter manipulation, set the suspend callback pointer in
tegra_clock_pm to a wrapper around pm_runtime_resume() called
tegra_clock_suspend() and do not set the resume callback in it at all.

This will also facilitate a planned change of the pm_runtime_put()
return type to void in the future.

Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2026-01-17 01:13:24 +01:00
Haoxiang LiandThierry Reding fce0d0bd9c clk: tegra: tegra124-emc: Fix potential memory leak in tegra124_clk_register_emc()
If clk_register() fails, call kfree to release "tegra".

Fixes: 2db04f16b5 ("clk: tegra: Add EMC clock driver")
Cc: stable@vger.kernel.org
Signed-off-by: Haoxiang Li <lihaoxiang@isrc.iscas.ac.cn>
Reviewed-by: Brian Masney <bmasney@redhat.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2026-01-16 19:36:04 +01:00
Thierry Reding a97fbc3ee3 syscore: Pass context data to callbacks
Several drivers can benefit from registering per-instance data along
with the syscore operations. To achieve this, move the modifiable fields
out of the syscore_ops structure and into a separate struct syscore that
can be registered with the framework. Add a void * driver data field for
drivers to store contextual data that will be passed to the syscore ops.

Acked-by: Rafael J. Wysocki (Intel) <rafael@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-11-14 10:01:52 +01:00
Stephen Boyd 112104e2b7 Merge branch 'clk-determine-rate' into clk-next
* clk-determine-rate: (120 commits)
  clk: microchip: core: remove duplicate roclk_determine_rate()
  clk: nxp: Fix pll0 rate check condition in LPC18xx CGU driver
  clk: scmi: migrate round_rate() to determine_rate()
  clk: ti: fapll: convert from round_rate() to determine_rate()
  clk: ti: dra7-atl: convert from round_rate() to determine_rate()
  clk: ti: divider: convert from round_rate() to determine_rate()
  clk: ti: composite: convert from round_rate() to determine_rate()
  clk: ti: dpll: convert from round_rate() to determine_rate()
  clk: ti: dpll: change error return from ~0 to -EINVAL
  clk: ti: dpll: remove round_rate() in favor of determine_rate()
  clk: tegra: tegra210-emc: convert from round_rate() to determine_rate()
  clk: tegra: super: convert from round_rate() to determine_rate()
  clk: tegra: pll: convert from round_rate() to determine_rate()
  clk: tegra: periph: divider: convert from round_rate() to determine_rate()
  clk: tegra: divider: convert from round_rate() to determine_rate()
  clk: tegra: audio-sync: convert from round_rate() to determine_rate()
  clk: fixed-factor: drop round_rate() clk ops
  clk: divider: remove round_rate() in favor of determine_rate()
  clk: visconti: pll: convert from round_rate() to determine_rate()
  clk: versatile: vexpress-osc: convert from round_rate() to determine_rate()
  ...
2025-10-06 13:02:50 -05:00
Stephen Boyd 3aae991cc2 Merge branches 'clk-samsung', 'clk-tegra' and 'clk-amlogic' into clk-next
* clk-samsung:
  clk: s2mps11: add support for S2MPG10 PMIC clock
  dt-bindings: clock: samsung,s2mps11: add s2mpg10
  clk: samsung: exynos990: Add PERIC0 and PERIC1 clock support
  dt-bindings: clock: exynos990: Add PERIC0 and PERIC1 clock units
  clk: samsung: exynos990: Add missing USB clock registers to HSI0
  clk: samsung: exynos990: Add LHS_ACEL gate clock for HSI0 and update CLK_NR_TOP
  dt-bindings: clock: exynos990: Add LHS_ACEL clock ID for HSI0 block
  clk: samsung: artpec-8: Add initial clock support for ARTPEC-8 SoC
  clk: samsung: Add clock PLL support for ARTPEC-8 SoC
  dt-bindings: clock: Add ARTPEC-8 clock controller
  clk: samsung: exynos990: Add DPU_BUS and CMUREF mux/div and update CLKS_NR_TOP
  dt-bindings: clock: exynos990: Extend clocks IDs
  clk: samsung: exynos990: Replace bogus divs with fixed-factor clocks
  clk: samsung: exynos990: Fix CMU_TOP mux/div bit widths
  clk: samsung: exynos990: Use PLL_CON0 for PLL parent muxes
  clk: samsung: pll: convert from round_rate() to determine_rate()
  clk: samsung: cpu: convert from round_rate() to determine_rate()
  clk: samsung: fsd: Add clk id for PCLK and PLL in CAM_CSI block
  dt-bindings: clock: Add CAM_CSI clock macro for FSD

* clk-tegra:
  clk: tegra: dfll: Add CVB tables for Tegra114
  clk: tegra: Add DFLL DVCO reset control for Tegra114
  dt-bindings: arm: tegra: Add ASUS TF101G and SL101
  dt-bindings: reset: Add Tegra114 CAR header
  dt-bindings: arm: tegra: Add Xiaomi Mi Pad (A0101)
  dt-bindings: clock: tegra30: Add IDs for CSI pad clocks
  dt-bindings: display: tegra: Move avdd-dsi-csi-supply from VI to CSI
  dt-bindings: i2c: nvidia,tegra20-i2c: Document Tegra264 I2C

* clk-amlogic:
  clk: amlogic: fix recent code refactoring
  clk: amlogic: c3-peripherals: use helper for basic composite clocks
  clk: amlogic: align s4 and c3 pwm clock descriptions
  clk: amlogic: add composite clock helpers
  clk: amlogic: use the common pclk definition
  clk: amlogic: introduce a common pclk definition
  clk: amlogic: pclk explicitly use CLK_IGNORE_UNUSED
  clk: amlogic: drop CLK_SET_RATE_PARENT from peripheral clocks
  clk: amlogic: move PCLK definition to clkc-utils
  clk: amlogic: aoclk: use clkc-utils syscon probe
  clk: amlogic: use probe helper in mmio based controllers
  clk: amlogic: add probe helper for mmio based controllers
  clk: amlogic: drop meson-clkcee
  clk: amlogic: naming consistency alignment
2025-10-06 12:56:46 -05:00
Fedor PchelkinandStephen Boyd 49ef649110 clk: tegra: do not overallocate memory for bpmp clocks
struct tegra_bpmp::clocks is a pointer to a dynamically allocated array
of pointers to 'struct tegra_bpmp_clk'.

But the size of the allocated area is calculated like it is an array
containing actual 'struct tegra_bpmp_clk' objects - it's not true, there
are just pointers.

Found by Linux Verification Center (linuxtesting.org) with Svace static
analysis tool.

Fixes: 2db12b15c6 ("clk: tegra: Register clocks from root to leaf")
Signed-off-by: Fedor Pchelkin <pchelkin@ispras.ru>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-09-21 13:09:12 -07:00
Svyatoslav RyhelandThierry Reding 5aba939e80 clk: tegra: dfll: Add CVB tables for Tegra114
Extend the Tegra124 DFLL driver to include configuration settings
required for Tegra114 compatibility.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
[treding@nvidia.com: Use TEGRA210 instead of T210]
Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-09-14 08:23:28 +02:00
Svyatoslav RyhelandThierry Reding 8e7bd526e8 clk: tegra: Add DFLL DVCO reset control for Tegra114
The DVCO present in the DFLL IP block has a separate reset line, exposed
via the CAR IP block.  This reset line is asserted upon SoC reset.
Unless something (such as the DFLL driver) deasserts this line, the DVCO
will not oscillate, although reads and writes to the DFLL IP block will
complete.

Based on a3c83ff2 ("clk: tegra: Add DFLL DVCO reset control for Tegra124")

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-09-11 18:29:48 +02:00
Svyatoslav RyhelandThierry Reding fc02f529a8 dt-bindings: clock: tegra30: Add IDs for CSI pad clocks
Tegra30 has CSI pad clock enable bits embedded into PLLD/PLLD2 registers.
Add ids for these clocks. Additionally, move TEGRA30_CLK_CLK_MAX into
clk-tegra30 source.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2025-09-11 18:03:10 +02:00
Brian Masney 3b9877b162 clk: tegra: tegra210-emc: convert from round_rate() to determine_rate()
The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series.

Signed-off-by: Brian Masney <bmasney@redhat.com>
2025-09-08 12:50:51 -04:00
Brian Masney 13e19a074b clk: tegra: super: convert from round_rate() to determine_rate()
The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate().

Note that this change also requires the same migration to
drivers/clk/tegra/clk-divider.c.

Signed-off-by: Brian Masney <bmasney@redhat.com>
2025-09-08 12:50:47 -04:00
Brian Masney 65227c79e0 clk: tegra: pll: convert from round_rate() to determine_rate()
The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series.

Signed-off-by: Brian Masney <bmasney@redhat.com>
2025-09-08 12:50:44 -04:00
Brian Masney e3d1744baa clk: tegra: periph: divider: convert from round_rate() to determine_rate()
The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate().

Note that this change also requires the same migration to
drivers/clk/tegra/clk-divider.c.

Signed-off-by: Brian Masney <bmasney@redhat.com>
2025-09-08 12:50:41 -04:00
Brian Masney 3891c3c700 clk: tegra: divider: convert from round_rate() to determine_rate()
The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series.

Signed-off-by: Brian Masney <bmasney@redhat.com>
2025-09-08 12:50:38 -04:00
Brian Masney 706000971c clk: tegra: audio-sync: convert from round_rate() to determine_rate()
The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series.

Signed-off-by: Brian Masney <bmasney@redhat.com>
2025-09-08 12:50:34 -04:00
Liao YuanhongandStephen Boyd a1e1c10878 clk: tegra: Remove redundant semicolons
Remove unnecessary semicolons.

Signed-off-by: Liao Yuanhong <liaoyuanhong@vivo.com>
Link: https://lore.kernel.org/r/20250813094003.552308-1-liaoyuanhong@vivo.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-08-14 13:25:25 -07:00