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drm/amd/display: Fix implicit narrowing conversion warnings

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[Why]
Multiple display source files contain implicit narrowing
conversions when assigning wider integer types (int, uint32_t)
to narrower fields (uint8_t, uint16_t) at hardware register,
protocol, and storage boundaries. These conversions are
intentional but undocumented, and accompanying runtime assertions
add noise without providing compile-time safety.

[How]
Add explicit casts at all intentional narrowing boundaries across
display source files. Use narrower loop variable types where loop
bounds guarantee safe range. Remove runtime assertions paired
with narrowing casts, inline single-use intermediate variables,
and revert block scopes and braces introduced solely to contain
those assertions.

Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Gaghik Khachatrian <gaghik.khachatrian@amd.com>
Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Gaghik Khachatrian
2026-04-17 15:41:15 -04:00
committed by Alex Deucher
parent 866f716b17
commit f4cdbb5d54
107 changed files with 733 additions and 704 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/gpu/drm/amd/display/dc/basics/custom_float.c
+1 -1
View File
@@ -90,7 +90,7 @@ static bool build_custom_float(struct fixed31_32 value,
dc_fixpt_lt(dc_fixpt_one, mantiss))
mantiss = dc_fixpt_zero;
else
mantiss = dc_fixpt_shl(mantiss, format->mantissa_bits);
mantiss = dc_fixpt_shl(mantiss, (unsigned char)format->mantissa_bits);
*mantissa = dc_fixpt_floor(mantiss);
drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
+1 -1
View File
@@ -3077,7 +3077,7 @@ bool bw_calcs(struct dc_context *ctx,
}
calculate_bandwidth(dceip, vbios, data);
yclk_lvl = data->y_clk_level;
yclk_lvl = (uint8_t)data->y_clk_level;
calcs_output->nbp_state_change_enable =
data->nbp_state_change_enable;
drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
+3 -3
View File
@@ -803,8 +803,8 @@ static enum bp_result bios_parser_dac_load_detection(
uint32_t bios_0_scratch;
uint32_t device_id_mask = 0;
bp_params.device_id = get_support_mask_for_device_id(
DEVICE_TYPE_CRT, engine_id == ENGINE_ID_DACB ? 2 : 1);
bp_params.device_id = (uint16_t)get_support_mask_for_device_id(
DEVICE_TYPE_CRT, engine_id == ENGINE_ID_DACB ? 2 : 1);
if (bp_params.device_id == ATOM_DEVICE_CRT1_SUPPORT)
device_id_mask = ATOM_S0_CRT1_MASK;
@@ -1382,7 +1382,7 @@ static enum bp_result get_embedded_panel_info_v1_2(
info->ss_id = lvds->ucSS_Id;
{
uint8_t rr = le16_to_cpu(lvds->usSupportedRefreshRate);
uint16_t rr = le16_to_cpu(lvds->usSupportedRefreshRate);
/* Get minimum supported refresh rate*/
if (SUPPORTED_LCD_REFRESHRATE_30Hz & rr)
info->supported_rr.REFRESH_RATE_30HZ = 1;
drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+10 -10
View File
@@ -157,7 +157,7 @@ static uint8_t bios_parser_get_connectors_number(struct dc_bios *dcb)
break;
}
return count;
return (uint8_t)count;
}
static struct graphics_object_id bios_parser_get_connector_id(
@@ -401,7 +401,7 @@ static enum bp_result bios_parser_get_i2c_info(struct dc_bios *dcb,
return BP_RESULT_BADINPUT;
if (id.type == OBJECT_TYPE_GENERIC) {
dummy_record.i2c_id = id.id;
dummy_record.i2c_id = (uint8_t)id.id;
if (get_gpio_i2c_info(bp, &dummy_record, info) == BP_RESULT_OK)
return BP_RESULT_OK;
@@ -1228,7 +1228,7 @@ static enum bp_result get_disp_caps_v4_1(
if (!disp_cntl_tbl)
return BP_RESULT_BADBIOSTABLE;
*dce_caps = disp_cntl_tbl->display_caps;
*dce_caps = (uint8_t)disp_cntl_tbl->display_caps;
return result;
}
@@ -1252,7 +1252,7 @@ static enum bp_result get_disp_caps_v4_2(
if (!disp_cntl_tbl)
return BP_RESULT_BADBIOSTABLE;
*dce_caps = disp_cntl_tbl->display_caps;
*dce_caps = (uint8_t)disp_cntl_tbl->display_caps;
return result;
}
@@ -1276,7 +1276,7 @@ static enum bp_result get_disp_caps_v4_3(
if (!disp_cntl_tbl)
return BP_RESULT_BADBIOSTABLE;
*dce_caps = disp_cntl_tbl->display_caps;
*dce_caps = (uint8_t)disp_cntl_tbl->display_caps;
return result;
}
@@ -1300,7 +1300,7 @@ static enum bp_result get_disp_caps_v4_4(
if (!disp_cntl_tbl)
return BP_RESULT_BADBIOSTABLE;
*dce_caps = disp_cntl_tbl->display_caps;
*dce_caps = (uint8_t)disp_cntl_tbl->display_caps;
return result;
}
@@ -1324,7 +1324,7 @@ static enum bp_result get_disp_caps_v4_5(
if (!disp_cntl_tbl)
return BP_RESULT_BADBIOSTABLE;
*dce_caps = disp_cntl_tbl->display_caps;
*dce_caps = (uint8_t)disp_cntl_tbl->display_caps;
return result;
}
@@ -2585,7 +2585,7 @@ static enum bp_result get_integrated_info_v11(
info->ext_disp_conn_info.path[i].channel_mapping.raw =
info_v11->extdispconninfo.path[i].channelmapping;
info->ext_disp_conn_info.path[i].caps =
le16_to_cpu(info_v11->extdispconninfo.path[i].caps);
(unsigned short)le16_to_cpu(info_v11->extdispconninfo.path[i].caps);
}
info->ext_disp_conn_info.checksum =
info_v11->extdispconninfo.checksum;
@@ -2790,7 +2790,7 @@ static enum bp_result get_integrated_info_v2_1(
info->ext_disp_conn_info.path[i].channel_mapping.raw =
info_v2_1->extdispconninfo.path[i].channelmapping;
info->ext_disp_conn_info.path[i].caps =
le16_to_cpu(info_v2_1->extdispconninfo.path[i].caps);
(unsigned short)le16_to_cpu(info_v2_1->extdispconninfo.path[i].caps);
}
info->ext_disp_conn_info.checksum =
@@ -2954,7 +2954,7 @@ static enum bp_result get_integrated_info_v2_2(
info->ext_disp_conn_info.path[i].channel_mapping.raw =
info_v2_2->extdispconninfo.path[i].channelmapping;
info->ext_disp_conn_info.path[i].caps =
le16_to_cpu(info_v2_2->extdispconninfo.path[i].caps);
(unsigned short)le16_to_cpu(info_v2_2->extdispconninfo.path[i].caps);
}
info->ext_disp_conn_info.checksum =
drivers/gpu/drm/amd/display/dc/bios/command_table.c
+6 -6
View File
@@ -1521,8 +1521,8 @@ static enum bp_result adjust_display_pll_v2(
if (pixel_clock_10KHz_in != 0) {
bp_params->adjusted_pixel_clock =
div_u64(pixel_clk * pixel_clk_10_khz_out,
pixel_clock_10KHz_in);
(uint32_t)div_u64(pixel_clk * pixel_clk_10_khz_out,
pixel_clock_10KHz_in);
} else {
bp_params->adjusted_pixel_clock = 0;
BREAK_TO_DEBUGGER();
@@ -1571,8 +1571,8 @@ static enum bp_result adjust_display_pll_v3(
if (pixel_clk_10_kHz_in != 0) {
bp_params->adjusted_pixel_clock =
div_u64(pixel_clk * pixel_clk_10_khz_out,
pixel_clk_10_kHz_in);
(uint32_t)div_u64(pixel_clk * pixel_clk_10_khz_out,
pixel_clk_10_kHz_in);
} else {
bp_params->adjusted_pixel_clock = 0;
BREAK_TO_DEBUGGER();
@@ -2662,8 +2662,8 @@ static enum bp_result set_dce_clock_v2_1(
!cmd->dc_clock_type_to_atom(bp_params->clock_type, &atom_clock_type))
return BP_RESULT_BADINPUT;
params.asParam.ucDCEClkSrc = atom_pll_id;
params.asParam.ucDCEClkType = atom_clock_type;
params.asParam.ucDCEClkSrc = (uint8_t)atom_pll_id;
params.asParam.ucDCEClkType = (uint8_t)atom_clock_type;
if (bp_params->clock_type == DCECLOCK_TYPE_DPREFCLK) {
if (bp_params->flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK)
drivers/gpu/drm/amd/display/dc/bios/command_table2.c
+2 -2
View File
@@ -929,8 +929,8 @@ static enum bp_result set_dce_clock_v2_1(
&atom_clock_type))
return BP_RESULT_BADINPUT;
params.param.dceclksrc = atom_pll_id;
params.param.dceclktype = atom_clock_type;
params.param.dceclksrc = (uint8_t)atom_pll_id;
params.param.dceclktype = (uint8_t)atom_clock_type;
if (bp_params->clock_type == DCECLOCK_TYPE_DPREFCLK) {
if (bp_params->flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK)
drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
+3 -3
View File
@@ -127,7 +127,7 @@ void dce110_fill_display_configs(
pp_display_cfg->avail_mclk_switch_time_us = dce110_get_min_vblank_time_us(context);
pp_display_cfg->disp_clk_khz = dc->clk_mgr->clks.dispclk_khz;
pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0;
pp_display_cfg->crtc_index = dc->res_pool->res_cap->num_timing_generator;
pp_display_cfg->crtc_index = (uint8_t)dc->res_pool->res_cap->num_timing_generator;
for (j = 0; j < context->stream_count; j++) {
int k;
@@ -151,7 +151,7 @@ void dce110_fill_display_configs(
num_cfgs++;
cfg->signal = pipe_ctx->stream->signal;
cfg->pipe_idx = pipe_ctx->stream_res.tg->inst;
cfg->pipe_idx = (uint8_t)pipe_ctx->stream_res.tg->inst;
cfg->src_height = stream->src.height;
cfg->src_width = stream->src.width;
cfg->ddi_channel_mapping =
@@ -189,7 +189,7 @@ void dce110_fill_display_configs(
pp_display_cfg->line_time_in_us = 0;
}
pp_display_cfg->display_count = num_cfgs;
pp_display_cfg->display_count = (uint8_t)num_cfgs;
}
void dce11_pplib_apply_display_requirements(
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+6 -3
View File
@@ -462,8 +462,10 @@ static void build_watermark_ranges(struct clk_bw_params *bw_params, struct pp_sm
if (!bw_params->wm_table.entries[i].valid)
continue;
ranges->reader_wm_sets[num_valid_sets].wm_inst = bw_params->wm_table.entries[i].wm_inst;
ranges->reader_wm_sets[num_valid_sets].wm_type = bw_params->wm_table.entries[i].wm_type;
ranges->reader_wm_sets[num_valid_sets].wm_inst =
(uint8_t)bw_params->wm_table.entries[i].wm_inst;
ranges->reader_wm_sets[num_valid_sets].wm_type =
(uint8_t)bw_params->wm_table.entries[i].wm_type;
/* We will not select WM based on fclk, so leave it as unconstrained */
ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
ranges->reader_wm_sets[num_valid_sets].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
@@ -476,7 +478,8 @@ static void build_watermark_ranges(struct clk_bw_params *bw_params, struct pp_sm
/* add 1 to make it non-overlapping with next lvl */
ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz = bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
}
ranges->reader_wm_sets[num_valid_sets].max_drain_clk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
ranges->reader_wm_sets[num_valid_sets].max_drain_clk_mhz =
(uint16_t)bw_params->clk_table.entries[i].dcfclk_mhz;
} else {
/* unconstrained for memory retraining */
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
+21 -18
View File
@@ -78,9 +78,9 @@ static const struct clk_mgr_mask clk_mgr_mask = {
/* Query SMU for all clock states for a particular clock */
static void dcn3_init_single_clock(struct clk_mgr_internal *clk_mgr, uint32_t clk, unsigned int *entry_0, unsigned int *num_levels)
static void dcn3_init_single_clock(struct clk_mgr_internal *clk_mgr, uint32_t clk, unsigned int *entry_0, uint8_t *num_levels)
{
unsigned int i;
uint8_t i;
char *entry_i = (char *)entry_0;
uint32_t ret = dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, 0xFF);
@@ -109,7 +109,7 @@ static void dcn3_build_wm_range_table(struct clk_mgr_internal *clk_mgr)
void dcn3_init_clocks(struct clk_mgr *clk_mgr_base)
{
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
unsigned int num_levels;
uint8_t num_levels;
memset(&(clk_mgr_base->clks), 0, sizeof(struct dc_clocks));
clk_mgr_base->clks.p_state_change_support = true;
@@ -234,7 +234,7 @@ static void dcn3_update_clocks(struct clk_mgr *clk_mgr_base,
if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DCEFCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz));
dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DCEFCLK, (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz));
}
if (should_set_clock(safe_to_lower, new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
@@ -265,10 +265,11 @@ static void dcn3_update_clocks(struct clk_mgr *clk_mgr_base,
if (dc->clk_mgr->dc_mode_softmax_enabled &&
new_clocks->dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)
dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
dc->clk_mgr->bw_params->dc_mode_softmax_memclk);
(uint16_t)dc->clk_mgr->bw_params->dc_mode_softmax_memclk);
else
dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz);
(uint16_t)clk_mgr_base->bw_params->clk_table.entries[
clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz);
}
}
@@ -281,20 +282,20 @@ static void dcn3_update_clocks(struct clk_mgr *clk_mgr_base,
/* set UCLK to requested value if P-State switching is supported, or to re-enable P-State switching */
if (clk_mgr_base->clks.p_state_change_support &&
(update_uclk || !clk_mgr_base->clks.prev_p_state_change_support))
dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr_base->clks.dppclk_khz)) {
if (clk_mgr_base->clks.dppclk_khz > new_clocks->dppclk_khz)
dpp_clock_lowered = true;
clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_PIXCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dppclk_khz));
dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_PIXCLK, (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dppclk_khz));
update_dppclk = true;
}
if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dispclk_khz));
dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK, (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dispclk_khz));
update_dispclk = true;
}
@@ -323,7 +324,7 @@ static void dcn3_update_clocks(struct clk_mgr *clk_mgr_base,
static void dcn3_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
{
unsigned int i;
uint8_t i;
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
WatermarksExternal_t *table = (WatermarksExternal_t *) clk_mgr->wm_range_table;
@@ -363,13 +364,14 @@ static void dcn3_set_hard_min_memclk(struct clk_mgr *clk_mgr_base, bool current_
if (current_mode) {
if (clk_mgr_base->clks.p_state_change_support)
dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
(uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
else
dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz);
(uint16_t)clk_mgr_base->bw_params->clk_table.entries[
clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz);
} else {
dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz);
(uint16_t)clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz);
}
}
@@ -382,7 +384,8 @@ static void dcn3_set_hard_max_memclk(struct clk_mgr *clk_mgr_base)
return;
dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK,
clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz);
(uint16_t)clk_mgr_base->bw_params->clk_table.entries[
clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz);
}
static void dcn3_set_max_memclk(struct clk_mgr *clk_mgr_base, unsigned int memclk_mhz)
@@ -392,7 +395,7 @@ static void dcn3_set_max_memclk(struct clk_mgr *clk_mgr_base, unsigned int memcl
if (!clk_mgr->smu_present)
return;
dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, memclk_mhz);
dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, (uint16_t)memclk_mhz);
}
static void dcn3_set_min_memclk(struct clk_mgr *clk_mgr_base, unsigned int memclk_mhz)
{
@@ -400,14 +403,14 @@ static void dcn3_set_min_memclk(struct clk_mgr *clk_mgr_base, unsigned int memcl
if (!clk_mgr->smu_present)
return;
dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, memclk_mhz);
dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, (uint16_t)memclk_mhz);
}
/* Get current memclk states, update bounding box */
static void dcn3_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base)
{
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
unsigned int num_levels;
uint8_t num_levels;
if (!clk_mgr->smu_present)
return;
@@ -480,7 +483,7 @@ static void dcn30_notify_link_rate_change(struct clk_mgr *clk_mgr_base, struct d
if (max_phyclk_req != clk_mgr_base->clks.phyclk_khz) {
clk_mgr_base->clks.phyclk_khz = max_phyclk_req;
dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_PHYCLK, khz_to_mhz_ceil(clk_mgr_base->clks.phyclk_khz));
dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_PHYCLK, (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.phyclk_khz));
}
}
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
+7 -4
View File
@@ -385,7 +385,7 @@ static void vg_init_clocks(struct clk_mgr *clk_mgr)
static void vg_build_watermark_ranges(struct clk_bw_params *bw_params, struct watermarks *table)
{
int i, num_valid_sets;
uint8_t i, num_valid_sets;
num_valid_sets = 0;
@@ -394,8 +394,11 @@ static void vg_build_watermark_ranges(struct clk_bw_params *bw_params, struct wa
if (!bw_params->wm_table.entries[i].valid)
continue;
table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting =
(uint8_t)bw_params->wm_table.entries[i].wm_inst;
table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType =
(uint8_t)bw_params->wm_table.entries[i].wm_type;
/* We will not select WM based on fclk, so leave it as unconstrained */
table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
@@ -409,7 +412,7 @@ static void vg_build_watermark_ranges(struct clk_bw_params *bw_params, struct wa
bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
}
table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
bw_params->clk_table.entries[i].dcfclk_mhz;
(uint16_t)bw_params->clk_table.entries[i].dcfclk_mhz;
} else {
/* unconstrained for memory retraining */
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
+7 -5
View File
@@ -114,7 +114,7 @@ static int dcn31_get_active_display_cnt_wa(
static void dcn31_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable)
{
struct dc *dc = clk_mgr_base->ctx->dc;
int i;
uint8_t i;
for (i = 0; i < dc->res_pool->pipe_count; ++i) {
struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
@@ -424,7 +424,7 @@ static struct dcn31_watermarks dummy_wms = { 0 };
static void dcn31_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn31_watermarks *table)
{
int i, num_valid_sets;
uint8_t i, num_valid_sets;
num_valid_sets = 0;
@@ -433,8 +433,10 @@ static void dcn31_build_watermark_ranges(struct clk_bw_params *bw_params, struct
if (!bw_params->wm_table.entries[i].valid)
continue;
table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting =
(uint8_t)bw_params->wm_table.entries[i].wm_inst;
table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType =
(uint8_t)bw_params->wm_table.entries[i].wm_type;
/* We will not select WM based on fclk, so leave it as unconstrained */
table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
@@ -448,7 +450,7 @@ static void dcn31_build_watermark_ranges(struct clk_bw_params *bw_params, struct
bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
}
table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
bw_params->clk_table.entries[i].dcfclk_mhz;
(uint16_t)bw_params->clk_table.entries[i].dcfclk_mhz;
} else {
/* unconstrained for memory retraining */
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
+7 -5
View File
@@ -149,7 +149,7 @@ static void dcn314_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state
bool safe_to_lower, bool disable)
{
struct dc *dc = clk_mgr_base->ctx->dc;
int i;
uint8_t i;
for (i = 0; i < dc->res_pool->pipe_count; ++i) {
struct pipe_ctx *pipe = safe_to_lower
@@ -495,7 +495,7 @@ static struct dcn314_ss_info_table ss_info_table = {
static void dcn314_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn314_watermarks *table)
{
int i, num_valid_sets;
uint8_t i, num_valid_sets;
num_valid_sets = 0;
@@ -504,8 +504,10 @@ static void dcn314_build_watermark_ranges(struct clk_bw_params *bw_params, struc
if (!bw_params->wm_table.entries[i].valid)
continue;
table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting =
(uint8_t)bw_params->wm_table.entries[i].wm_inst;
table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType =
(uint8_t)bw_params->wm_table.entries[i].wm_type;
/* We will not select WM based on fclk, so leave it as unconstrained */
table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
@@ -519,7 +521,7 @@ static void dcn314_build_watermark_ranges(struct clk_bw_params *bw_params, struc
bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
}
table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
bw_params->clk_table.entries[i].dcfclk_mhz;
(uint16_t)bw_params->clk_table.entries[i].dcfclk_mhz;
} else {
/* unconstrained for memory retraining */
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
+8 -5
View File
@@ -100,7 +100,7 @@ static bool should_disable_otg(struct pipe_ctx *pipe)
static void dcn315_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable)
{
struct dc *dc = clk_mgr_base->ctx->dc;
int i;
uint8_t i;
for (i = 0; i < dc->res_pool->pipe_count; ++i) {
struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
@@ -384,7 +384,7 @@ static struct dcn315_watermarks dummy_wms = { 0 };
static void dcn315_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn315_watermarks *table)
{
int i, num_valid_sets;
uint8_t i, num_valid_sets;
num_valid_sets = 0;
@@ -393,8 +393,11 @@ static void dcn315_build_watermark_ranges(struct clk_bw_params *bw_params, struc
if (!bw_params->wm_table.entries[i].valid)
continue;
table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting =
(uint8_t)bw_params->wm_table.entries[i].wm_inst;
table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType =
(uint8_t)bw_params->wm_table.entries[i].wm_type;
/* We will not select WM based on fclk, so leave it as unconstrained */
table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
@@ -408,7 +411,7 @@ static void dcn315_build_watermark_ranges(struct clk_bw_params *bw_params, struc
bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
}
table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
bw_params->clk_table.entries[i].dcfclk_mhz;
(uint16_t)bw_params->clk_table.entries[i].dcfclk_mhz;
} else {
/* unconstrained for memory retraining */
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
+8 -5
View File
@@ -103,7 +103,7 @@ static void dcn316_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state
bool safe_to_lower, bool disable)
{
struct dc *dc = clk_mgr_base->ctx->dc;
int i;
uint8_t i;
for (i = 0; i < dc->res_pool->pipe_count; ++i) {
struct pipe_ctx *pipe = safe_to_lower
@@ -350,7 +350,7 @@ static struct dcn316_watermarks dummy_wms = { 0 };
static void dcn316_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn316_watermarks *table)
{
int i, num_valid_sets;
uint8_t i, num_valid_sets;
num_valid_sets = 0;
@@ -359,8 +359,11 @@ static void dcn316_build_watermark_ranges(struct clk_bw_params *bw_params, struc
if (!bw_params->wm_table.entries[i].valid)
continue;
table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting =
(uint8_t)bw_params->wm_table.entries[i].wm_inst;
table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType =
(uint8_t)bw_params->wm_table.entries[i].wm_type;
/* We will not select WM based on fclk, so leave it as unconstrained */
table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
@@ -374,7 +377,7 @@ static void dcn316_build_watermark_ranges(struct clk_bw_params *bw_params, struc
bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
}
table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
bw_params->clk_table.entries[i].dcfclk_mhz;
(uint16_t)bw_params->clk_table.entries[i].dcfclk_mhz;
} else {
/* unconstrained for memory retraining */
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
+22 -21
View File
@@ -132,7 +132,7 @@ static const struct clk_mgr_mask clk_mgr_mask_dcn321 = {
static void dcn32_init_single_clock(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, unsigned int *entry_0,
unsigned int *num_levels)
{
unsigned int i;
uint8_t i;
char *entry_i = (char *)entry_0;
uint32_t ret = dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, 0xFF);
@@ -409,7 +409,7 @@ static void dcn32_update_clocks_update_dentist(
* floored in Mhz to describe the intended clock.
*/
dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK,
khz_to_mhz_floor(temp_dispclk_khz));
(uint16_t)khz_to_mhz_floor(temp_dispclk_khz));
if (dc->debug.override_dispclk_programming) {
REG_GET(DENTIST_DISPCLK_CNTL,
@@ -456,7 +456,7 @@ static void dcn32_update_clocks_update_dentist(
* floored in Mhz to describe the intended clock.
*/
dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK,
khz_to_mhz_floor(clk_mgr->base.clks.dispclk_khz));
(uint16_t)khz_to_mhz_floor(clk_mgr->base.clks.dispclk_khz));
if (dc->debug.override_dispclk_programming) {
REG_GET(DENTIST_DISPCLK_CNTL,
@@ -680,7 +680,7 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base,
if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz) &&
!dc->work_arounds.clock_update_disable_mask.dcfclk) {
clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DCFCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz));
dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DCFCLK, (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz));
}
if (should_set_clock(safe_to_lower, new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz) &&
@@ -715,13 +715,13 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base,
* frequency.
*/
if (dc->debug.disable_dc_mode_overwrite) {
dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, dc->clk_mgr->bw_params->max_memclk_mhz);
dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, dc->clk_mgr->bw_params->max_memclk_mhz);
dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, (uint16_t)dc->clk_mgr->bw_params->max_memclk_mhz);
dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, (uint16_t)dc->clk_mgr->bw_params->max_memclk_mhz);
} else
dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
dc->clk_mgr->bw_params->dc_mode_softmax_memclk);
(uint16_t)dc->clk_mgr->bw_params->dc_mode_softmax_memclk);
} else {
dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, dc->clk_mgr->bw_params->max_memclk_mhz);
dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, (uint16_t)dc->clk_mgr->bw_params->max_memclk_mhz);
}
}
}
@@ -755,9 +755,10 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base,
!dc->work_arounds.clock_update_disable_mask.uclk) {
if (dc->clk_mgr->dc_mode_softmax_enabled && dc->debug.disable_dc_mode_overwrite)
dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK,
max((int)dc->clk_mgr->bw_params->dc_mode_softmax_memclk, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz)));
(uint16_t)max((int)dc->clk_mgr->bw_params->dc_mode_softmax_memclk,
khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz)));
dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
}
if (clk_mgr_base->clks.num_ways != new_clocks->num_ways &&
@@ -783,7 +784,7 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base,
* floored in Mhz to describe the intended clock.
*/
dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DPPCLK,
khz_to_mhz_floor(clk_mgr_base->clks.dppclk_khz));
(uint16_t)khz_to_mhz_floor(clk_mgr_base->clks.dppclk_khz));
update_dppclk = true;
}
@@ -803,7 +804,7 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base,
should_set_clock(safe_to_lower, new_clocks->ref_dtbclk_khz / 1000, clk_mgr_base->clks.ref_dtbclk_khz / 1000)) {
/* DCCG requires KHz precision for DTBCLK */
clk_mgr_base->clks.ref_dtbclk_khz =
dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DTBCLK, khz_to_mhz_ceil(new_clocks->ref_dtbclk_khz));
dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DTBCLK, (uint16_t)khz_to_mhz_ceil(new_clocks->ref_dtbclk_khz));
dcn32_update_clocks_update_dtb_dto(clk_mgr, context, clk_mgr_base->clks.ref_dtbclk_khz);
}
@@ -822,7 +823,7 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base,
* floored in Mhz to describe the intended clock.
*/
dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DPPCLK,
khz_to_mhz_floor(clk_mgr_base->clks.dppclk_khz));
(uint16_t)khz_to_mhz_floor(clk_mgr_base->clks.dppclk_khz));
} else {
/* if clock is being raised, increase refclk before lowering DTO */
if (update_dppclk || update_dispclk)
@@ -968,7 +969,7 @@ static void dcn32_clock_read_ss_info(struct clk_mgr_internal *clk_mgr)
}
static void dcn32_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
{
unsigned int i;
uint8_t i;
struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
WatermarksExternal_t *table = (WatermarksExternal_t *) clk_mgr->wm_range_table;
@@ -1002,13 +1003,13 @@ static void dcn32_set_hard_min_memclk(struct clk_mgr *clk_mgr_base, bool current
if (current_mode) {
if (clk_mgr_base->clks.p_state_change_support)
dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
(uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
else
dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
clk_mgr_base->bw_params->max_memclk_mhz);
(uint16_t)clk_mgr_base->bw_params->max_memclk_mhz);
} else {
dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz);
(uint16_t)clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz);
}
}
@@ -1020,7 +1021,7 @@ static void dcn32_set_hard_max_memclk(struct clk_mgr *clk_mgr_base)
if (!clk_mgr->smu_present)
return;
dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, clk_mgr_base->bw_params->max_memclk_mhz);
dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, (uint16_t)clk_mgr_base->bw_params->max_memclk_mhz);
}
/* Get current memclk states, update bounding box */
@@ -1052,7 +1053,7 @@ static void dcn32_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base)
clk_mgr_base->bw_params->max_memclk_mhz =
clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_memclk_levels - 1].memclk_mhz;
clk_mgr_base->bw_params->clk_table.num_entries = num_levels ? num_levels : 1;
clk_mgr_base->bw_params->clk_table.num_entries = (uint8_t)(num_levels ? num_levels : 1);
if (clk_mgr->dpm_present && !num_levels)
clk_mgr->dpm_present = false;
@@ -1109,7 +1110,7 @@ static void dcn32_set_max_memclk(struct clk_mgr *clk_mgr_base, unsigned int memc
if (!clk_mgr->smu_present)
return;
dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, memclk_mhz);
dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, (uint16_t)memclk_mhz);
}
static void dcn32_set_min_memclk(struct clk_mgr *clk_mgr_base, unsigned int memclk_mhz)
@@ -1119,7 +1120,7 @@ static void dcn32_set_min_memclk(struct clk_mgr *clk_mgr_base, unsigned int memc
if (!clk_mgr->smu_present)
return;
dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, memclk_mhz);
dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, (uint16_t)memclk_mhz);
}
static struct clk_mgr_funcs dcn32_funcs = {
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
+8 -6
View File
@@ -190,7 +190,7 @@ void dcn35_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context
bool safe_to_lower, bool disable)
{
struct dc *dc = clk_mgr_base->ctx->dc;
int i;
uint8_t i;
if (dc->ctx->dce_environment == DCE_ENV_DIAG)
return;
@@ -332,7 +332,7 @@ static uint8_t get_lowest_dpia_index(const struct dc_link *link)
continue;
if (idx > dc_struct->links[i]->link_index)
idx = dc_struct->links[i]->link_index;
idx = (uint8_t)dc_struct->links[i]->link_index;
}
return idx;
@@ -863,7 +863,7 @@ static void dcn35_read_ss_info_from_lut(struct clk_mgr_internal *clk_mgr)
static void dcn35_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn35_watermarks *table)
{
int i, num_valid_sets;
uint8_t i, num_valid_sets;
num_valid_sets = 0;
@@ -872,8 +872,10 @@ static void dcn35_build_watermark_ranges(struct clk_bw_params *bw_params, struct
if (!bw_params->wm_table.entries[i].valid)
continue;
table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting =
(uint8_t)bw_params->wm_table.entries[i].wm_inst;
table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType =
(uint8_t)bw_params->wm_table.entries[i].wm_type;
/* We will not select WM based on fclk, so leave it as unconstrained */
table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
@@ -887,7 +889,7 @@ static void dcn35_build_watermark_ranges(struct clk_bw_params *bw_params, struct
bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
}
table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
bw_params->clk_table.entries[i].dcfclk_mhz;
(uint16_t)bw_params->clk_table.entries[i].dcfclk_mhz;
} else {
/* unconstrained for memory retraining */
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
+20 -20
View File
@@ -174,7 +174,7 @@ static void dcn401_init_single_clock(struct clk_mgr_internal *clk_mgr, PPCLK_e c
/* if the initial message failed, num_levels will be 0 */
for (i = 0; i < *num_levels && i < ARRAY_SIZE(clk_mgr->base.bw_params->clk_table.entries); i++) {
*((unsigned int *)entry_i) = (dcn401_smu_get_dpm_freq_by_index(clk_mgr, clk, i) & 0xFFFF);
*((unsigned int *)entry_i) = (dcn401_smu_get_dpm_freq_by_index(clk_mgr, clk, (uint8_t)i) & 0xFFFF);
entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]);
}
}
@@ -182,15 +182,15 @@ static void dcn401_init_single_clock(struct clk_mgr_internal *clk_mgr, PPCLK_e c
static void dcn401_build_wm_range_table(struct clk_mgr *clk_mgr)
{
/* For min clocks use as reported by PM FW and report those as min */
uint16_t min_uclk_mhz = clk_mgr->bw_params->clk_table.entries[0].memclk_mhz;
uint16_t min_dcfclk_mhz = clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz;
unsigned int min_uclk_mhz = clk_mgr->bw_params->clk_table.entries[0].memclk_mhz;
unsigned int min_dcfclk_mhz = clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz;
/* Set A - Normal - default values */
clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid = true;
clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE;
clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;
clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = (uint16_t)min_dcfclk_mhz;
clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF;
clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = min_uclk_mhz;
clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = (uint16_t)min_uclk_mhz;
clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_uclk = 0xFFFF;
/* Set B - Unused on dcn4 */
@@ -201,9 +201,9 @@ static void dcn401_build_wm_range_table(struct clk_mgr *clk_mgr)
if (clk_mgr->ctx->dc->bb_overrides.dummy_clock_change_latency_ns != 0x7FFFFFFF) {
clk_mgr->bw_params->wm_table.nv_entries[WM_1A].valid = true;
clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.wm_type = WATERMARKS_DUMMY_PSTATE;
clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;
clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.min_dcfclk = (uint16_t)min_dcfclk_mhz;
clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.max_dcfclk = 0xFFFF;
clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.min_uclk = min_uclk_mhz;
clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.min_uclk = (uint16_t)min_uclk_mhz;
clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.max_uclk = 0xFFFF;
} else {
clk_mgr->bw_params->wm_table.nv_entries[WM_1A].valid = false;
@@ -604,10 +604,10 @@ static int dcn401_set_hard_min_by_freq_optimized(struct clk_mgr_internal *clk_mg
* clock returned is less than requested, then we will ceil the
* requested value to mhz and call it again.
*/
int actual_clk_khz = dcn401_smu_set_hard_min_by_freq(clk_mgr, clk, khz_to_mhz_floor(requested_clk_khz));
int actual_clk_khz = dcn401_smu_set_hard_min_by_freq(clk_mgr, clk, (uint16_t)khz_to_mhz_floor(requested_clk_khz));
if (actual_clk_khz < requested_clk_khz)
actual_clk_khz = dcn401_smu_set_hard_min_by_freq(clk_mgr, clk, khz_to_mhz_ceil(requested_clk_khz));
actual_clk_khz = dcn401_smu_set_hard_min_by_freq(clk_mgr, clk, (uint16_t)khz_to_mhz_ceil(requested_clk_khz));
return actual_clk_khz;
}
@@ -849,7 +849,7 @@ static unsigned int dcn401_build_update_bandwidth_clocks_sequence(
clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
if (dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_DCFCLK)) {
block_sequence[num_steps].params.update_hardmin_params.ppclk = PPCLK_DCFCLK;
block_sequence[num_steps].params.update_hardmin_params.freq_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz);
block_sequence[num_steps].params.update_hardmin_params.freq_mhz = (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz);
block_sequence[num_steps].params.update_hardmin_params.response = NULL;
block_sequence[num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK;
num_steps++;
@@ -860,7 +860,7 @@ static unsigned int dcn401_build_update_bandwidth_clocks_sequence(
if (should_set_clock(safe_to_lower, new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
if (dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_DCFCLK)) {
block_sequence[num_steps].params.update_deep_sleep_dcfclk_params.freq_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_sleep_khz);
block_sequence[num_steps].params.update_deep_sleep_dcfclk_params.freq_mhz = (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_sleep_khz);
block_sequence[num_steps].func = CLK_MGR401_UPDATE_DEEP_SLEEP_DCFCLK;
num_steps++;
}
@@ -984,24 +984,24 @@ static unsigned int dcn401_build_update_bandwidth_clocks_sequence(
/* When idle DPM is enabled, need to send active and idle hardmins separately */
/* CLK_MGR401_UPDATE_ACTIVE_HARDMINS */
if ((update_active_uclk || update_active_fclk) && is_idle_dpm_enabled) {
block_sequence[num_steps].params.update_idle_hardmin_params.uclk_mhz = active_uclk_mhz;
block_sequence[num_steps].params.update_idle_hardmin_params.fclk_mhz = active_fclk_mhz;
block_sequence[num_steps].params.update_idle_hardmin_params.uclk_mhz = (uint16_t)active_uclk_mhz;
block_sequence[num_steps].params.update_idle_hardmin_params.fclk_mhz = (uint16_t)active_fclk_mhz;
block_sequence[num_steps].func = CLK_MGR401_UPDATE_ACTIVE_HARDMINS;
num_steps++;
}
/* CLK_MGR401_UPDATE_IDLE_HARDMINS */
if ((update_idle_uclk || update_idle_fclk) && is_idle_dpm_enabled) {
block_sequence[num_steps].params.update_idle_hardmin_params.uclk_mhz = idle_uclk_mhz;
block_sequence[num_steps].params.update_idle_hardmin_params.fclk_mhz = idle_fclk_mhz;
block_sequence[num_steps].params.update_idle_hardmin_params.uclk_mhz = (uint16_t)idle_uclk_mhz;
block_sequence[num_steps].params.update_idle_hardmin_params.fclk_mhz = (uint16_t)idle_fclk_mhz;
block_sequence[num_steps].func = CLK_MGR401_UPDATE_IDLE_HARDMINS;
num_steps++;
}
/* CLK_MGR401_UPDATE_SUBVP_HARDMINS */
if ((update_subvp_prefetch_dramclk || update_subvp_prefetch_fclk) && is_df_throttle_opt_enabled) {
block_sequence[num_steps].params.update_idle_hardmin_params.uclk_mhz = subvp_prefetch_dramclk_mhz;
block_sequence[num_steps].params.update_idle_hardmin_params.fclk_mhz = subvp_prefetch_fclk_mhz;
block_sequence[num_steps].params.update_idle_hardmin_params.uclk_mhz = (uint16_t)subvp_prefetch_dramclk_mhz;
block_sequence[num_steps].params.update_idle_hardmin_params.fclk_mhz = (uint16_t)subvp_prefetch_fclk_mhz;
block_sequence[num_steps].func = CLK_MGR401_UPDATE_SUBVP_HARDMINS;
num_steps++;
}
@@ -1010,7 +1010,7 @@ static unsigned int dcn401_build_update_bandwidth_clocks_sequence(
if (update_active_uclk || update_idle_uclk) {
if (!is_idle_dpm_enabled) {
block_sequence[num_steps].params.update_hardmin_params.ppclk = PPCLK_UCLK;
block_sequence[num_steps].params.update_hardmin_params.freq_mhz = active_uclk_mhz;
block_sequence[num_steps].params.update_hardmin_params.freq_mhz = (uint16_t)active_uclk_mhz;
block_sequence[num_steps].params.update_hardmin_params.response = NULL;
block_sequence[num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK;
num_steps++;
@@ -1123,7 +1123,7 @@ static unsigned int dcn401_build_update_display_clocks_sequence(
dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_DTBCLK)) {
/* DCCG requires KHz precision for DTBCLK */
block_sequence[num_steps].params.update_hardmin_params.ppclk = PPCLK_DTBCLK;
block_sequence[num_steps].params.update_hardmin_params.freq_mhz = khz_to_mhz_ceil(new_clocks->ref_dtbclk_khz);
block_sequence[num_steps].params.update_hardmin_params.freq_mhz = (uint16_t)khz_to_mhz_ceil(new_clocks->ref_dtbclk_khz);
block_sequence[num_steps].params.update_hardmin_params.response = &clk_mgr_base->clks.ref_dtbclk_khz;
block_sequence[num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK;
num_steps++;
@@ -1318,7 +1318,7 @@ static void dcn401_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
/* collect valid ranges, place in pmfw table */
for (i = 0; i < WM_SET_COUNT; i++)
if (clk_mgr->base.bw_params->wm_table.nv_entries[i].valid) {
table->Watermarks.WatermarkRow[i].WmSetting = i;
table->Watermarks.WatermarkRow[i].WmSetting = (uint8_t)i;
table->Watermarks.WatermarkRow[i].Flags = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.wm_type;
}
dcn401_smu_set_dram_addr_high(clk_mgr, clk_mgr->wm_range_table_addr >> 32);
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c
+6 -4
View File
@@ -634,7 +634,7 @@ static void dcn42_read_ss_info_from_lut(struct clk_mgr_internal *clk_mgr)
void dcn42_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn42_watermarks *table)
{
int i, num_valid_sets;
uint8_t i, num_valid_sets;
num_valid_sets = 0;
@@ -643,8 +643,10 @@ void dcn42_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn42_
if (!bw_params->wm_table.entries[i].valid)
continue;
table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting =
(uint8_t)bw_params->wm_table.entries[i].wm_inst;
table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType =
(uint8_t)bw_params->wm_table.entries[i].wm_type;
/* We will not select WM based on fclk, so leave it as unconstrained */
table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
@@ -658,7 +660,7 @@ void dcn42_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn42_
bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
}
table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
bw_params->clk_table.entries[i].dcfclk_mhz;
(uint16_t)bw_params->clk_table.entries[i].dcfclk_mhz;
} else {
/* unconstrained for memory retraining */
drivers/gpu/drm/amd/display/dc/core/dc.c
+34 -34
View File
@@ -235,7 +235,7 @@ static bool create_links(
* variants of the same card.
*/
for (i = 0; dc->link_count < connectors_num && i < MAX_LINKS; i++) {
struct graphics_object_id connector_id = bios->funcs->get_connector_id(bios, i);
struct graphics_object_id connector_id = bios->funcs->get_connector_id(bios, (uint8_t)i);
struct link_init_data link_init_params = {0};
struct dc_link *link;
@@ -246,7 +246,7 @@ static bool create_links(
link_init_params.ctx = dc->ctx;
/* next BIOS object table connector */
link_init_params.connector_index = i;
link_init_params.connector_index = (uint8_t)i;
link_init_params.link_index = dc->link_count;
link_init_params.dc = dc;
link = dc->link_srv->create_link(&link_init_params);
@@ -267,7 +267,7 @@ static bool create_links(
struct dc_link *link;
link_init_params.ctx = dc->ctx;
link_init_params.connector_index = i;
link_init_params.connector_index = (uint8_t)i;
link_init_params.link_index = dc->link_count;
link_init_params.dc = dc;
link_init_params.is_dpia_link = true;
@@ -659,12 +659,12 @@ bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream,
/* By default, capture the full frame */
param.windowa_x_start = 0;
param.windowa_y_start = 0;
param.windowa_x_end = pipe->stream->timing.h_addressable;
param.windowa_y_end = pipe->stream->timing.v_addressable;
param.windowa_x_end = (uint16_t)pipe->stream->timing.h_addressable;
param.windowa_y_end = (uint16_t)pipe->stream->timing.v_addressable;
param.windowb_x_start = 0;
param.windowb_y_start = 0;
param.windowb_x_end = pipe->stream->timing.h_addressable;
param.windowb_y_end = pipe->stream->timing.v_addressable;
param.windowb_x_end = (uint16_t)pipe->stream->timing.h_addressable;
param.windowb_y_end = (uint16_t)pipe->stream->timing.v_addressable;
param.crc_poly_mode = crc_poly_mode;
if (crc_window) {
@@ -2137,7 +2137,7 @@ static uint8_t get_stream_mask(struct dc *dc, struct dc_state *context)
stream_mask |= 1 << i;
}
return stream_mask;
return (uint8_t)stream_mask;
}
void dc_z10_restore(const struct dc *dc)
@@ -2482,7 +2482,7 @@ enum dc_status dc_commit_streams(struct dc *dc, struct dc_commit_streams_params
set[i].stream = stream;
if (status) {
set[i].plane_count = status->plane_count;
set[i].plane_count = (uint8_t)status->plane_count;
for (j = 0; j < status->plane_count; j++)
set[i].plane_states[j] = status->plane_states[j];
}
@@ -2541,7 +2541,7 @@ enum dc_status dc_commit_streams(struct dc *dc, struct dc_commit_streams_params
for (i = 0; i < params->stream_count; i++) {
for (j = 0; j < context->stream_count; j++) {
if (params->streams[i]->stream_id == context->streams[j]->stream_id)
params->streams[i]->out.otg_offset = context->stream_status[j].primary_otg_inst;
params->streams[i]->out.otg_offset = (uint8_t)context->stream_status[j].primary_otg_inst;
if (dc_is_embedded_signal(params->streams[i]->signal)) {
struct dc_stream_status *status = dc_state_get_stream_status(context, params->streams[i]);
@@ -2669,7 +2669,7 @@ void dc_post_update_surfaces_to_stream(struct dc *dc)
for (i = 0; i < dc->res_pool->pipe_count; i++)
if (context->res_ctx.pipe_ctx[i].stream == NULL ||
context->res_ctx.pipe_ctx[i].plane_state == NULL) {
context->res_ctx.pipe_ctx[i].pipe_idx = i;
context->res_ctx.pipe_ctx[i].pipe_idx = (uint8_t)i;
dc->hwss.disable_plane(dc, context, &context->res_ctx.pipe_ctx[i]);
}
@@ -3218,10 +3218,10 @@ static void copy_surface_update_to_plane(
surface->flip_immediate =
srf_update->flip_addr->flip_immediate;
surface->time.time_elapsed_in_us[surface->time.index] =
srf_update->flip_addr->flip_timestamp_in_us -
surface->time.prev_update_time_in_us;
(unsigned int)(srf_update->flip_addr->flip_timestamp_in_us -
surface->time.prev_update_time_in_us);
surface->time.prev_update_time_in_us =
srf_update->flip_addr->flip_timestamp_in_us;
(unsigned int)srf_update->flip_addr->flip_timestamp_in_us;
surface->time.index++;
if (surface->time.index >= DC_PLANE_UPDATE_TIMES_MAX)
surface->time.index = 0;
@@ -3997,7 +3997,7 @@ void dc_dmub_update_dirty_rect(struct dc *dc,
else
update_dirty_rect->cmd_version = DMUB_CMD_CURSOR_UPDATE_VERSION_1;
update_dirty_rect->dirty_rect_count = flip_addr->dirty_rect_count;
update_dirty_rect->dirty_rect_count = (uint8_t)flip_addr->dirty_rect_count;
memcpy(update_dirty_rect->src_dirty_rects, flip_addr->dirty_rects,
sizeof(flip_addr->dirty_rects));
for (j = 0; j < dc->res_pool->pipe_count; j++) {
@@ -4008,9 +4008,9 @@ void dc_dmub_update_dirty_rect(struct dc *dc,
if (pipe_ctx->plane_state != plane_state)
continue;
update_dirty_rect->panel_inst = panel_inst;
update_dirty_rect->pipe_idx = j;
update_dirty_rect->otg_inst = pipe_ctx->stream_res.tg->inst;
update_dirty_rect->panel_inst = (uint8_t)panel_inst;
update_dirty_rect->pipe_idx = (uint8_t)j;
update_dirty_rect->otg_inst = (uint8_t)pipe_ctx->stream_res.tg->inst;
dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);
}
}
@@ -4058,7 +4058,7 @@ static void build_dmub_update_dirty_rect(
else
update_dirty_rect->cmd_version = DMUB_CMD_CURSOR_UPDATE_VERSION_1;
update_dirty_rect->dirty_rect_count = flip_addr->dirty_rect_count;
update_dirty_rect->dirty_rect_count = (uint8_t)flip_addr->dirty_rect_count;
memcpy(update_dirty_rect->src_dirty_rects, flip_addr->dirty_rects,
sizeof(flip_addr->dirty_rects));
for (j = 0; j < dc->res_pool->pipe_count; j++) {
@@ -4068,9 +4068,9 @@ static void build_dmub_update_dirty_rect(
continue;
if (pipe_ctx->plane_state != plane_state)
continue;
update_dirty_rect->panel_inst = panel_inst;
update_dirty_rect->pipe_idx = j;
update_dirty_rect->otg_inst = pipe_ctx->stream_res.tg->inst;
update_dirty_rect->panel_inst = (uint8_t)panel_inst;
update_dirty_rect->pipe_idx = (uint8_t)j;
update_dirty_rect->otg_inst = (uint8_t)pipe_ctx->stream_res.tg->inst;
dc_dmub_cmd[*dmub_cmd_count].dmub_cmd = cmd;
dc_dmub_cmd[*dmub_cmd_count].wait_type = DM_DMUB_WAIT_TYPE_NO_WAIT;
(*dmub_cmd_count)++;
@@ -4373,7 +4373,7 @@ static void commit_planes_for_stream(struct dc *dc,
struct dmub_hw_lock_inst_flags inst_flags = { 0 };
hw_locks.bits.lock_dig = 1;
inst_flags.dig_inst = top_pipe_to_program->stream_res.tg->inst;
inst_flags.dig_inst = (uint8_t)top_pipe_to_program->stream_res.tg->inst;
dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,
true,
@@ -4640,7 +4640,7 @@ static void commit_planes_for_stream(struct dc *dc,
struct dmub_hw_lock_inst_flags inst_flags = { 0 };
hw_locks.bits.lock_dig = 1;
inst_flags.dig_inst = top_pipe_to_program->stream_res.tg->inst;
inst_flags.dig_inst = (uint8_t)top_pipe_to_program->stream_res.tg->inst;
dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,
false,
@@ -6170,12 +6170,12 @@ bool dc_process_dmub_aux_transfer_async(struct dc *dc,
else
cmd.dp_aux_access.aux_control.type = AUX_CHANNEL_LEGACY_DDC;
cmd.dp_aux_access.aux_control.instance = dc->links[link_index]->ddc_hw_inst;
cmd.dp_aux_access.aux_control.instance = (uint8_t)dc->links[link_index]->ddc_hw_inst;
cmd.dp_aux_access.aux_control.sw_crc_enabled = 0;
cmd.dp_aux_access.aux_control.timeout = 0;
cmd.dp_aux_access.aux_control.dpaux.address = payload->address;
cmd.dp_aux_access.aux_control.dpaux.is_i2c_over_aux = payload->i2c_over_aux;
cmd.dp_aux_access.aux_control.dpaux.length = payload->length;
cmd.dp_aux_access.aux_control.dpaux.length = (uint8_t)payload->length;
/* set aux action */
if (payload->i2c_over_aux) {
@@ -6241,7 +6241,7 @@ bool dc_smart_power_oled_enable(const struct dc_link *link, bool enable, uint16_
}
if (pipe_ctx)
otg_inst = pipe_ctx->stream_res.tg->inst;
otg_inst = (uint8_t)pipe_ctx->stream_res.tg->inst;
// before enable smart power OLED, we need to call set pipe for DMUB to set ABM config
if (enable) {
@@ -6258,11 +6258,11 @@ bool dc_smart_power_oled_enable(const struct dc_link *link, bool enable, uint16_
sizeof(struct dmub_rb_cmd_smart_power_oled_enable_data) - sizeof(struct dmub_cmd_header);
cmd.smart_power_oled_enable.header.ret_status = 1;
cmd.smart_power_oled_enable.data.enable = enable;
cmd.smart_power_oled_enable.data.panel_inst = panel_inst;
cmd.smart_power_oled_enable.data.panel_inst = (uint8_t)panel_inst;
cmd.smart_power_oled_enable.data.peak_nits = peak_nits;
cmd.smart_power_oled_enable.data.otg_inst = otg_inst;
cmd.smart_power_oled_enable.data.digfe_inst = link->link_enc->preferred_engine;
cmd.smart_power_oled_enable.data.digbe_inst = link->link_enc->transmitter;
cmd.smart_power_oled_enable.data.digfe_inst = (uint8_t)link->link_enc->preferred_engine;
cmd.smart_power_oled_enable.data.digbe_inst = (uint8_t)link->link_enc->transmitter;
cmd.smart_power_oled_enable.data.debugcontrol = debug_control;
cmd.smart_power_oled_enable.data.triggerline = triggerline;
@@ -6293,7 +6293,7 @@ bool dc_smart_power_oled_get_max_cll(const struct dc_link *link, unsigned int *p
cmd.smart_power_oled_getmaxcll.header.payload_bytes = sizeof(cmd.smart_power_oled_getmaxcll.data);
cmd.smart_power_oled_getmaxcll.header.ret_status = 1;
cmd.smart_power_oled_getmaxcll.data.input.panel_inst = panel_inst;
cmd.smart_power_oled_getmaxcll.data.input.panel_inst = (uint8_t)panel_inst;
// send cmd and wait for reply
status = dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY);
@@ -6351,7 +6351,7 @@ bool dc_process_dmub_set_config_async(struct dc *dc,
cmd.set_config_access.header.type = DMUB_CMD__DPIA;
cmd.set_config_access.header.sub_type = DMUB_CMD__DPIA_SET_CONFIG_ACCESS;
cmd.set_config_access.set_config_control.instance = dc->links[link_index]->ddc_hw_inst;
cmd.set_config_access.set_config_control.instance = (uint8_t)dc->links[link_index]->ddc_hw_inst;
cmd.set_config_access.set_config_control.cmd_pkt.msg_type = payload->msg_type;
cmd.set_config_access.set_config_control.cmd_pkt.msg_data = payload->msg_data;
@@ -6395,7 +6395,7 @@ enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc,
cmd.set_mst_alloc_slots.header.type = DMUB_CMD__DPIA;
cmd.set_mst_alloc_slots.header.sub_type = DMUB_CMD__DPIA_MST_ALLOC_SLOTS;
cmd.set_mst_alloc_slots.mst_slots_control.instance = dc->links[link_index]->ddc_hw_inst;
cmd.set_mst_alloc_slots.mst_slots_control.instance = (uint8_t)dc->links[link_index]->ddc_hw_inst;
cmd.set_mst_alloc_slots.mst_slots_control.mst_alloc_slots = mst_alloc_slots;
if (!dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY))
@@ -6435,7 +6435,7 @@ void dc_process_dmub_dpia_set_tps_notification(const struct dc *dc, uint32_t lin
cmd.set_tps_notification.header.type = DMUB_CMD__DPIA;
cmd.set_tps_notification.header.sub_type = DMUB_CMD__DPIA_SET_TPS_NOTIFICATION;
cmd.set_tps_notification.tps_notification.instance = dc->links[link_index]->ddc_hw_inst;
cmd.set_tps_notification.tps_notification.instance = (uint8_t)dc->links[link_index]->ddc_hw_inst;
cmd.set_tps_notification.tps_notification.tps = tps;
dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
+45 -45
View File
@@ -347,39 +347,39 @@ void get_surface_visual_confirm_color(
switch (pipe_ctx->plane_res.scl_data.format) {
case PIXEL_FORMAT_ARGB8888:
/* set border color to red */
color->color_r_cr = color_value;
color->color_r_cr = (uint16_t)color_value;
if (pipe_ctx->plane_state->layer_index > 0) {
/* set border color to pink */
color->color_b_cb = color_value;
color->color_g_y = color_value * 0.5;
color->color_b_cb = (uint16_t)color_value;
color->color_g_y = (uint16_t)(color_value / 2);
}
break;
case PIXEL_FORMAT_ARGB2101010:
/* set border color to blue */
color->color_b_cb = color_value;
color->color_b_cb = (uint16_t)color_value;
if (pipe_ctx->plane_state->layer_index > 0) {
/* set border color to cyan */
color->color_g_y = color_value;
color->color_g_y = (uint16_t)color_value;
}
break;
case PIXEL_FORMAT_420BPP8:
/* set border color to green */
color->color_g_y = color_value;
color->color_g_y = (uint16_t)color_value;
break;
case PIXEL_FORMAT_420BPP10:
/* set border color to yellow */
color->color_g_y = color_value;
color->color_r_cr = color_value;
color->color_g_y = (uint16_t)color_value;
color->color_r_cr = (uint16_t)color_value;
break;
case PIXEL_FORMAT_FP16:
/* set border color to white */
color->color_r_cr = color_value;
color->color_b_cb = color_value;
color->color_g_y = color_value;
color->color_r_cr = (uint16_t)color_value;
color->color_b_cb = (uint16_t)color_value;
color->color_g_y = (uint16_t)color_value;
if (pipe_ctx->plane_state->layer_index > 0) {
/* set border color to orange */
color->color_g_y = 0.22 * color_value;
color->color_g_y = (uint16_t)((color_value * 22) / 100);
color->color_b_cb = 0;
}
break;
@@ -405,21 +405,21 @@ void get_hdr_visual_confirm_color(
case PIXEL_FORMAT_ARGB2101010:
if (top_pipe_ctx->stream->out_transfer_func.tf == TRANSFER_FUNCTION_PQ) {
/* HDR10, ARGB2101010 - set border color to red */
color->color_r_cr = color_value;
color->color_r_cr = (uint16_t)color_value;
} else if (top_pipe_ctx->stream->out_transfer_func.tf == TRANSFER_FUNCTION_GAMMA22) {
/* FreeSync 2 ARGB2101010 - set border color to pink */
color->color_r_cr = color_value;
color->color_b_cb = color_value;
color->color_r_cr = (uint16_t)color_value;
color->color_b_cb = (uint16_t)color_value;
} else
is_sdr = true;
break;
case PIXEL_FORMAT_FP16:
if (top_pipe_ctx->stream->out_transfer_func.tf == TRANSFER_FUNCTION_PQ) {
/* HDR10, FP16 - set border color to blue */
color->color_b_cb = color_value;
color->color_b_cb = (uint16_t)color_value;
} else if (top_pipe_ctx->stream->out_transfer_func.tf == TRANSFER_FUNCTION_GAMMA22) {
/* FreeSync 2 HDR - set border color to green */
color->color_g_y = color_value;
color->color_g_y = (uint16_t)color_value;
} else
is_sdr = true;
break;
@@ -430,9 +430,9 @@ void get_hdr_visual_confirm_color(
if (is_sdr) {
/* SDR - set border color to Gray */
color->color_r_cr = color_value/2;
color->color_b_cb = color_value/2;
color->color_g_y = color_value/2;
color->color_r_cr = (uint16_t)(color_value / 2);
color->color_b_cb = (uint16_t)(color_value / 2);
color->color_g_y = (uint16_t)(color_value / 2);
}
}
@@ -456,7 +456,7 @@ void get_smartmux_visual_confirm_color(
*color = sm_ver_colors[dc->config.smart_mux_version];
} else {
/* dGPU driving the eDP - red */
color->color_r_cr = color_value;
color->color_r_cr = (uint16_t)color_value;
color->color_g_y = 0;
color->color_b_cb = 0;
}
@@ -478,19 +478,19 @@ void get_vabc_visual_confirm_color(
if (edp_link) {
switch (edp_link->backlight_control_type) {
case BACKLIGHT_CONTROL_PWM:
color->color_r_cr = color_value;
color->color_r_cr = (uint16_t)color_value;
color->color_g_y = 0;
color->color_b_cb = 0;
break;
case BACKLIGHT_CONTROL_AMD_AUX:
color->color_r_cr = 0;
color->color_g_y = color_value;
color->color_g_y = (uint16_t)color_value;
color->color_b_cb = 0;
break;
case BACKLIGHT_CONTROL_VESA_AUX:
color->color_r_cr = 0;
color->color_g_y = 0;
color->color_b_cb = color_value;
color->color_b_cb = (uint16_t)color_value;
break;
}
} else {
@@ -508,19 +508,19 @@ void get_subvp_visual_confirm_color(
if (pipe_ctx) {
switch (pipe_ctx->p_state_type) {
case P_STATE_SUB_VP:
color->color_r_cr = color_value;
color->color_r_cr = (uint16_t)color_value;
color->color_g_y = 0;
color->color_b_cb = 0;
break;
case P_STATE_DRR_SUB_VP:
color->color_r_cr = 0;
color->color_g_y = color_value;
color->color_g_y = (uint16_t)color_value;
color->color_b_cb = 0;
break;
case P_STATE_V_BLANK_SUB_VP:
color->color_r_cr = 0;
color->color_g_y = 0;
color->color_b_cb = color_value;
color->color_b_cb = (uint16_t)color_value;
break;
default:
break;
@@ -537,34 +537,34 @@ void get_mclk_switch_visual_confirm_color(
if (pipe_ctx) {
switch (pipe_ctx->p_state_type) {
case P_STATE_V_BLANK:
color->color_r_cr = color_value;
color->color_g_y = color_value;
color->color_r_cr = (uint16_t)color_value;
color->color_g_y = (uint16_t)color_value;
color->color_b_cb = 0;
break;
case P_STATE_FPO:
color->color_r_cr = 0;
color->color_g_y = color_value;
color->color_b_cb = color_value;
color->color_g_y = (uint16_t)color_value;
color->color_b_cb = (uint16_t)color_value;
break;
case P_STATE_V_ACTIVE:
color->color_r_cr = color_value;
color->color_r_cr = (uint16_t)color_value;
color->color_g_y = 0;
color->color_b_cb = color_value;
color->color_b_cb = (uint16_t)color_value;
break;
case P_STATE_SUB_VP:
color->color_r_cr = color_value;
color->color_r_cr = (uint16_t)color_value;
color->color_g_y = 0;
color->color_b_cb = 0;
break;
case P_STATE_DRR_SUB_VP:
color->color_r_cr = 0;
color->color_g_y = color_value;
color->color_g_y = (uint16_t)color_value;
color->color_b_cb = 0;
break;
case P_STATE_V_BLANK_SUB_VP:
color->color_r_cr = 0;
color->color_g_y = 0;
color->color_b_cb = color_value;
color->color_b_cb = (uint16_t)color_value;
break;
default:
break;
@@ -579,13 +579,13 @@ void get_cursor_visual_confirm_color(
uint32_t color_value = MAX_TG_COLOR_VALUE;
if (pipe_ctx->stream && pipe_ctx->stream->cursor_position.enable) {
color->color_r_cr = color_value;
color->color_r_cr = (uint16_t)color_value;
color->color_g_y = 0;
color->color_b_cb = 0;
} else {
color->color_r_cr = 0;
color->color_g_y = 0;
color->color_b_cb = color_value;
color->color_b_cb = (uint16_t)color_value;
}
}
@@ -723,9 +723,9 @@ void get_fams2_visual_confirm_color(
/* driver only handles visual confirm when FAMS2 is disabled */
if (!dc_state_is_fams2_in_use(dc, context)) {
/* when FAMS2 is disabled, all pipes are grey */
color->color_g_y = color_value / 2;
color->color_b_cb = color_value / 2;
color->color_r_cr = color_value / 2;
color->color_g_y = (uint16_t)(color_value / 2);
color->color_b_cb = (uint16_t)(color_value / 2);
color->color_r_cr = (uint16_t)(color_value / 2);
}
}
@@ -2414,7 +2414,7 @@ void get_surface_tile_visual_confirm_color(
switch (bottom_pipe_ctx->plane_state->tiling_info.gfx9.swizzle) {
case DC_SW_LINEAR:
/* LINEAR Surface - set border color to red */
color->color_r_cr = color_value;
color->color_r_cr = (uint16_t)color_value;
break;
default:
break;
@@ -4595,8 +4595,8 @@ void get_refresh_rate_confirm_color(struct pipe_ctx *pipe_ctx, struct tg_color *
if (max_refresh_rate - min_refresh_rate)
scaling_factor = MAX_TG_COLOR_VALUE * (refresh_rate - min_refresh_rate) / (max_refresh_rate - min_refresh_rate);
pipe_ctx->visual_confirm_color.color_r_cr = color_value;
pipe_ctx->visual_confirm_color.color_g_y = scaling_factor;
pipe_ctx->visual_confirm_color.color_b_cb = color_value;
pipe_ctx->visual_confirm_color.color_r_cr = (uint16_t)color_value;
pipe_ctx->visual_confirm_color.color_g_y = (uint16_t)scaling_factor;
pipe_ctx->visual_confirm_color.color_b_cb = (uint16_t)color_value;
}
}

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