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drivers: net: Add APM X-Gene SoC ethernet driver support.
This patch adds network driver for APM X-Gene SoC ethernet. Signed-off-by: Iyappan Subramanian <isubramanian@apm.com> Signed-off-by: Ravi Patel <rapatel@apm.com> Signed-off-by: Keyur Chudgar <kchudgar@apm.com> Signed-off-by: Dean Nelson <dnelson@redhat.com> Reviewed-by: Tobias Klauser <tklauser@distanz.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Iyappan Subramanian
committed by
David S. Miller
David S. Miller
parent
3d390425a6
commit
e6ad767305
@@ -24,6 +24,7 @@ source "drivers/net/ethernet/allwinner/Kconfig"
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source "drivers/net/ethernet/alteon/Kconfig"
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source "drivers/net/ethernet/altera/Kconfig"
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source "drivers/net/ethernet/amd/Kconfig"
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source "drivers/net/ethernet/apm/Kconfig"
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source "drivers/net/ethernet/apple/Kconfig"
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source "drivers/net/ethernet/arc/Kconfig"
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source "drivers/net/ethernet/atheros/Kconfig"
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@@ -10,6 +10,7 @@ obj-$(CONFIG_NET_VENDOR_ALLWINNER) += allwinner/
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obj-$(CONFIG_NET_VENDOR_ALTEON) += alteon/
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obj-$(CONFIG_ALTERA_TSE) += altera/
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obj-$(CONFIG_NET_VENDOR_AMD) += amd/
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obj-$(CONFIG_NET_XGENE) += apm/
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obj-$(CONFIG_NET_VENDOR_APPLE) += apple/
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obj-$(CONFIG_NET_VENDOR_ARC) += arc/
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obj-$(CONFIG_NET_VENDOR_ATHEROS) += atheros/
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@@ -0,0 +1 @@
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source "drivers/net/ethernet/apm/xgene/Kconfig"
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@@ -0,0 +1,5 @@
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#
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# Makefile for APM X-GENE Ethernet driver.
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#
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obj-$(CONFIG_NET_XGENE) += xgene/
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@@ -0,0 +1,9 @@
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config NET_XGENE
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tristate "APM X-Gene SoC Ethernet Driver"
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select PHYLIB
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help
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This is the Ethernet driver for the on-chip ethernet interface on the
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APM X-Gene SoC.
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To compile this driver as a module, choose M here. This module will
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be called xgene_enet.
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@@ -0,0 +1,6 @@
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#
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# Makefile for APM X-Gene Ethernet Driver.
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#
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xgene-enet-objs := xgene_enet_hw.o xgene_enet_main.o xgene_enet_ethtool.o
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obj-$(CONFIG_NET_XGENE) += xgene-enet.o
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@@ -0,0 +1,125 @@
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/* Applied Micro X-Gene SoC Ethernet Driver
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*
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* Copyright (c) 2014, Applied Micro Circuits Corporation
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* Authors: Iyappan Subramanian <isubramanian@apm.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/ethtool.h>
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#include "xgene_enet_main.h"
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struct xgene_gstrings_stats {
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char name[ETH_GSTRING_LEN];
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int offset;
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};
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#define XGENE_STAT(m) { #m, offsetof(struct xgene_enet_pdata, stats.m) }
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static const struct xgene_gstrings_stats gstrings_stats[] = {
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XGENE_STAT(rx_packets),
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XGENE_STAT(tx_packets),
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XGENE_STAT(rx_bytes),
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XGENE_STAT(tx_bytes),
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XGENE_STAT(rx_errors),
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XGENE_STAT(tx_errors),
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XGENE_STAT(rx_length_errors),
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XGENE_STAT(rx_crc_errors),
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XGENE_STAT(rx_frame_errors),
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XGENE_STAT(rx_fifo_errors)
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};
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#define XGENE_STATS_LEN ARRAY_SIZE(gstrings_stats)
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static void xgene_get_drvinfo(struct net_device *ndev,
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struct ethtool_drvinfo *info)
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{
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struct xgene_enet_pdata *pdata = netdev_priv(ndev);
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struct platform_device *pdev = pdata->pdev;
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strcpy(info->driver, "xgene_enet");
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strcpy(info->version, XGENE_DRV_VERSION);
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snprintf(info->fw_version, ETHTOOL_FWVERS_LEN, "N/A");
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sprintf(info->bus_info, "%s", pdev->name);
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}
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static int xgene_get_settings(struct net_device *ndev, struct ethtool_cmd *cmd)
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{
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struct xgene_enet_pdata *pdata = netdev_priv(ndev);
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struct phy_device *phydev = pdata->phy_dev;
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if (phydev == NULL)
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return -ENODEV;
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return phy_ethtool_gset(phydev, cmd);
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}
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static int xgene_set_settings(struct net_device *ndev, struct ethtool_cmd *cmd)
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{
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struct xgene_enet_pdata *pdata = netdev_priv(ndev);
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struct phy_device *phydev = pdata->phy_dev;
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if (phydev == NULL)
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return -ENODEV;
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return phy_ethtool_sset(phydev, cmd);
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}
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static void xgene_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
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{
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int i;
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u8 *p = data;
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if (stringset != ETH_SS_STATS)
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return;
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for (i = 0; i < XGENE_STATS_LEN; i++) {
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memcpy(p, gstrings_stats[i].name, ETH_GSTRING_LEN);
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p += ETH_GSTRING_LEN;
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}
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}
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static int xgene_get_sset_count(struct net_device *ndev, int sset)
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{
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if (sset != ETH_SS_STATS)
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return -EINVAL;
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return XGENE_STATS_LEN;
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}
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static void xgene_get_ethtool_stats(struct net_device *ndev,
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struct ethtool_stats *dummy,
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u64 *data)
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{
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void *pdata = netdev_priv(ndev);
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int i;
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for (i = 0; i < XGENE_STATS_LEN; i++)
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*data++ = *(u64 *)(pdata + gstrings_stats[i].offset);
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}
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static const struct ethtool_ops xgene_ethtool_ops = {
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.get_drvinfo = xgene_get_drvinfo,
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.get_settings = xgene_get_settings,
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.set_settings = xgene_set_settings,
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.get_link = ethtool_op_get_link,
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.get_strings = xgene_get_strings,
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.get_sset_count = xgene_get_sset_count,
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.get_ethtool_stats = xgene_get_ethtool_stats
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};
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void xgene_enet_set_ethtool_ops(struct net_device *ndev)
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{
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ndev->ethtool_ops = &xgene_ethtool_ops;
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}
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,337 @@
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/* Applied Micro X-Gene SoC Ethernet Driver
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*
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* Copyright (c) 2014, Applied Micro Circuits Corporation
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* Authors: Iyappan Subramanian <isubramanian@apm.com>
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* Ravi Patel <rapatel@apm.com>
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* Keyur Chudgar <kchudgar@apm.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __XGENE_ENET_HW_H__
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#define __XGENE_ENET_HW_H__
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#include "xgene_enet_main.h"
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struct xgene_enet_pdata;
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struct xgene_enet_stats;
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/* clears and then set bits */
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static inline void xgene_set_bits(u32 *dst, u32 val, u32 start, u32 len)
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{
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u32 end = start + len - 1;
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u32 mask = GENMASK(end, start);
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*dst &= ~mask;
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*dst |= (val << start) & mask;
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}
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static inline u32 xgene_get_bits(u32 val, u32 start, u32 end)
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{
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return (val & GENMASK(end, start)) >> start;
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}
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#define CSR_RING_ID 0x0008
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#define OVERWRITE BIT(31)
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#define IS_BUFFER_POOL BIT(20)
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#define PREFETCH_BUF_EN BIT(21)
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#define CSR_RING_ID_BUF 0x000c
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#define CSR_RING_NE_INT_MODE 0x017c
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#define CSR_RING_CONFIG 0x006c
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#define CSR_RING_WR_BASE 0x0070
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#define NUM_RING_CONFIG 5
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#define BUFPOOL_MODE 3
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#define RM3 3
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#define INC_DEC_CMD_ADDR 0x002c
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#define UDP_HDR_SIZE 2
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#define BUF_LEN_CODE_2K 0x5000
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#define CREATE_MASK(pos, len) GENMASK((pos)+(len)-1, (pos))
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#define CREATE_MASK_ULL(pos, len) GENMASK_ULL((pos)+(len)-1, (pos))
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/* Empty slot soft signature */
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#define EMPTY_SLOT_INDEX 1
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#define EMPTY_SLOT ~0ULL
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#define WORK_DESC_SIZE 32
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#define BUFPOOL_DESC_SIZE 16
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#define RING_OWNER_MASK GENMASK(9, 6)
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#define RING_BUFNUM_MASK GENMASK(5, 0)
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#define SELTHRSH_POS 3
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#define SELTHRSH_LEN 3
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#define RINGADDRL_POS 5
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#define RINGADDRL_LEN 27
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#define RINGADDRH_POS 0
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#define RINGADDRH_LEN 6
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#define RINGSIZE_POS 23
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#define RINGSIZE_LEN 3
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#define RINGTYPE_POS 19
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#define RINGTYPE_LEN 2
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#define RINGMODE_POS 20
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#define RINGMODE_LEN 3
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#define RECOMTIMEOUTL_POS 28
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#define RECOMTIMEOUTL_LEN 3
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#define RECOMTIMEOUTH_POS 0
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#define RECOMTIMEOUTH_LEN 2
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#define NUMMSGSINQ_POS 1
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#define NUMMSGSINQ_LEN 16
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#define ACCEPTLERR BIT(19)
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#define QCOHERENT BIT(4)
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#define RECOMBBUF BIT(27)
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#define BLOCK_ETH_CSR_OFFSET 0x2000
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#define BLOCK_ETH_RING_IF_OFFSET 0x9000
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#define BLOCK_ETH_CLKRST_CSR_OFFSET 0xC000
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#define BLOCK_ETH_DIAG_CSR_OFFSET 0xD000
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#define BLOCK_ETH_MAC_OFFSET 0x0000
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#define BLOCK_ETH_STATS_OFFSET 0x0014
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#define BLOCK_ETH_MAC_CSR_OFFSET 0x2800
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#define MAC_ADDR_REG_OFFSET 0x00
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#define MAC_COMMAND_REG_OFFSET 0x04
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#define MAC_WRITE_REG_OFFSET 0x08
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#define MAC_READ_REG_OFFSET 0x0c
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#define MAC_COMMAND_DONE_REG_OFFSET 0x10
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#define STAT_ADDR_REG_OFFSET 0x00
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#define STAT_COMMAND_REG_OFFSET 0x04
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#define STAT_WRITE_REG_OFFSET 0x08
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#define STAT_READ_REG_OFFSET 0x0c
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#define STAT_COMMAND_DONE_REG_OFFSET 0x10
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#define MII_MGMT_CONFIG_ADDR 0x20
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#define MII_MGMT_COMMAND_ADDR 0x24
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#define MII_MGMT_ADDRESS_ADDR 0x28
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#define MII_MGMT_CONTROL_ADDR 0x2c
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#define MII_MGMT_STATUS_ADDR 0x30
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#define MII_MGMT_INDICATORS_ADDR 0x34
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#define BUSY_MASK BIT(0)
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#define READ_CYCLE_MASK BIT(0)
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#define PHY_CONTROL_SET(dst, val) xgene_set_bits(dst, val, 0, 16)
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#define ENET_SPARE_CFG_REG_ADDR 0x0750
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#define RSIF_CONFIG_REG_ADDR 0x0010
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#define RSIF_RAM_DBG_REG0_ADDR 0x0048
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#define RGMII_REG_0_ADDR 0x07e0
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#define CFG_LINK_AGGR_RESUME_0_ADDR 0x07c8
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#define DEBUG_REG_ADDR 0x0700
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#define CFG_BYPASS_ADDR 0x0294
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#define CLE_BYPASS_REG0_0_ADDR 0x0490
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#define CLE_BYPASS_REG1_0_ADDR 0x0494
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#define CFG_RSIF_FPBUFF_TIMEOUT_EN BIT(31)
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#define RESUME_TX BIT(0)
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#define CFG_SPEED_1250 BIT(24)
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#define TX_PORT0 BIT(0)
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#define CFG_BYPASS_UNISEC_TX BIT(2)
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#define CFG_BYPASS_UNISEC_RX BIT(1)
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#define CFG_CLE_BYPASS_EN0 BIT(31)
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#define CFG_TXCLK_MUXSEL0_SET(dst, val) xgene_set_bits(dst, val, 29, 3)
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#define CFG_CLE_IP_PROTOCOL0_SET(dst, val) xgene_set_bits(dst, val, 16, 2)
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#define CFG_CLE_DSTQID0_SET(dst, val) xgene_set_bits(dst, val, 0, 12)
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#define CFG_CLE_FPSEL0_SET(dst, val) xgene_set_bits(dst, val, 16, 4)
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#define CFG_MACMODE_SET(dst, val) xgene_set_bits(dst, val, 18, 2)
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#define CFG_WAITASYNCRD_SET(dst, val) xgene_set_bits(dst, val, 0, 16)
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#define ICM_CONFIG0_REG_0_ADDR 0x0400
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#define ICM_CONFIG2_REG_0_ADDR 0x0410
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#define RX_DV_GATE_REG_0_ADDR 0x05fc
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#define TX_DV_GATE_EN0 BIT(2)
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#define RX_DV_GATE_EN0 BIT(1)
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#define RESUME_RX0 BIT(0)
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#define ENET_CFGSSQMIWQASSOC_ADDR 0xe0
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#define ENET_CFGSSQMIFPQASSOC_ADDR 0xdc
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#define ENET_CFGSSQMIQMLITEFPQASSOC_ADDR 0xf0
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#define ENET_CFGSSQMIQMLITEWQASSOC_ADDR 0xf4
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#define ENET_CFG_MEM_RAM_SHUTDOWN_ADDR 0x70
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#define ENET_BLOCK_MEM_RDY_ADDR 0x74
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#define MAC_CONFIG_1_ADDR 0x00
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#define MAC_CONFIG_2_ADDR 0x04
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#define MAX_FRAME_LEN_ADDR 0x10
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#define INTERFACE_CONTROL_ADDR 0x38
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#define STATION_ADDR0_ADDR 0x40
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#define STATION_ADDR1_ADDR 0x44
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#define PHY_ADDR_SET(dst, val) xgene_set_bits(dst, val, 8, 5)
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#define REG_ADDR_SET(dst, val) xgene_set_bits(dst, val, 0, 5)
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#define ENET_INTERFACE_MODE2_SET(dst, val) xgene_set_bits(dst, val, 8, 2)
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#define MGMT_CLOCK_SEL_SET(dst, val) xgene_set_bits(dst, val, 0, 3)
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#define SOFT_RESET1 BIT(31)
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#define TX_EN BIT(0)
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#define RX_EN BIT(2)
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#define ENET_LHD_MODE BIT(25)
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#define ENET_GHD_MODE BIT(26)
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#define FULL_DUPLEX2 BIT(0)
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#define SCAN_AUTO_INCR BIT(5)
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#define TBYT_ADDR 0x38
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#define TPKT_ADDR 0x39
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#define TDRP_ADDR 0x45
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#define TFCS_ADDR 0x47
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#define TUND_ADDR 0x4a
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#define TSO_IPPROTO_TCP 1
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#define FULL_DUPLEX 2
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#define USERINFO_POS 0
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#define USERINFO_LEN 32
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#define FPQNUM_POS 32
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#define FPQNUM_LEN 12
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#define LERR_POS 60
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#define LERR_LEN 3
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#define STASH_POS 52
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#define STASH_LEN 2
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#define BUFDATALEN_POS 48
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#define BUFDATALEN_LEN 12
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#define DATAADDR_POS 0
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#define DATAADDR_LEN 42
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#define COHERENT_POS 63
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#define HENQNUM_POS 48
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#define HENQNUM_LEN 12
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#define TYPESEL_POS 44
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#define TYPESEL_LEN 4
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#define ETHHDR_POS 12
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#define ETHHDR_LEN 8
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#define IC_POS 35 /* Insert CRC */
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#define TCPHDR_POS 0
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#define TCPHDR_LEN 6
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#define IPHDR_POS 6
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#define IPHDR_LEN 6
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#define EC_POS 22 /* Enable checksum */
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#define EC_LEN 1
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#define IS_POS 24 /* IP protocol select */
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#define IS_LEN 1
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#define TYPE_ETH_WORK_MESSAGE_POS 44
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struct xgene_enet_raw_desc {
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__le64 m0;
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__le64 m1;
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__le64 m2;
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__le64 m3;
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};
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struct xgene_enet_raw_desc16 {
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__le64 m0;
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__le64 m1;
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};
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static inline void xgene_enet_mark_desc_slot_empty(void *desc_slot_ptr)
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{
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__le64 *desc_slot = desc_slot_ptr;
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desc_slot[EMPTY_SLOT_INDEX] = cpu_to_le64(EMPTY_SLOT);
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}
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static inline bool xgene_enet_is_desc_slot_empty(void *desc_slot_ptr)
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{
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__le64 *desc_slot = desc_slot_ptr;
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|
||||
return (desc_slot[EMPTY_SLOT_INDEX] == cpu_to_le64(EMPTY_SLOT));
|
||||
}
|
||||
|
||||
enum xgene_enet_ring_cfgsize {
|
||||
RING_CFGSIZE_512B,
|
||||
RING_CFGSIZE_2KB,
|
||||
RING_CFGSIZE_16KB,
|
||||
RING_CFGSIZE_64KB,
|
||||
RING_CFGSIZE_512KB,
|
||||
RING_CFGSIZE_INVALID
|
||||
};
|
||||
|
||||
enum xgene_enet_ring_type {
|
||||
RING_DISABLED,
|
||||
RING_REGULAR,
|
||||
RING_BUFPOOL
|
||||
};
|
||||
|
||||
enum xgene_ring_owner {
|
||||
RING_OWNER_ETH0,
|
||||
RING_OWNER_CPU = 15,
|
||||
RING_OWNER_INVALID
|
||||
};
|
||||
|
||||
enum xgene_enet_ring_bufnum {
|
||||
RING_BUFNUM_REGULAR = 0x0,
|
||||
RING_BUFNUM_BUFPOOL = 0x20,
|
||||
RING_BUFNUM_INVALID
|
||||
};
|
||||
|
||||
enum xgene_enet_cmd {
|
||||
XGENE_ENET_WR_CMD = BIT(31),
|
||||
XGENE_ENET_RD_CMD = BIT(30)
|
||||
};
|
||||
|
||||
enum xgene_enet_err_code {
|
||||
HBF_READ_DATA = 3,
|
||||
HBF_LL_READ = 4,
|
||||
BAD_WORK_MSG = 6,
|
||||
BUFPOOL_TIMEOUT = 15,
|
||||
INGRESS_CRC = 16,
|
||||
INGRESS_CHECKSUM = 17,
|
||||
INGRESS_TRUNC_FRAME = 18,
|
||||
INGRESS_PKT_LEN = 19,
|
||||
INGRESS_PKT_UNDER = 20,
|
||||
INGRESS_FIFO_OVERRUN = 21,
|
||||
INGRESS_CHECKSUM_COMPUTE = 26,
|
||||
ERR_CODE_INVALID
|
||||
};
|
||||
|
||||
static inline enum xgene_ring_owner xgene_enet_ring_owner(u16 id)
|
||||
{
|
||||
return (id & RING_OWNER_MASK) >> 6;
|
||||
}
|
||||
|
||||
static inline u8 xgene_enet_ring_bufnum(u16 id)
|
||||
{
|
||||
return id & RING_BUFNUM_MASK;
|
||||
}
|
||||
|
||||
static inline bool xgene_enet_is_bufpool(u16 id)
|
||||
{
|
||||
return ((id & RING_BUFNUM_MASK) >= 0x20) ? true : false;
|
||||
}
|
||||
|
||||
static inline u16 xgene_enet_get_numslots(u16 id, u32 size)
|
||||
{
|
||||
bool is_bufpool = xgene_enet_is_bufpool(id);
|
||||
|
||||
return (is_bufpool) ? size / BUFPOOL_DESC_SIZE :
|
||||
size / WORK_DESC_SIZE;
|
||||
}
|
||||
|
||||
struct xgene_enet_desc_ring *xgene_enet_setup_ring(
|
||||
struct xgene_enet_desc_ring *ring);
|
||||
void xgene_enet_clear_ring(struct xgene_enet_desc_ring *ring);
|
||||
void xgene_enet_parse_error(struct xgene_enet_desc_ring *ring,
|
||||
struct xgene_enet_pdata *pdata,
|
||||
enum xgene_enet_err_code status);
|
||||
|
||||
void xgene_enet_reset(struct xgene_enet_pdata *priv);
|
||||
void xgene_gmac_reset(struct xgene_enet_pdata *priv);
|
||||
void xgene_gmac_init(struct xgene_enet_pdata *priv, int speed);
|
||||
void xgene_gmac_tx_enable(struct xgene_enet_pdata *priv);
|
||||
void xgene_gmac_rx_enable(struct xgene_enet_pdata *priv);
|
||||
void xgene_gmac_tx_disable(struct xgene_enet_pdata *priv);
|
||||
void xgene_gmac_rx_disable(struct xgene_enet_pdata *priv);
|
||||
void xgene_gmac_set_mac_addr(struct xgene_enet_pdata *pdata);
|
||||
void xgene_enet_cle_bypass(struct xgene_enet_pdata *pdata,
|
||||
u32 dst_ring_num, u16 bufpool_id);
|
||||
void xgene_gport_shutdown(struct xgene_enet_pdata *priv);
|
||||
void xgene_gmac_get_tx_stats(struct xgene_enet_pdata *pdata);
|
||||
|
||||
int xgene_enet_mdio_config(struct xgene_enet_pdata *pdata);
|
||||
void xgene_enet_mdio_remove(struct xgene_enet_pdata *pdata);
|
||||
|
||||
#endif /* __XGENE_ENET_HW_H__ */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,135 @@
|
||||
/* Applied Micro X-Gene SoC Ethernet Driver
|
||||
*
|
||||
* Copyright (c) 2014, Applied Micro Circuits Corporation
|
||||
* Authors: Iyappan Subramanian <isubramanian@apm.com>
|
||||
* Ravi Patel <rapatel@apm.com>
|
||||
* Keyur Chudgar <kchudgar@apm.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef __XGENE_ENET_MAIN_H__
|
||||
#define __XGENE_ENET_MAIN_H__
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/of_net.h>
|
||||
#include <linux/of_mdio.h>
|
||||
#include <linux/module.h>
|
||||
#include <net/ip.h>
|
||||
#include <linux/prefetch.h>
|
||||
#include <linux/if_vlan.h>
|
||||
#include <linux/phy.h>
|
||||
#include "xgene_enet_hw.h"
|
||||
|
||||
#define XGENE_DRV_VERSION "v1.0"
|
||||
#define XGENE_ENET_MAX_MTU 1536
|
||||
#define SKB_BUFFER_SIZE (XGENE_ENET_MAX_MTU - NET_IP_ALIGN)
|
||||
#define NUM_PKT_BUF 64
|
||||
#define NUM_BUFPOOL 32
|
||||
|
||||
/* software context of a descriptor ring */
|
||||
struct xgene_enet_desc_ring {
|
||||
struct net_device *ndev;
|
||||
u16 id;
|
||||
u16 num;
|
||||
u16 head;
|
||||
u16 tail;
|
||||
u16 slots;
|
||||
u16 irq;
|
||||
u32 size;
|
||||
u32 state[NUM_RING_CONFIG];
|
||||
void __iomem *cmd_base;
|
||||
void __iomem *cmd;
|
||||
dma_addr_t dma;
|
||||
u16 dst_ring_num;
|
||||
u8 nbufpool;
|
||||
struct sk_buff *(*rx_skb);
|
||||
struct sk_buff *(*cp_skb);
|
||||
enum xgene_enet_ring_cfgsize cfgsize;
|
||||
struct xgene_enet_desc_ring *cp_ring;
|
||||
struct xgene_enet_desc_ring *buf_pool;
|
||||
struct napi_struct napi;
|
||||
union {
|
||||
void *desc_addr;
|
||||
struct xgene_enet_raw_desc *raw_desc;
|
||||
struct xgene_enet_raw_desc16 *raw_desc16;
|
||||
};
|
||||
};
|
||||
|
||||
/* ethernet private data */
|
||||
struct xgene_enet_pdata {
|
||||
struct net_device *ndev;
|
||||
struct mii_bus *mdio_bus;
|
||||
struct phy_device *phy_dev;
|
||||
int phy_speed;
|
||||
struct clk *clk;
|
||||
struct platform_device *pdev;
|
||||
struct xgene_enet_desc_ring *tx_ring;
|
||||
struct xgene_enet_desc_ring *rx_ring;
|
||||
char *dev_name;
|
||||
u32 rx_buff_cnt;
|
||||
u32 tx_qcnt_hi;
|
||||
u32 cp_qcnt_hi;
|
||||
u32 cp_qcnt_low;
|
||||
u32 rx_irq;
|
||||
void __iomem *eth_csr_addr;
|
||||
void __iomem *eth_ring_if_addr;
|
||||
void __iomem *eth_diag_csr_addr;
|
||||
void __iomem *mcx_mac_addr;
|
||||
void __iomem *mcx_stats_addr;
|
||||
void __iomem *mcx_mac_csr_addr;
|
||||
void __iomem *base_addr;
|
||||
void __iomem *ring_csr_addr;
|
||||
void __iomem *ring_cmd_addr;
|
||||
u32 phy_addr;
|
||||
int phy_mode;
|
||||
u32 speed;
|
||||
u16 rm;
|
||||
struct rtnl_link_stats64 stats;
|
||||
};
|
||||
|
||||
/* Set the specified value into a bit-field defined by its starting position
|
||||
* and length within a single u64.
|
||||
*/
|
||||
static inline u64 xgene_enet_set_field_value(int pos, int len, u64 val)
|
||||
{
|
||||
return (val & ((1ULL << len) - 1)) << pos;
|
||||
}
|
||||
|
||||
#define SET_VAL(field, val) \
|
||||
xgene_enet_set_field_value(field ## _POS, field ## _LEN, val)
|
||||
|
||||
#define SET_BIT(field) \
|
||||
xgene_enet_set_field_value(field ## _POS, 1, 1)
|
||||
|
||||
/* Get the value from a bit-field defined by its starting position
|
||||
* and length within the specified u64.
|
||||
*/
|
||||
static inline u64 xgene_enet_get_field_value(int pos, int len, u64 src)
|
||||
{
|
||||
return (src >> pos) & ((1ULL << len) - 1);
|
||||
}
|
||||
|
||||
#define GET_VAL(field, src) \
|
||||
xgene_enet_get_field_value(field ## _POS, field ## _LEN, src)
|
||||
|
||||
static inline struct device *ndev_to_dev(struct net_device *ndev)
|
||||
{
|
||||
return ndev->dev.parent;
|
||||
}
|
||||
|
||||
void xgene_enet_set_ethtool_ops(struct net_device *netdev);
|
||||
|
||||
#endif /* __XGENE_ENET_MAIN_H__ */
|
||||
Reference in New Issue
Block a user