From dab9d4a4c782469c72210d6c16bc6bd223edd261 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 9 Jun 2026 16:16:09 +0200 Subject: [PATCH] arm64: dts: qcom: glymur: Drop fake PCIe phy 3B According to user manual / programming guide there is no separate PCIe phy 3A and 3B, but one 8-lane QMP PCIe Gen5 PHY which consists of two 4-lane blocks. This is also visible in memory map, where the 0xf00000 is marked as the main block with additional sub blocks for each 4-lane phys. Describing the sub phys without the rest is not correct from hardware description, even if it works. Link: https://lore.kernel.org/r/20260420-optimistic-unnatural-stingray-80da35@quoll/ Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/glymur-crd.dtsi | 5 --- arch/arm64/boot/dts/qcom/glymur.dtsi | 39 +----------------------- 2 files changed, 1 insertion(+), 43 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi index 50a64ca2c064..a0199fafb7f2 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi @@ -686,11 +686,6 @@ pinctrl-names = "default"; }; -&pcie3b_phy { - vdda-phy-supply = <&vreg_l3c_e1_0p89>; - vdda-pll-supply = <&vreg_l2c_e1_1p14>; -}; - &pcie3b_port0 { reset-gpios = <&tlmm 155 GPIO_ACTIVE_LOW>; wake-gpios = <&tlmm 157 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 12b6f3b031f3..daceca31af60 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -785,7 +785,7 @@ <0>, /* USB 2 Phy PIPEGMUX */ <0>, /* USB 2 Phy SYS PCIE PIPEGMUX */ <0>, /* PCIe 3a */ - <&pcie3b_phy>, /* PCIe 3b */ + <0>, /* PCIe 3b */ <&pcie4_phy>, /* PCIe 4 */ <&pcie5_phy>, /* PCIe 5 */ <&pcie6_phy>, /* PCIe 6 */ @@ -3675,49 +3675,12 @@ reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; - phys = <&pcie3b_phy>; - #address-cells = <3>; #size-cells = <2>; ranges; }; }; - pcie3b_phy: phy@f10000 { - compatible = "qcom,glymur-qmp-gen5x4-pcie-phy"; - reg = <0x0 0x00f10000 0x0 0x10000>; - - clocks = <&gcc GCC_PCIE_PHY_3B_AUX_CLK>, - <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, - <&tcsr TCSR_PCIE_3_CLKREF_EN>, - <&gcc GCC_PCIE_3B_PHY_RCHNG_CLK>, - <&gcc GCC_PCIE_3B_PIPE_CLK>, - <&gcc GCC_PCIE_3B_PIPE_DIV2_CLK>; - clock-names = "aux", - "cfg_ahb", - "ref", - "rchng", - "pipe", - "pipediv2"; - - resets = <&gcc GCC_PCIE_3B_PHY_BCR>, - <&gcc GCC_PCIE_3B_NOCSR_COM_PHY_BCR>; - reset-names = "phy", - "phy_nocsr"; - - assigned-clocks = <&gcc GCC_PCIE_3B_PHY_RCHNG_CLK>; - assigned-clock-rates = <100000000>; - - power-domains = <&gcc GCC_PCIE_3B_PHY_GDSC>; - - #clock-cells = <0>; - clock-output-names = "pcie3b_pipe_clk"; - - #phy-cells = <0>; - - status = "disabled"; - }; - cryptobam: dma-controller@1dc4000 { compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; reg = <0x0 0x01dc4000 0x0 0x28000>;