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media: nxp: Add i.MX8 ISI driver
The Image Sensing Interface (ISI) combines image processing pipelines with DMA engines to process and capture frames originating from a variety of sources. The inputs to the ISI go through Pixel Link interfaces, and their number and nature is SoC-dependent. They cover both capture interfaces (MIPI CSI-2 RX, HDMI RX) and memory inputs. Signed-off-by: Christian Hemp <c.hemp@phytec.de> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Guoniu Zhou <guoniu.zhou@nxp.com> Signed-off-by: Jacopo Mondi <jacopo@jmondi.org> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de> Tested-by: Adam Ford <aford173@gmail.com> #imx8mn-beacon Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
This commit is contained in:
Laurent Pinchart authored and 
Mauro Carvalho Chehab committed
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@@ -14931,6 +14931,13 @@ F: Documentation/devicetree/bindings/clock/imx*
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F: drivers/clk/imx/
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F: include/dt-bindings/clock/imx*
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NXP i.MX 8M ISI DRIVER
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M: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
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L: linux-media@vger.kernel.org
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S: Maintained
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F: Documentation/devicetree/bindings/media/nxp,imx8-isi.yaml
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F: drivers/media/platform/nxp/imx8-isi/
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NXP i.MX 8MQ DCSS DRIVER
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M: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
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R: Lucas Stach <l.stach@pengutronix.de>
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@@ -28,6 +28,8 @@ config VIDEO_IMX_MIPI_CSIS
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Video4Linux2 sub-device driver for the MIPI CSI-2 CSIS receiver
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v3.3/v3.6.3 found on some i.MX7 and i.MX8 SoCs.
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source "drivers/media/platform/nxp/imx8-isi/Kconfig"
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# mem2mem drivers
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config VIDEO_IMX_PXP
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@@ -2,6 +2,7 @@
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obj-y += dw100/
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obj-y += imx-jpeg/
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obj-y += imx8-isi/
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obj-$(CONFIG_VIDEO_IMX7_CSI) += imx7-media-csi.o
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obj-$(CONFIG_VIDEO_IMX_MIPI_CSIS) += imx-mipi-csis.o
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@@ -0,0 +1,22 @@
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# SPDX-License-Identifier: GPL-2.0-only
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config VIDEO_IMX8_ISI
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tristate "i.MX8 Image Sensor Interface (ISI) driver"
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depends on ARCH_MXC || COMPILE_TEST
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depends on HAS_DMA && PM
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depends on VIDEO_DEV
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select MEDIA_CONTROLLER
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select V4L2_FWNODE
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select V4L2_MEM2MEM_DEV if VIDEO_IMX8_ISI_M2M
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select VIDEO_V4L2_SUBDEV_API
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select VIDEOBUF2_DMA_CONTIG
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help
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V4L2 driver for the Image Sensor Interface (ISI) found in various
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i.MX8 SoCs.
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config VIDEO_IMX8_ISI_M2M
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bool "i.MX8 Image Sensor Interface (ISI) memory-to-memory support"
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depends on VIDEO_IMX8_ISI
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help
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Select 'yes' here to enable support for memory-to-memory processing
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in the ISI driver.
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@@ -0,0 +1,8 @@
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# SPDX-License-Identifier: GPL-2.0-only
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imx8-isi-y := imx8-isi-core.o imx8-isi-crossbar.o imx8-isi-hw.o \
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imx8-isi-pipe.o imx8-isi-video.o
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imx8-isi-$(CONFIG_DEBUG_FS) += imx8-isi-debug.o
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imx8-isi-$(CONFIG_VIDEO_IMX8_ISI_M2M) += imx8-isi-m2m.o
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obj-$(CONFIG_VIDEO_IMX8_ISI) += imx8-isi.o
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File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,395 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* V4L2 Capture ISI subdev for i.MX8QXP/QM platform
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*
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* ISI is a Image Sensor Interface of i.MX8QXP/QM platform, which
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* used to process image from camera sensor to memory or DC
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* Copyright 2019-2020 NXP
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*/
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#ifndef __MXC_ISI_CORE_H__
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#define __MXC_ISI_CORE_H__
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#include <linux/list.h>
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#include <linux/mutex.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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#include <linux/videodev2.h>
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#include <media/media-device.h>
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#include <media/media-entity.h>
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#include <media/v4l2-async.h>
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#include <media/v4l2-ctrls.h>
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#include <media/v4l2-dev.h>
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#include <media/v4l2-device.h>
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#include <media/v4l2-subdev.h>
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#include <media/videobuf2-core.h>
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#include <media/videobuf2-v4l2.h>
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struct clk_bulk_data;
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struct dentry;
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struct device;
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struct media_intf_devnode;
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struct regmap;
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struct v4l2_m2m_dev;
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/* Pipeline pads */
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#define MXC_ISI_PIPE_PAD_SINK 0
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#define MXC_ISI_PIPE_PAD_SOURCE 1
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#define MXC_ISI_PIPE_PADS_NUM 2
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#define MXC_ISI_MIN_WIDTH 1U
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#define MXC_ISI_MIN_HEIGHT 1U
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#define MXC_ISI_MAX_WIDTH_UNCHAINED 2048U
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#define MXC_ISI_MAX_WIDTH_CHAINED 4096U
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#define MXC_ISI_MAX_HEIGHT 8191U
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#define MXC_ISI_DEF_WIDTH 1920U
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#define MXC_ISI_DEF_HEIGHT 1080U
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#define MXC_ISI_DEF_MBUS_CODE_SINK MEDIA_BUS_FMT_UYVY8_1X16
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#define MXC_ISI_DEF_MBUS_CODE_SOURCE MEDIA_BUS_FMT_YUV8_1X24
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#define MXC_ISI_DEF_PIXEL_FORMAT V4L2_PIX_FMT_YUYV
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#define MXC_ISI_DEF_COLOR_SPACE V4L2_COLORSPACE_SRGB
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#define MXC_ISI_DEF_YCBCR_ENC V4L2_YCBCR_ENC_601
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#define MXC_ISI_DEF_QUANTIZATION V4L2_QUANTIZATION_LIM_RANGE
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#define MXC_ISI_DEF_XFER_FUNC V4L2_XFER_FUNC_SRGB
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#define MXC_ISI_DRIVER_NAME "mxc-isi"
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#define MXC_ISI_CAPTURE "mxc-isi-cap"
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#define MXC_ISI_M2M "mxc-isi-m2m"
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#define MXC_MAX_PLANES 3
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struct mxc_isi_dev;
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struct mxc_isi_m2m_ctx;
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enum mxc_isi_buf_id {
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MXC_ISI_BUF1 = 0x0,
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MXC_ISI_BUF2,
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};
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enum mxc_isi_encoding {
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MXC_ISI_ENC_RAW,
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MXC_ISI_ENC_RGB,
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MXC_ISI_ENC_YUV,
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};
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enum mxc_isi_input_id {
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/* Inputs from the crossbar switch range from 0 to 15 */
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MXC_ISI_INPUT_MEM = 16,
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};
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enum mxc_isi_video_type {
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MXC_ISI_VIDEO_CAP = BIT(0),
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MXC_ISI_VIDEO_M2M_OUT = BIT(1),
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MXC_ISI_VIDEO_M2M_CAP = BIT(2),
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};
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struct mxc_isi_format_info {
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u32 mbus_code;
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u32 fourcc;
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enum mxc_isi_video_type type;
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u32 isi_in_format;
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u32 isi_out_format;
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u8 mem_planes;
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u8 color_planes;
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u8 depth[MXC_MAX_PLANES];
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u8 hsub;
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u8 vsub;
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enum mxc_isi_encoding encoding;
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};
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struct mxc_isi_bus_format_info {
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u32 mbus_code;
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u32 output;
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u32 pads;
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enum mxc_isi_encoding encoding;
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};
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struct mxc_isi_buffer {
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struct vb2_v4l2_buffer v4l2_buf;
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struct list_head list;
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dma_addr_t dma_addrs[3];
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enum mxc_isi_buf_id id;
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bool discard;
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};
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struct mxc_isi_reg {
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u32 offset;
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u32 mask;
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};
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struct mxc_isi_ier_reg {
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/* Overflow Y/U/V trigger enable*/
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struct mxc_isi_reg oflw_y_buf_en;
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struct mxc_isi_reg oflw_u_buf_en;
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struct mxc_isi_reg oflw_v_buf_en;
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/* Excess overflow Y/U/V trigger enable*/
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struct mxc_isi_reg excs_oflw_y_buf_en;
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struct mxc_isi_reg excs_oflw_u_buf_en;
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struct mxc_isi_reg excs_oflw_v_buf_en;
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/* Panic Y/U/V trigger enable*/
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struct mxc_isi_reg panic_y_buf_en;
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struct mxc_isi_reg panic_v_buf_en;
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struct mxc_isi_reg panic_u_buf_en;
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};
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struct mxc_isi_panic_thd {
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u32 mask;
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u32 offset;
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u32 threshold;
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};
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struct mxc_isi_set_thd {
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struct mxc_isi_panic_thd panic_set_thd_y;
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struct mxc_isi_panic_thd panic_set_thd_u;
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struct mxc_isi_panic_thd panic_set_thd_v;
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};
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enum model {
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MXC_ISI_IMX8,
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MXC_ISI_IMX8MN,
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MXC_ISI_IMX8MP,
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};
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struct mxc_isi_plat_data {
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enum model model;
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unsigned int num_ports;
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unsigned int num_channels;
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unsigned int reg_offset;
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const struct mxc_isi_ier_reg *ier_reg;
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const struct mxc_isi_set_thd *set_thd;
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const struct clk_bulk_data *clks;
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unsigned int num_clks;
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bool buf_active_reverse;
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bool has_gasket;
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bool has_36bit_dma;
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};
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struct mxc_isi_dma_buffer {
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size_t size;
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void *addr;
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dma_addr_t dma;
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};
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struct mxc_isi_input {
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unsigned int enable_count;
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};
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struct mxc_isi_crossbar {
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struct mxc_isi_dev *isi;
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unsigned int num_sinks;
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unsigned int num_sources;
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struct mxc_isi_input *inputs;
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struct v4l2_subdev sd;
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struct media_pad *pads;
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};
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struct mxc_isi_video {
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struct mxc_isi_pipe *pipe;
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struct video_device vdev;
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struct media_pad pad;
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/* Protects is_streaming, and the vdev and vb2_q operations */
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struct mutex lock;
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bool is_streaming;
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struct v4l2_pix_format_mplane pix;
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const struct mxc_isi_format_info *fmtinfo;
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struct {
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struct v4l2_ctrl_handler handler;
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unsigned int alpha;
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bool hflip;
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bool vflip;
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} ctrls;
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struct vb2_queue vb2_q;
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struct mxc_isi_buffer buf_discard[3];
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struct list_head out_pending;
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struct list_head out_active;
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struct list_head out_discard;
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u32 frame_count;
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/* Protects out_pending, out_active, out_discard and frame_count */
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spinlock_t buf_lock;
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struct mxc_isi_dma_buffer discard_buffer[MXC_MAX_PLANES];
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};
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typedef void(*mxc_isi_pipe_irq_t)(struct mxc_isi_pipe *, u32);
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struct mxc_isi_pipe {
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struct mxc_isi_dev *isi;
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u32 id;
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void __iomem *regs;
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struct media_pipeline pipe;
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struct v4l2_subdev sd;
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struct media_pad pads[MXC_ISI_PIPE_PADS_NUM];
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struct mxc_isi_video video;
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/*
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* Protects use_count, irq_handler, res_available, res_acquired,
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* chained_res, and the CHNL_CTRL register.
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*/
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struct mutex lock;
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unsigned int use_count;
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mxc_isi_pipe_irq_t irq_handler;
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#define MXC_ISI_CHANNEL_RES_LINE_BUF BIT(0)
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#define MXC_ISI_CHANNEL_RES_OUTPUT_BUF BIT(1)
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u8 available_res;
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u8 acquired_res;
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u8 chained_res;
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bool chained;
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};
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struct mxc_isi_m2m {
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struct mxc_isi_dev *isi;
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struct mxc_isi_pipe *pipe;
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struct media_pad pad;
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struct video_device vdev;
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struct media_intf_devnode *intf;
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struct v4l2_m2m_dev *m2m_dev;
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/* Protects last_ctx, usage_count and chained_count */
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struct mutex lock;
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struct mxc_isi_m2m_ctx *last_ctx;
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int usage_count;
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int chained_count;
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};
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struct mxc_isi_dev {
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struct device *dev;
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const struct mxc_isi_plat_data *pdata;
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void __iomem *regs;
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struct clk_bulk_data *clks;
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struct regmap *gasket;
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struct mxc_isi_crossbar crossbar;
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struct mxc_isi_pipe *pipes;
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struct mxc_isi_m2m m2m;
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struct media_device media_dev;
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struct v4l2_device v4l2_dev;
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struct v4l2_async_notifier notifier;
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struct dentry *debugfs_root;
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};
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int mxc_isi_crossbar_init(struct mxc_isi_dev *isi);
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void mxc_isi_crossbar_cleanup(struct mxc_isi_crossbar *xbar);
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int mxc_isi_crossbar_register(struct mxc_isi_crossbar *xbar);
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void mxc_isi_crossbar_unregister(struct mxc_isi_crossbar *xbar);
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const struct mxc_isi_bus_format_info *
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mxc_isi_bus_format_by_code(u32 code, unsigned int pad);
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const struct mxc_isi_bus_format_info *
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mxc_isi_bus_format_by_index(unsigned int index, unsigned int pad);
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const struct mxc_isi_format_info *
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mxc_isi_format_by_fourcc(u32 fourcc, enum mxc_isi_video_type type);
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const struct mxc_isi_format_info *
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mxc_isi_format_enum(unsigned int index, enum mxc_isi_video_type type);
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const struct mxc_isi_format_info *
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mxc_isi_format_try(struct mxc_isi_pipe *pipe, struct v4l2_pix_format_mplane *pix,
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enum mxc_isi_video_type type);
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int mxc_isi_pipe_init(struct mxc_isi_dev *isi, unsigned int id);
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void mxc_isi_pipe_cleanup(struct mxc_isi_pipe *pipe);
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int mxc_isi_pipe_acquire(struct mxc_isi_pipe *pipe,
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mxc_isi_pipe_irq_t irq_handler);
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void mxc_isi_pipe_release(struct mxc_isi_pipe *pipe);
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int mxc_isi_pipe_enable(struct mxc_isi_pipe *pipe);
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void mxc_isi_pipe_disable(struct mxc_isi_pipe *pipe);
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int mxc_isi_video_register(struct mxc_isi_pipe *pipe,
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struct v4l2_device *v4l2_dev);
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void mxc_isi_video_unregister(struct mxc_isi_pipe *pipe);
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void mxc_isi_video_suspend(struct mxc_isi_pipe *pipe);
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int mxc_isi_video_resume(struct mxc_isi_pipe *pipe);
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int mxc_isi_video_queue_setup(const struct v4l2_pix_format_mplane *format,
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const struct mxc_isi_format_info *info,
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unsigned int *num_buffers,
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unsigned int *num_planes, unsigned int sizes[]);
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void mxc_isi_video_buffer_init(struct vb2_buffer *vb2, dma_addr_t dma_addrs[3],
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const struct mxc_isi_format_info *info,
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const struct v4l2_pix_format_mplane *pix);
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int mxc_isi_video_buffer_prepare(struct mxc_isi_dev *isi, struct vb2_buffer *vb2,
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const struct mxc_isi_format_info *info,
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const struct v4l2_pix_format_mplane *pix);
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#ifdef CONFIG_VIDEO_IMX8_ISI_M2M
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int mxc_isi_m2m_register(struct mxc_isi_dev *isi, struct v4l2_device *v4l2_dev);
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int mxc_isi_m2m_unregister(struct mxc_isi_dev *isi);
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#else
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static inline int mxc_isi_m2m_register(struct mxc_isi_dev *isi,
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struct v4l2_device *v4l2_dev)
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{
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return 0;
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}
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static inline int mxc_isi_m2m_unregister(struct mxc_isi_dev *isi)
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{
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return 0;
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}
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#endif
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int mxc_isi_channel_acquire(struct mxc_isi_pipe *pipe,
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mxc_isi_pipe_irq_t irq_handler, bool bypass);
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void mxc_isi_channel_release(struct mxc_isi_pipe *pipe);
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void mxc_isi_channel_get(struct mxc_isi_pipe *pipe);
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void mxc_isi_channel_put(struct mxc_isi_pipe *pipe);
|
||||
void mxc_isi_channel_enable(struct mxc_isi_pipe *pipe);
|
||||
void mxc_isi_channel_disable(struct mxc_isi_pipe *pipe);
|
||||
int mxc_isi_channel_chain(struct mxc_isi_pipe *pipe, bool bypass);
|
||||
void mxc_isi_channel_unchain(struct mxc_isi_pipe *pipe);
|
||||
|
||||
void mxc_isi_channel_config(struct mxc_isi_pipe *pipe,
|
||||
enum mxc_isi_input_id input,
|
||||
const struct v4l2_area *in_size,
|
||||
const struct v4l2_area *scale,
|
||||
const struct v4l2_rect *crop,
|
||||
enum mxc_isi_encoding in_encoding,
|
||||
enum mxc_isi_encoding out_encoding);
|
||||
|
||||
void mxc_isi_channel_set_input_format(struct mxc_isi_pipe *pipe,
|
||||
const struct mxc_isi_format_info *info,
|
||||
const struct v4l2_pix_format_mplane *format);
|
||||
void mxc_isi_channel_set_output_format(struct mxc_isi_pipe *pipe,
|
||||
const struct mxc_isi_format_info *info,
|
||||
struct v4l2_pix_format_mplane *format);
|
||||
void mxc_isi_channel_m2m_start(struct mxc_isi_pipe *pipe);
|
||||
|
||||
void mxc_isi_channel_set_alpha(struct mxc_isi_pipe *pipe, u8 alpha);
|
||||
void mxc_isi_channel_set_flip(struct mxc_isi_pipe *pipe, bool hflip, bool vflip);
|
||||
|
||||
void mxc_isi_channel_set_inbuf(struct mxc_isi_pipe *pipe, dma_addr_t dma_addr);
|
||||
void mxc_isi_channel_set_outbuf(struct mxc_isi_pipe *pipe,
|
||||
const dma_addr_t dma_addrs[3],
|
||||
enum mxc_isi_buf_id buf_id);
|
||||
|
||||
u32 mxc_isi_channel_irq_status(struct mxc_isi_pipe *pipe, bool clear);
|
||||
void mxc_isi_channel_irq_clear(struct mxc_isi_pipe *pipe);
|
||||
|
||||
#if IS_ENABLED(CONFIG_DEBUG_FS)
|
||||
void mxc_isi_debug_init(struct mxc_isi_dev *isi);
|
||||
void mxc_isi_debug_cleanup(struct mxc_isi_dev *isi);
|
||||
#else
|
||||
static inline void mxc_isi_debug_init(struct mxc_isi_dev *isi)
|
||||
{
|
||||
}
|
||||
static inline void mxc_isi_debug_cleanup(struct mxc_isi_dev *isi)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __MXC_ISI_CORE_H__ */
|
||||
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,109 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright 2019-2020 NXP
|
||||
*/
|
||||
|
||||
#include <linux/debugfs.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/pm_runtime.h>
|
||||
#include <linux/seq_file.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
#include "imx8-isi-core.h"
|
||||
#include "imx8-isi-regs.h"
|
||||
|
||||
static inline u32 mxc_isi_read(struct mxc_isi_pipe *pipe, u32 reg)
|
||||
{
|
||||
return readl(pipe->regs + reg);
|
||||
}
|
||||
|
||||
static int mxc_isi_debug_dump_regs_show(struct seq_file *m, void *p)
|
||||
{
|
||||
#define MXC_ISI_DEBUG_REG(name) { name, #name }
|
||||
static const struct {
|
||||
u32 offset;
|
||||
const char * const name;
|
||||
} registers[] = {
|
||||
MXC_ISI_DEBUG_REG(CHNL_CTRL),
|
||||
MXC_ISI_DEBUG_REG(CHNL_IMG_CTRL),
|
||||
MXC_ISI_DEBUG_REG(CHNL_OUT_BUF_CTRL),
|
||||
MXC_ISI_DEBUG_REG(CHNL_IMG_CFG),
|
||||
MXC_ISI_DEBUG_REG(CHNL_IER),
|
||||
MXC_ISI_DEBUG_REG(CHNL_STS),
|
||||
MXC_ISI_DEBUG_REG(CHNL_SCALE_FACTOR),
|
||||
MXC_ISI_DEBUG_REG(CHNL_SCALE_OFFSET),
|
||||
MXC_ISI_DEBUG_REG(CHNL_CROP_ULC),
|
||||
MXC_ISI_DEBUG_REG(CHNL_CROP_LRC),
|
||||
MXC_ISI_DEBUG_REG(CHNL_CSC_COEFF0),
|
||||
MXC_ISI_DEBUG_REG(CHNL_CSC_COEFF1),
|
||||
MXC_ISI_DEBUG_REG(CHNL_CSC_COEFF2),
|
||||
MXC_ISI_DEBUG_REG(CHNL_CSC_COEFF3),
|
||||
MXC_ISI_DEBUG_REG(CHNL_CSC_COEFF4),
|
||||
MXC_ISI_DEBUG_REG(CHNL_CSC_COEFF5),
|
||||
MXC_ISI_DEBUG_REG(CHNL_ROI_0_ALPHA),
|
||||
MXC_ISI_DEBUG_REG(CHNL_ROI_0_ULC),
|
||||
MXC_ISI_DEBUG_REG(CHNL_ROI_0_LRC),
|
||||
MXC_ISI_DEBUG_REG(CHNL_ROI_1_ALPHA),
|
||||
MXC_ISI_DEBUG_REG(CHNL_ROI_1_ULC),
|
||||
MXC_ISI_DEBUG_REG(CHNL_ROI_1_LRC),
|
||||
MXC_ISI_DEBUG_REG(CHNL_ROI_2_ALPHA),
|
||||
MXC_ISI_DEBUG_REG(CHNL_ROI_2_ULC),
|
||||
MXC_ISI_DEBUG_REG(CHNL_ROI_2_LRC),
|
||||
MXC_ISI_DEBUG_REG(CHNL_ROI_3_ALPHA),
|
||||
MXC_ISI_DEBUG_REG(CHNL_ROI_3_ULC),
|
||||
MXC_ISI_DEBUG_REG(CHNL_ROI_3_LRC),
|
||||
MXC_ISI_DEBUG_REG(CHNL_OUT_BUF1_ADDR_Y),
|
||||
MXC_ISI_DEBUG_REG(CHNL_OUT_BUF1_ADDR_U),
|
||||
MXC_ISI_DEBUG_REG(CHNL_OUT_BUF1_ADDR_V),
|
||||
MXC_ISI_DEBUG_REG(CHNL_OUT_BUF_PITCH),
|
||||
MXC_ISI_DEBUG_REG(CHNL_IN_BUF_ADDR),
|
||||
MXC_ISI_DEBUG_REG(CHNL_IN_BUF_PITCH),
|
||||
MXC_ISI_DEBUG_REG(CHNL_MEM_RD_CTRL),
|
||||
MXC_ISI_DEBUG_REG(CHNL_OUT_BUF2_ADDR_Y),
|
||||
MXC_ISI_DEBUG_REG(CHNL_OUT_BUF2_ADDR_U),
|
||||
MXC_ISI_DEBUG_REG(CHNL_OUT_BUF2_ADDR_V),
|
||||
MXC_ISI_DEBUG_REG(CHNL_SCL_IMG_CFG),
|
||||
MXC_ISI_DEBUG_REG(CHNL_FLOW_CTRL),
|
||||
};
|
||||
|
||||
struct mxc_isi_pipe *pipe = m->private;
|
||||
unsigned int i;
|
||||
|
||||
if (!pm_runtime_get_if_in_use(pipe->isi->dev))
|
||||
return 0;
|
||||
|
||||
seq_printf(m, "--- ISI pipe %u registers ---\n", pipe->id);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(registers); ++i)
|
||||
seq_printf(m, "%20s[0x%02x]: 0x%08x\n",
|
||||
registers[i].name, registers[i].offset,
|
||||
mxc_isi_read(pipe, registers[i].offset));
|
||||
|
||||
pm_runtime_put(pipe->isi->dev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
DEFINE_SHOW_ATTRIBUTE(mxc_isi_debug_dump_regs);
|
||||
|
||||
void mxc_isi_debug_init(struct mxc_isi_dev *isi)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
isi->debugfs_root = debugfs_create_dir(dev_name(isi->dev), NULL);
|
||||
|
||||
for (i = 0; i < isi->pdata->num_channels; ++i) {
|
||||
struct mxc_isi_pipe *pipe = &isi->pipes[i];
|
||||
char name[8];
|
||||
|
||||
sprintf(name, "pipe%u", pipe->id);
|
||||
debugfs_create_file(name, 0444, isi->debugfs_root, pipe,
|
||||
&mxc_isi_debug_dump_regs_fops);
|
||||
}
|
||||
}
|
||||
|
||||
void mxc_isi_debug_cleanup(struct mxc_isi_dev *isi)
|
||||
{
|
||||
debugfs_remove_recursive(isi->debugfs_root);
|
||||
}
|
||||
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
File diff suppressed because it is too large.
Load diff
@@ -0,0 +1,418 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright 2019-2020 NXP
|
||||
*/
|
||||
|
||||
#ifndef __IMX8_ISI_REGS_H__
|
||||
#define __IMX8_ISI_REGS_H__
|
||||
|
||||
#include <linux/bits.h>
|
||||
|
||||
/* ISI Registers Define */
|
||||
/* Channel Control Register */
|
||||
#define CHNL_CTRL 0x0000
|
||||
#define CHNL_CTRL_CHNL_EN BIT(31)
|
||||
#define CHNL_CTRL_CLK_EN BIT(30)
|
||||
#define CHNL_CTRL_CHNL_BYPASS BIT(29)
|
||||
#define CHNL_CTRL_CHAIN_BUF(n) ((n) << 25)
|
||||
#define CHNL_CTRL_CHAIN_BUF_MASK GENMASK(26, 25)
|
||||
#define CHNL_CTRL_CHAIN_BUF_NO_CHAIN 0
|
||||
#define CHNL_CTRL_CHAIN_BUF_2_CHAIN 1
|
||||
#define CHNL_CTRL_SW_RST BIT(24)
|
||||
#define CHNL_CTRL_BLANK_PXL(n) ((n) << 16)
|
||||
#define CHNL_CTRL_BLANK_PXL_MASK GENMASK(23, 16)
|
||||
#define CHNL_CTRL_MIPI_VC_ID(n) ((n) << 6)
|
||||
#define CHNL_CTRL_MIPI_VC_ID_MASK GENMASK(7, 6)
|
||||
#define CHNL_CTRL_SRC_TYPE(n) ((n) << 4)
|
||||
#define CHNL_CTRL_SRC_TYPE_MASK BIT(4)
|
||||
#define CHNL_CTRL_SRC_TYPE_DEVICE 0
|
||||
#define CHNL_CTRL_SRC_TYPE_MEMORY 1
|
||||
#define CHNL_CTRL_SRC_INPUT(n) ((n) << 0)
|
||||
#define CHNL_CTRL_SRC_INPUT_MASK GENMASK(2, 0)
|
||||
|
||||
/* Channel Image Control Register */
|
||||
#define CHNL_IMG_CTRL 0x0004
|
||||
#define CHNL_IMG_CTRL_FORMAT(n) ((n) << 24)
|
||||
#define CHNL_IMG_CTRL_FORMAT_MASK GENMASK(29, 24)
|
||||
#define CHNL_IMG_CTRL_FORMAT_RGBA8888 0x00
|
||||
#define CHNL_IMG_CTRL_FORMAT_ABGR8888 0x01
|
||||
#define CHNL_IMG_CTRL_FORMAT_ARGB8888 0x02
|
||||
#define CHNL_IMG_CTRL_FORMAT_RGBX888 0x03
|
||||
#define CHNL_IMG_CTRL_FORMAT_XBGR888 0x04
|
||||
#define CHNL_IMG_CTRL_FORMAT_XRGB888 0x05
|
||||
#define CHNL_IMG_CTRL_FORMAT_RGB888P 0x06
|
||||
#define CHNL_IMG_CTRL_FORMAT_BGR888P 0x07
|
||||
#define CHNL_IMG_CTRL_FORMAT_A2BGR10 0x08
|
||||
#define CHNL_IMG_CTRL_FORMAT_A2RGB10 0x09
|
||||
#define CHNL_IMG_CTRL_FORMAT_RGB565 0x0a
|
||||
#define CHNL_IMG_CTRL_FORMAT_RAW8 0x0b
|
||||
#define CHNL_IMG_CTRL_FORMAT_RAW10 0x0c
|
||||
#define CHNL_IMG_CTRL_FORMAT_RAW10P 0x0d
|
||||
#define CHNL_IMG_CTRL_FORMAT_RAW12 0x0e
|
||||
#define CHNL_IMG_CTRL_FORMAT_RAW16 0x0f
|
||||
#define CHNL_IMG_CTRL_FORMAT_YUV444_1P8P 0x10
|
||||
#define CHNL_IMG_CTRL_FORMAT_YUV444_2P8P 0x11
|
||||
#define CHNL_IMG_CTRL_FORMAT_YUV444_3P8P 0x12
|
||||
#define CHNL_IMG_CTRL_FORMAT_YUV444_1P8 0x13
|
||||
#define CHNL_IMG_CTRL_FORMAT_YUV444_1P10 0x14
|
||||
#define CHNL_IMG_CTRL_FORMAT_YUV444_2P10 0x15
|
||||
#define CHNL_IMG_CTRL_FORMAT_YUV444_3P10 0x16
|
||||
#define CHNL_IMG_CTRL_FORMAT_YUV444_1P10P 0x18
|
||||
#define CHNL_IMG_CTRL_FORMAT_YUV444_2P10P 0x19
|
||||
#define CHNL_IMG_CTRL_FORMAT_YUV444_3P10P 0x1a
|
||||
#define CHNL_IMG_CTRL_FORMAT_YUV444_1P12 0x1c
|
||||
#define CHNL_IMG_CTRL_FORMAT_YUV444_2P12 0x1d
|
||||
#define CHNL_IMG_CTRL_FORMAT_YUV444_3P12 0x1e
|
||||
#define CHNL_IMG_CTRL_FORMAT_YUV422_1P8P 0x20
|
||||
#define CHNL_IMG_CTRL_FORMAT_YUV422_2P8P 0x21
|
||||
#define CHNL_IMG_CTRL_FORMAT_YUV422_3P8P 0x22
|
||||
#define CHNL_IMG_CTRL_FORMAT_YUV422_1P10 0x24
|
||||
#define CHNL_IMG_CTRL_FORMAT_YUV422_2P10 0x25
|
||||
#define CHNL_IMG_CTRL_FORMAT_YUV422_3P10 0x26
|
||||
#define CHNL_IMG_CTRL_FORMAT_YUV422_1P10P 0x28
|
||||
#define CHNL_IMG_CTRL_FORMAT_YUV422_2P10P 0x29
|
||||
#define CHNL_IMG_CTRL_FORMAT_YUV422_3P10P 0x2a
|
||||
#define CHNL_IMG_CTRL_FORMAT_YUV422_1P12 0x2c
|
||||
#define CHNL_IMG_CTRL_FORMAT_YUV422_2P12 0x2d
|
||||
#define CHNL_IMG_CTRL_FORMAT_YUV422_3P12 0x2e
|
||||
#define CHNL_IMG_CTRL_FORMAT_YUV420_2P8P 0x31
|
||||
#define CHNL_IMG_CTRL_FORMAT_YUV420_3P8P 0x32
|
||||
#define CHNL_IMG_CTRL_FORMAT_YUV420_2P10 0x35
|
||||
#define CHNL_IMG_CTRL_FORMAT_YUV420_3P10 0x36
|
||||
#define CHNL_IMG_CTRL_FORMAT_YUV420_2P10P 0x39
|
||||
#define CHNL_IMG_CTRL_FORMAT_YUV420_3P10P 0x3a
|
||||
#define CHNL_IMG_CTRL_FORMAT_YUV420_2P12 0x3d
|
||||
#define CHNL_IMG_CTRL_FORMAT_YUV420_3P12 0x3e
|
||||
#define CHNL_IMG_CTRL_GBL_ALPHA_VAL(n) ((n) << 16)
|
||||
#define CHNL_IMG_CTRL_GBL_ALPHA_VAL_MASK GENMASK(23, 16)
|
||||
#define CHNL_IMG_CTRL_GBL_ALPHA_EN BIT(15)
|
||||
#define CHNL_IMG_CTRL_DEINT(n) ((n) << 12)
|
||||
#define CHNL_IMG_CTRL_DEINT_MASK GENMASK(14, 12)
|
||||
#define CHNL_IMG_CTRL_DEINT_WEAVE_ODD_EVEN 2
|
||||
#define CHNL_IMG_CTRL_DEINT_WEAVE_EVEN_ODD 3
|
||||
#define CHNL_IMG_CTRL_DEINT_BLEND_ODD_EVEN 4
|
||||
#define CHNL_IMG_CTRL_DEINT_BLEND_EVEN_ODD 5
|
||||
#define CHNL_IMG_CTRL_DEINT_LDOUBLE_ODD_EVEN 6
|
||||
#define CHNL_IMG_CTRL_DEINT_LDOUBLE_EVEN_ODD 7
|
||||
#define CHNL_IMG_CTRL_DEC_X(n) ((n) << 10)
|
||||
#define CHNL_IMG_CTRL_DEC_X_MASK GENMASK(11, 10)
|
||||
#define CHNL_IMG_CTRL_DEC_Y(n) ((n) << 8)
|
||||
#define CHNL_IMG_CTRL_DEC_Y_MASK GENMASK(9, 8)
|
||||
#define CHNL_IMG_CTRL_CROP_EN BIT(7)
|
||||
#define CHNL_IMG_CTRL_VFLIP_EN BIT(6)
|
||||
#define CHNL_IMG_CTRL_HFLIP_EN BIT(5)
|
||||
#define CHNL_IMG_CTRL_YCBCR_MODE BIT(3)
|
||||
#define CHNL_IMG_CTRL_CSC_MODE(n) ((n) << 1)
|
||||
#define CHNL_IMG_CTRL_CSC_MODE_MASK GENMASK(2, 1)
|
||||
#define CHNL_IMG_CTRL_CSC_MODE_YUV2RGB 0
|
||||
#define CHNL_IMG_CTRL_CSC_MODE_YCBCR2RGB 1
|
||||
#define CHNL_IMG_CTRL_CSC_MODE_RGB2YUV 2
|
||||
#define CHNL_IMG_CTRL_CSC_MODE_RGB2YCBCR 3
|
||||
#define CHNL_IMG_CTRL_CSC_BYPASS BIT(0)
|
||||
|
||||
/* Channel Output Buffer Control Register */
|
||||
#define CHNL_OUT_BUF_CTRL 0x0008
|
||||
#define CHNL_OUT_BUF_CTRL_LOAD_BUF2_ADDR BIT(15)
|
||||
#define CHNL_OUT_BUF_CTRL_LOAD_BUF1_ADDR BIT(14)
|
||||
#define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_V(n) ((n) << 6)
|
||||
#define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_V_MASK GENMASK(7, 6)
|
||||
#define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_V_NO_PANIC 0
|
||||
#define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_V_PANIC_25 1
|
||||
#define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_V_PANIC_50 2
|
||||
#define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_V_PANIC_75 3
|
||||
#define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_U(n) ((n) << 3)
|
||||
#define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_U_MASK GENMASK(4, 3)
|
||||
#define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_U_NO_PANIC 0
|
||||
#define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_U_PANIC_25 1
|
||||
#define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_U_PANIC_50 2
|
||||
#define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_U_PANIC_75 3
|
||||
#define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_Y(n) ((n) << 0)
|
||||
#define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_Y_MASK GENMASK(1, 0)
|
||||
#define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_Y_NO_PANIC 0
|
||||
#define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_Y_PANIC_25 1
|
||||
#define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_Y_PANIC_50 2
|
||||
#define CHNL_OUT_BUF_CTRL_OFLW_PANIC_SET_THD_Y_PANIC_75 3
|
||||
|
||||
/* Channel Image Configuration */
|
||||
#define CHNL_IMG_CFG 0x000c
|
||||
#define CHNL_IMG_CFG_HEIGHT(n) ((n) << 16)
|
||||
#define CHNL_IMG_CFG_HEIGHT_MASK GENMASK(28, 16)
|
||||
#define CHNL_IMG_CFG_WIDTH(n) ((n) << 0)
|
||||
#define CHNL_IMG_CFG_WIDTH_MASK GENMASK(12, 0)
|
||||
|
||||
/* Channel Interrupt Enable Register */
|
||||
#define CHNL_IER 0x0010
|
||||
#define CHNL_IER_MEM_RD_DONE_EN BIT(31)
|
||||
#define CHNL_IER_LINE_RCVD_EN BIT(30)
|
||||
#define CHNL_IER_FRM_RCVD_EN BIT(29)
|
||||
#define CHNL_IER_AXI_WR_ERR_V_EN BIT(28)
|
||||
#define CHNL_IER_AXI_WR_ERR_U_EN BIT(27)
|
||||
#define CHNL_IER_AXI_WR_ERR_Y_EN BIT(26)
|
||||
#define CHNL_IER_AXI_RD_ERR_EN BIT(25)
|
||||
|
||||
/* Channel Status Register */
|
||||
#define CHNL_STS 0x0014
|
||||
#define CHNL_STS_MEM_RD_DONE BIT(31)
|
||||
#define CHNL_STS_LINE_STRD BIT(30)
|
||||
#define CHNL_STS_FRM_STRD BIT(29)
|
||||
#define CHNL_STS_AXI_WR_ERR_V BIT(28)
|
||||
#define CHNL_STS_AXI_WR_ERR_U BIT(27)
|
||||
#define CHNL_STS_AXI_WR_ERR_Y BIT(26)
|
||||
#define CHNL_STS_AXI_RD_ERR BIT(25)
|
||||
#define CHNL_STS_OFLW_PANIC_V_BUF BIT(24)
|
||||
#define CHNL_STS_EXCS_OFLW_V_BUF BIT(23)
|
||||
#define CHNL_STS_OFLW_V_BUF BIT(22)
|
||||
#define CHNL_STS_OFLW_PANIC_U_BUF BIT(21)
|
||||
#define CHNL_STS_EXCS_OFLW_U_BUF BIT(20)
|
||||
#define CHNL_STS_OFLW_U_BUF BIT(19)
|
||||
#define CHNL_STS_OFLW_PANIC_Y_BUF BIT(18)
|
||||
#define CHNL_STS_EXCS_OFLW_Y_BUF BIT(17)
|
||||
#define CHNL_STS_OFLW_Y_BUF BIT(16)
|
||||
#define CHNL_STS_EARLY_VSYNC_ERR BIT(15)
|
||||
#define CHNL_STS_LATE_VSYNC_ERR BIT(14)
|
||||
#define CHNL_STS_MEM_RD_OFLOW BIT(10)
|
||||
#define CHNL_STS_BUF2_ACTIVE BIT(9)
|
||||
#define CHNL_STS_BUF1_ACTIVE BIT(8)
|
||||
#define CHNL_STS_OFLW_BYTES(n) ((n) << 0)
|
||||
#define CHNL_STS_OFLW_BYTES_MASK GENMASK(7, 0)
|
||||
|
||||
/* Channel Scale Factor Register */
|
||||
#define CHNL_SCALE_FACTOR 0x0018
|
||||
#define CHNL_SCALE_FACTOR_Y_SCALE(n) ((n) << 16)
|
||||
#define CHNL_SCALE_FACTOR_Y_SCALE_MASK GENMASK(29, 16)
|
||||
#define CHNL_SCALE_FACTOR_X_SCALE(n) ((n) << 0)
|
||||
#define CHNL_SCALE_FACTOR_X_SCALE_MASK GENMASK(13, 0)
|
||||
|
||||
/* Channel Scale Offset Register */
|
||||
#define CHNL_SCALE_OFFSET 0x001c
|
||||
#define CHNL_SCALE_OFFSET_Y_SCALE(n) ((n) << 16)
|
||||
#define CHNL_SCALE_OFFSET_Y_SCALE_MASK GENMASK(27, 16)
|
||||
#define CHNL_SCALE_OFFSET_X_SCALE(n) ((n) << 0)
|
||||
#define CHNL_SCALE_OFFSET_X_SCALE_MASK GENMASK(11, 0)
|
||||
|
||||
/* Channel Crop Upper Left Corner Coordinate Register */
|
||||
#define CHNL_CROP_ULC 0x0020
|
||||
#define CHNL_CROP_ULC_X(n) ((n) << 16)
|
||||
#define CHNL_CROP_ULC_X_MASK GENMASK(27, 16)
|
||||
#define CHNL_CROP_ULC_Y(n) ((n) << 0)
|
||||
#define CHNL_CROP_ULC_Y_MASK GENMASK(11, 0)
|
||||
|
||||
/* Channel Crop Lower Right Corner Coordinate Register */
|
||||
#define CHNL_CROP_LRC 0x0024
|
||||
#define CHNL_CROP_LRC_X(n) ((n) << 16)
|
||||
#define CHNL_CROP_LRC_X_MASK GENMASK(27, 16)
|
||||
#define CHNL_CROP_LRC_Y(n) ((n) << 0)
|
||||
#define CHNL_CROP_LRC_Y_MASK GENMASK(11, 0)
|
||||
|
||||
/* Channel Color Space Conversion Coefficient Register 0 */
|
||||
#define CHNL_CSC_COEFF0 0x0028
|
||||
#define CHNL_CSC_COEFF0_A2(n) ((n) << 16)
|
||||
#define CHNL_CSC_COEFF0_A2_MASK GENMASK(26, 16)
|
||||
#define CHNL_CSC_COEFF0_A1(n) ((n) << 0)
|
||||
#define CHNL_CSC_COEFF0_A1_MASK GENMASK(10, 0)
|
||||
|
||||
/* Channel Color Space Conversion Coefficient Register 1 */
|
||||
#define CHNL_CSC_COEFF1 0x002c
|
||||
#define CHNL_CSC_COEFF1_B1(n) ((n) << 16)
|
||||
#define CHNL_CSC_COEFF1_B1_MASK GENMASK(26, 16)
|
||||
#define CHNL_CSC_COEFF1_A3(n) ((n) << 0)
|
||||
#define CHNL_CSC_COEFF1_A3_MASK GENMASK(10, 0)
|
||||
|
||||
/* Channel Color Space Conversion Coefficient Register 2 */
|
||||
#define CHNL_CSC_COEFF2 0x0030
|
||||
#define CHNL_CSC_COEFF2_B3(n) ((n) << 16)
|
||||
#define CHNL_CSC_COEFF2_B3_MASK GENMASK(26, 16)
|
||||
#define CHNL_CSC_COEFF2_B2(n) ((n) << 0)
|
||||
#define CHNL_CSC_COEFF2_B2_MASK GENMASK(10, 0)
|
||||
|
||||
/* Channel Color Space Conversion Coefficient Register 3 */
|
||||
#define CHNL_CSC_COEFF3 0x0034
|
||||
#define CHNL_CSC_COEFF3_C2(n) ((n) << 16)
|
||||
#define CHNL_CSC_COEFF3_C2_MASK GENMASK(26, 16)
|
||||
#define CHNL_CSC_COEFF3_C1(n) ((n) << 0)
|
||||
#define CHNL_CSC_COEFF3_C1_MASK GENMASK(10, 0)
|
||||
|
||||
/* Channel Color Space Conversion Coefficient Register 4 */
|
||||
#define CHNL_CSC_COEFF4 0x0038
|
||||
#define CHNL_CSC_COEFF4_D1(n) ((n) << 16)
|
||||
#define CHNL_CSC_COEFF4_D1_MASK GENMASK(24, 16)
|
||||
#define CHNL_CSC_COEFF4_C3(n) ((n) << 0)
|
||||
#define CHNL_CSC_COEFF4_C3_MASK GENMASK(10, 0)
|
||||
|
||||
/* Channel Color Space Conversion Coefficient Register 5 */
|
||||
#define CHNL_CSC_COEFF5 0x003c
|
||||
#define CHNL_CSC_COEFF5_D3(n) ((n) << 16)
|
||||
#define CHNL_CSC_COEFF5_D3_MASK GENMASK(24, 16)
|
||||
#define CHNL_CSC_COEFF5_D2(n) ((n) << 0)
|
||||
#define CHNL_CSC_COEFF5_D2_MASK GENMASK(8, 0)
|
||||
|
||||
/* Channel Alpha Value Register for ROI 0 */
|
||||
#define CHNL_ROI_0_ALPHA 0x0040
|
||||
#define CHNL_ROI_0_ALPHA_VAL(n) ((n) << 24)
|
||||
#define CHNL_ROI_0_ALPHA_MASK GENMASK(31, 24)
|
||||
#define CHNL_ROI_0_ALPHA_EN BIT(16)
|
||||
|
||||
/* Channel Upper Left Coordinate Register for ROI 0 */
|
||||
#define CHNL_ROI_0_ULC 0x0044
|
||||
#define CHNL_ROI_0_ULC_X(n) ((n) << 16)
|
||||
#define CHNL_ROI_0_ULC_X_MASK GENMASK(27, 16)
|
||||
#define CHNL_ROI_0_ULC_Y(n) ((n) << 0)
|
||||
#define CHNL_ROI_0_ULC_Y_MASK GENMASK(11, 0)
|
||||
|
||||
/* Channel Lower Right Coordinate Register for ROI 0 */
|
||||
#define CHNL_ROI_0_LRC 0x0048
|
||||
#define CHNL_ROI_0_LRC_X(n) ((n) << 16)
|
||||
#define CHNL_ROI_0_LRC_X_MASK GENMASK(27, 16)
|
||||
#define CHNL_ROI_0_LRC_Y(n) ((n) << 0)
|
||||
#define CHNL_ROI_0_LRC_Y_MASK GENMASK(11, 0)
|
||||
|
||||
/* Channel Alpha Value Register for ROI 1 */
|
||||
#define CHNL_ROI_1_ALPHA 0x004c
|
||||
#define CHNL_ROI_1_ALPHA_VAL(n) ((n) << 24)
|
||||
#define CHNL_ROI_1_ALPHA_MASK GENMASK(31, 24)
|
||||
#define CHNL_ROI_1_ALPHA_EN BIT(16)
|
||||
|
||||
/* Channel Upper Left Coordinate Register for ROI 1 */
|
||||
#define CHNL_ROI_1_ULC 0x0050
|
||||
#define CHNL_ROI_1_ULC_X(n) ((n) << 16)
|
||||
#define CHNL_ROI_1_ULC_X_MASK GENMASK(27, 16)
|
||||
#define CHNL_ROI_1_ULC_Y(n) ((n) << 0)
|
||||
#define CHNL_ROI_1_ULC_Y_MASK GENMASK(11, 0)
|
||||
|
||||
/* Channel Lower Right Coordinate Register for ROI 1 */
|
||||
#define CHNL_ROI_1_LRC 0x0054
|
||||
#define CHNL_ROI_1_LRC_X(n) ((n) << 16)
|
||||
#define CHNL_ROI_1_LRC_X_MASK GENMASK(27, 16)
|
||||
#define CHNL_ROI_1_LRC_Y(n) ((n) << 0)
|
||||
#define CHNL_ROI_1_LRC_Y_MASK GENMASK(11, 0)
|
||||
|
||||
/* Channel Alpha Value Register for ROI 2 */
|
||||
#define CHNL_ROI_2_ALPHA 0x0058
|
||||
#define CHNL_ROI_2_ALPHA_VAL(n) ((n) << 24)
|
||||
#define CHNL_ROI_2_ALPHA_MASK GENMASK(31, 24)
|
||||
#define CHNL_ROI_2_ALPHA_EN BIT(16)
|
||||
|
||||
/* Channel Upper Left Coordinate Register for ROI 2 */
|
||||
#define CHNL_ROI_2_ULC 0x005c
|
||||
#define CHNL_ROI_2_ULC_X(n) ((n) << 16)
|
||||
#define CHNL_ROI_2_ULC_X_MASK GENMASK(27, 16)
|
||||
#define CHNL_ROI_2_ULC_Y(n) ((n) << 0)
|
||||
#define CHNL_ROI_2_ULC_Y_MASK GENMASK(11, 0)
|
||||
|
||||
/* Channel Lower Right Coordinate Register for ROI 2 */
|
||||
#define CHNL_ROI_2_LRC 0x0060
|
||||
#define CHNL_ROI_2_LRC_X(n) ((n) << 16)
|
||||
#define CHNL_ROI_2_LRC_X_MASK GENMASK(27, 16)
|
||||
#define CHNL_ROI_2_LRC_Y(n) ((n) << 0)
|
||||
#define CHNL_ROI_2_LRC_Y_MASK GENMASK(11, 0)
|
||||
|
||||
/* Channel Alpha Value Register for ROI 3 */
|
||||
#define CHNL_ROI_3_ALPHA 0x0064
|
||||
#define CHNL_ROI_3_ALPHA_VAL(n) ((n) << 24)
|
||||
#define CHNL_ROI_3_ALPHA_MASK GENMASK(31, 24)
|
||||
#define CHNL_ROI_3_ALPHA_EN BIT(16)
|
||||
|
||||
/* Channel Upper Left Coordinate Register for ROI 3 */
|
||||
#define CHNL_ROI_3_ULC 0x0068
|
||||
#define CHNL_ROI_3_ULC_X(n) ((n) << 16)
|
||||
#define CHNL_ROI_3_ULC_X_MASK GENMASK(27, 16)
|
||||
#define CHNL_ROI_3_ULC_Y(n) ((n) << 0)
|
||||
#define CHNL_ROI_3_ULC_Y_MASK GENMASK(11, 0)
|
||||
|
||||
/* Channel Lower Right Coordinate Register for ROI 3 */
|
||||
#define CHNL_ROI_3_LRC 0x006c
|
||||
#define CHNL_ROI_3_LRC_X(n) ((n) << 16)
|
||||
#define CHNL_ROI_3_LRC_X_MASK GENMASK(27, 16)
|
||||
#define CHNL_ROI_3_LRC_Y(n) ((n) << 0)
|
||||
#define CHNL_ROI_3_LRC_Y_MASK GENMASK(11, 0)
|
||||
/* Channel RGB or Luma (Y) Output Buffer 1 Address */
|
||||
#define CHNL_OUT_BUF1_ADDR_Y 0x0070
|
||||
|
||||
/* Channel Chroma (U/Cb/UV/CbCr) Output Buffer 1 Address */
|
||||
#define CHNL_OUT_BUF1_ADDR_U 0x0074
|
||||
|
||||
/* Channel Chroma (V/Cr) Output Buffer 1 Address */
|
||||
#define CHNL_OUT_BUF1_ADDR_V 0x0078
|
||||
|
||||
/* Channel Output Buffer Pitch */
|
||||
#define CHNL_OUT_BUF_PITCH 0x007c
|
||||
#define CHNL_OUT_BUF_PITCH_LINE_PITCH(n) ((n) << 0)
|
||||
#define CHNL_OUT_BUF_PITCH_LINE_PITCH_MASK GENMASK(15, 0)
|
||||
|
||||
/* Channel Input Buffer Address */
|
||||
#define CHNL_IN_BUF_ADDR 0x0080
|
||||
|
||||
/* Channel Input Buffer Pitch */
|
||||
#define CHNL_IN_BUF_PITCH 0x0084
|
||||
#define CHNL_IN_BUF_PITCH_FRM_PITCH(n) ((n) << 16)
|
||||
#define CHNL_IN_BUF_PITCH_FRM_PITCH_MASK GENMASK(31, 16)
|
||||
#define CHNL_IN_BUF_PITCH_LINE_PITCH(n) ((n) << 0)
|
||||
#define CHNL_IN_BUF_PITCH_LINE_PITCH_MASK GENMASK(15, 0)
|
||||
|
||||
/* Channel Memory Read Control */
|
||||
#define CHNL_MEM_RD_CTRL 0x0088
|
||||
#define CHNL_MEM_RD_CTRL_IMG_TYPE(n) ((n) << 28)
|
||||
#define CHNL_MEM_RD_CTRL_IMG_TYPE_MASK GENMASK(31, 28)
|
||||
#define CHNL_MEM_RD_CTRL_IMG_TYPE_BGR8P 0x00
|
||||
#define CHNL_MEM_RD_CTRL_IMG_TYPE_RGB8P 0x01
|
||||
#define CHNL_MEM_RD_CTRL_IMG_TYPE_XRGB8 0x02
|
||||
#define CHNL_MEM_RD_CTRL_IMG_TYPE_RGBX8 0x03
|
||||
#define CHNL_MEM_RD_CTRL_IMG_TYPE_XBGR8 0x04
|
||||
#define CHNL_MEM_RD_CTRL_IMG_TYPE_RGB565 0x05
|
||||
#define CHNL_MEM_RD_CTRL_IMG_TYPE_A2BGR10 0x06
|
||||
#define CHNL_MEM_RD_CTRL_IMG_TYPE_A2RGB10 0x07
|
||||
#define CHNL_MEM_RD_CTRL_IMG_TYPE_YUV444_1P8P 0x08
|
||||
#define CHNL_MEM_RD_CTRL_IMG_TYPE_YUV444_1P10 0x09
|
||||
#define CHNL_MEM_RD_CTRL_IMG_TYPE_YUV444_1P10P 0x0a
|
||||
#define CHNL_MEM_RD_CTRL_IMG_TYPE_YUV444_1P12 0x0b
|
||||
#define CHNL_MEM_RD_CTRL_IMG_TYPE_YUV444_1P8 0x0c
|
||||
#define CHNL_MEM_RD_CTRL_IMG_TYPE_YUV422_1P8P 0x0d
|
||||
#define CHNL_MEM_RD_CTRL_IMG_TYPE_YUV422_1P10 0x0e
|
||||
#define CHNL_MEM_RD_CTRL_IMG_TYPE_YUV422_1P12 0x0f
|
||||
#define CHNL_MEM_RD_CTRL_READ_MEM BIT(0)
|
||||
|
||||
/* Channel RGB or Luma (Y) Output Buffer 2 Address */
|
||||
#define CHNL_OUT_BUF2_ADDR_Y 0x008c
|
||||
|
||||
/* Channel Chroma (U/Cb/UV/CbCr) Output Buffer 2 Address */
|
||||
#define CHNL_OUT_BUF2_ADDR_U 0x0090
|
||||
|
||||
/* Channel Chroma (V/Cr) Output Buffer 2 Address */
|
||||
#define CHNL_OUT_BUF2_ADDR_V 0x0094
|
||||
|
||||
/* Channel scale image config */
|
||||
#define CHNL_SCL_IMG_CFG 0x0098
|
||||
#define CHNL_SCL_IMG_CFG_HEIGHT(n) ((n) << 16)
|
||||
#define CHNL_SCL_IMG_CFG_HEIGHT_MASK GENMASK(28, 16)
|
||||
#define CHNL_SCL_IMG_CFG_WIDTH(n) ((n) << 0)
|
||||
#define CHNL_SCL_IMG_CFG_WIDTH_MASK GENMASK(12, 0)
|
||||
|
||||
/* Channel Flow Control Register */
|
||||
#define CHNL_FLOW_CTRL 0x009c
|
||||
#define CHNL_FLOW_CTRL_FC_DENOM_MASK GENMASK(7, 0)
|
||||
#define CHNL_FLOW_CTRL_FC_DENOM(n) ((n) << 0)
|
||||
#define CHNL_FLOW_CTRL_FC_NUMER_MASK GENMASK(23, 16)
|
||||
#define CHNL_FLOW_CTRL_FC_NUMER(n) ((n) << 0)
|
||||
|
||||
/* Channel Output Y-Buffer 1 Extended Address Bits */
|
||||
#define CHNL_Y_BUF1_XTND_ADDR 0x00a0
|
||||
|
||||
/* Channel Output U-Buffer 1 Extended Address Bits */
|
||||
#define CHNL_U_BUF1_XTND_ADDR 0x00a4
|
||||
|
||||
/* Channel Output V-Buffer 1 Extended Address Bits */
|
||||
#define CHNL_V_BUF1_XTND_ADDR 0x00a8
|
||||
|
||||
/* Channel Output Y-Buffer 2 Extended Address Bits */
|
||||
#define CHNL_Y_BUF2_XTND_ADDR 0x00ac
|
||||
|
||||
/* Channel Output U-Buffer 2 Extended Address Bits */
|
||||
#define CHNL_U_BUF2_XTND_ADDR 0x00b0
|
||||
|
||||
/* Channel Output V-Buffer 2 Extended Address Bits */
|
||||
#define CHNL_V_BUF2_XTND_ADDR 0x00b4
|
||||
|
||||
/* Channel Input Buffer Extended Address Bits */
|
||||
#define CHNL_IN_BUF_XTND_ADDR 0x00b8
|
||||
|
||||
#endif /* __IMX8_ISI_REGS_H__ */
|
||||
File diff suppressed because it is too large.
Load diff
Reference in new issue
Block a user