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drm/amd/ras: Add umc common ras functions
Add umc common ras functions. Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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YiPeng Chai
committed by
Alex Deucher
Alex Deucher
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commit
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/* SPDX-License-Identifier: MIT */
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/*
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* Copyright 2025 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __RAS_UMC_H__
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#define __RAS_UMC_H__
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#include "ras.h"
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#include "ras_eeprom.h"
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#include "ras_cmd.h"
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#define UMC_VRAM_TYPE_UNKNOWN 0
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#define UMC_VRAM_TYPE_GDDR1 1
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#define UMC_VRAM_TYPE_DDR2 2
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#define UMC_VRAM_TYPE_GDDR3 3
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#define UMC_VRAM_TYPE_GDDR4 4
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#define UMC_VRAM_TYPE_GDDR5 5
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#define UMC_VRAM_TYPE_HBM 6
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#define UMC_VRAM_TYPE_DDR3 7
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#define UMC_VRAM_TYPE_DDR4 8
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#define UMC_VRAM_TYPE_GDDR6 9
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#define UMC_VRAM_TYPE_DDR5 10
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#define UMC_VRAM_TYPE_LPDDR4 11
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#define UMC_VRAM_TYPE_LPDDR5 12
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#define UMC_VRAM_TYPE_HBM3E 13
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#define UMC_ECC_NEW_DETECTED_TAG 0x1
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#define UMC_INV_MEM_PFN (0xFFFFFFFFFFFFFFFF)
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/* three column bits and one row bit in MCA address flip
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* in bad page retirement
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*/
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#define UMC_PA_FLIP_BITS_NUM 4
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enum umc_memory_partition_mode {
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UMC_MEMORY_PARTITION_MODE_NONE = 0,
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UMC_MEMORY_PARTITION_MODE_NPS1 = 1,
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UMC_MEMORY_PARTITION_MODE_NPS2 = 2,
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UMC_MEMORY_PARTITION_MODE_NPS3 = 3,
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UMC_MEMORY_PARTITION_MODE_NPS4 = 4,
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UMC_MEMORY_PARTITION_MODE_NPS6 = 6,
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UMC_MEMORY_PARTITION_MODE_NPS8 = 8,
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UMC_MEMORY_PARTITION_MODE_UNKNOWN
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};
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struct ras_core_context;
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struct ras_bank_ecc;
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struct umc_flip_bits {
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uint32_t flip_bits_in_pa[UMC_PA_FLIP_BITS_NUM];
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uint32_t flip_row_bit;
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uint32_t r13_in_pa;
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uint32_t bit_num;
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};
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struct umc_mca_addr {
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uint64_t err_addr;
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uint32_t ch_inst;
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uint32_t umc_inst;
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uint32_t node_inst;
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uint32_t socket_id;
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};
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struct umc_phy_addr {
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uint64_t pa;
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uint32_t bank;
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uint32_t channel_idx;
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};
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struct umc_bank_addr {
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uint32_t stack_id; /* SID */
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uint32_t bank_group;
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uint32_t bank;
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uint32_t row;
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uint32_t column;
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uint32_t channel;
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uint32_t subchannel; /* Also called Pseudochannel (PC) */
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};
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struct ras_umc_ip_func {
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int (*bank_to_eeprom_record)(struct ras_core_context *ras_core,
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struct ras_bank_ecc *bank, struct eeprom_umc_record *record);
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int (*eeprom_record_to_nps_record)(struct ras_core_context *ras_core,
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struct eeprom_umc_record *record, uint32_t nps);
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int (*eeprom_record_to_nps_pages)(struct ras_core_context *ras_core,
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struct eeprom_umc_record *record, uint32_t nps,
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uint64_t *pfns, uint32_t num);
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int (*bank_to_soc_pa)(struct ras_core_context *ras_core,
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struct umc_bank_addr bank_addr, uint64_t *soc_pa);
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int (*soc_pa_to_bank)(struct ras_core_context *ras_core,
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uint64_t soc_pa, struct umc_bank_addr *bank_addr);
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};
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struct eeprom_store_record {
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/* point to data records array */
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struct eeprom_umc_record *bps;
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/* the count of entries */
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int count;
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/* the space can place new entries */
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int space_left;
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};
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struct ras_umc_err_data {
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struct eeprom_store_record rom_data;
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struct eeprom_store_record ram_data;
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enum umc_memory_partition_mode umc_nps_mode;
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uint64_t last_retired_pfn;
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};
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struct ras_umc {
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u32 umc_ip_version;
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u32 umc_vram_type;
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const struct ras_umc_ip_func *ip_func;
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struct radix_tree_root root;
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struct mutex tree_lock;
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struct mutex umc_lock;
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struct mutex bank_log_lock;
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struct mutex pending_ecc_lock;
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struct ras_umc_err_data umc_err_data;
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struct list_head pending_ecc_list;
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};
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int ras_umc_sw_init(struct ras_core_context *ras);
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int ras_umc_sw_fini(struct ras_core_context *ras);
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int ras_umc_hw_init(struct ras_core_context *ras);
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int ras_umc_hw_fini(struct ras_core_context *ras);
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int ras_umc_psp_convert_ma_to_pa(struct ras_core_context *ras_core,
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struct umc_mca_addr *in, struct umc_phy_addr *out,
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uint32_t nps);
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int ras_umc_handle_bad_pages(struct ras_core_context *ras_core, void *data);
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int ras_umc_log_bad_bank(struct ras_core_context *ras, struct ras_bank_ecc *bank);
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int ras_umc_log_bad_bank_pending(struct ras_core_context *ras_core, struct ras_bank_ecc *bank);
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int ras_umc_log_pending_bad_bank(struct ras_core_context *ras_core);
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int ras_umc_clear_logged_ecc(struct ras_core_context *ras_core);
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int ras_umc_load_bad_pages(struct ras_core_context *ras_core);
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int ras_umc_get_saved_eeprom_count(struct ras_core_context *ras_core);
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int ras_umc_clean_badpage_data(struct ras_core_context *ras_core);
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int ras_umc_fill_eeprom_record(struct ras_core_context *ras_core,
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uint64_t err_addr, uint32_t umc_inst, struct umc_phy_addr *cur_nps_addr,
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enum umc_memory_partition_mode cur_nps, struct eeprom_umc_record *record);
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int ras_umc_get_badpage_count(struct ras_core_context *ras_core);
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int ras_umc_get_badpage_record(struct ras_core_context *ras_core, uint32_t index, void *record);
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bool ras_umc_check_retired_addr(struct ras_core_context *ras_core, uint64_t addr);
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int ras_umc_translate_soc_pa_and_bank(struct ras_core_context *ras_core,
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uint64_t *soc_pa, struct umc_bank_addr *bank_addr, bool bank_to_pa);
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#endif
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