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MIPS: Alchemy: Extended DB1200 board support.
Create own directory for DB1200 code and update it with new features. - SPI support: - tmp121 temperature sensor - SPI flash on DB1200 - I2C support - NE1619 sensor - AT24 eeprom - I2C/SPI can be selected at boot time via switch S6.8 - Carddetect IRQs for SD cards. - gen_nand based NAND support. - hexleds count sleep/wake transitions. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Cc: Linux-MIPS <linux-mips@linux-mips.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Manuel Lauss
committed by
Ralf Baechle
Ralf Baechle
parent
206aa6cdad
commit
63323ec54a
@@ -164,9 +164,6 @@ void au1000_halt(void)
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#ifdef CONFIG_MIPS_MIRAGE
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gpio_direction_output(210, 1);
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#endif
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#ifdef CONFIG_MIPS_DB1200
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au_writew(au_readw(0xB980001C) | (1 << 14), 0xB980001C);
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#endif
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#ifdef CONFIG_PM
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au_sleep();
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@@ -11,7 +11,7 @@ obj-$(CONFIG_MIPS_PB1500) += pb1500/
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obj-$(CONFIG_MIPS_PB1550) += pb1550/
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obj-$(CONFIG_MIPS_DB1000) += db1x00/
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obj-$(CONFIG_MIPS_DB1100) += db1x00/
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obj-$(CONFIG_MIPS_DB1200) += pb1200/
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obj-$(CONFIG_MIPS_DB1200) += db1200/
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obj-$(CONFIG_MIPS_DB1500) += db1x00/
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obj-$(CONFIG_MIPS_DB1550) += db1x00/
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obj-$(CONFIG_MIPS_BOSPORUS) += db1x00/
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@@ -0,0 +1 @@
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obj-y += setup.o platform.o
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,137 @@
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/*
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* Alchemy/AMD/RMI DB1200 board setup.
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*
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* Licensed under the terms outlined in the file COPYING in the root of
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* this source archive.
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/pm.h>
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#include <asm/mach-au1x00/au1000.h>
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#include <asm/mach-db1x00/bcsr.h>
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#include <asm/mach-db1x00/db1200.h>
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#include <asm/processor.h>
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#include <asm/reboot.h>
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const char *get_system_type(void)
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{
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return "Alchemy Db1200";
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}
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static void board_power_off(void)
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{
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bcsr_write(BCSR_RESETS, 0);
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bcsr_write(BCSR_SYSTEM, BCSR_SYSTEM_PWROFF | BCSR_SYSTEM_RESET);
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}
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void board_reset(void)
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{
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bcsr_write(BCSR_RESETS, 0);
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bcsr_write(BCSR_SYSTEM, 0);
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}
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void __init board_setup(void)
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{
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unsigned long freq0, clksrc, div, pfc;
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unsigned short whoami;
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bcsr_init(DB1200_BCSR_PHYS_ADDR,
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DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS);
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whoami = bcsr_read(BCSR_WHOAMI);
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printk(KERN_INFO "Alchemy/AMD/RMI DB1200 Board, CPLD Rev %d"
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" Board-ID %d Daughtercard ID %d\n",
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(whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf);
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/* SMBus/SPI on PSC0, Audio on PSC1 */
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pfc = __raw_readl((void __iomem *)SYS_PINFUNC);
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pfc &= ~(SYS_PINFUNC_P0A | SYS_PINFUNC_P0B);
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pfc &= ~(SYS_PINFUNC_P1A | SYS_PINFUNC_P1B | SYS_PINFUNC_FS3);
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pfc |= SYS_PINFUNC_P1C; /* SPI is configured later */
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__raw_writel(pfc, (void __iomem *)SYS_PINFUNC);
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wmb();
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/* Clock configurations: PSC0: ~50MHz via Clkgen0, derived from
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* CPU clock; all other clock generators off/unused.
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*/
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div = (get_au1x00_speed() + 25000000) / 50000000;
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if (div & 1)
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div++;
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div = ((div >> 1) - 1) & 0xff;
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freq0 = div << SYS_FC_FRDIV0_BIT;
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__raw_writel(freq0, (void __iomem *)SYS_FREQCTRL0);
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wmb();
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freq0 |= SYS_FC_FE0; /* enable F0 */
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__raw_writel(freq0, (void __iomem *)SYS_FREQCTRL0);
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wmb();
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/* psc0_intclk comes 1:1 from F0 */
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clksrc = SYS_CS_MUX_FQ0 << SYS_CS_ME0_BIT;
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__raw_writel(clksrc, (void __iomem *)SYS_CLKSRC);
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wmb();
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pm_power_off = board_power_off;
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_machine_halt = board_power_off;
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_machine_restart = (void(*)(char *))board_reset;
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}
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/* use the hexleds to count the number of times the cpu has entered
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* wait, the dots to indicate whether the CPU is currently idle or
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* active (dots off = sleeping, dots on = working) for cases where
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* the number doesn't change for a long(er) period of time.
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*/
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static void db1200_wait(void)
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{
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__asm__(" .set push \n"
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" .set mips3 \n"
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" .set noreorder \n"
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" cache 0x14, 0(%0) \n"
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" cache 0x14, 32(%0) \n"
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" cache 0x14, 64(%0) \n"
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/* dots off: we're about to call wait */
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" lui $26, 0xb980 \n"
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" ori $27, $0, 3 \n"
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" sb $27, 0x18($26) \n"
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" sync \n"
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" nop \n"
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" wait \n"
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" nop \n"
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" nop \n"
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" nop \n"
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" nop \n"
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" nop \n"
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/* dots on: there's work to do, increment cntr */
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" lui $26, 0xb980 \n"
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" sb $0, 0x18($26) \n"
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" lui $26, 0xb9c0 \n"
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" lb $27, 0($26) \n"
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" addiu $27, $27, 1 \n"
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" sb $27, 0($26) \n"
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" sync \n"
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" .set pop \n"
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: : "r" (db1200_wait));
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}
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static int __init db1200_arch_init(void)
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{
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/* GPIO7 is low-level triggered CPLD cascade */
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set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW);
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bcsr_init_irq(DB1200_INT_BEGIN, DB1200_INT_END, AU1200_GPIO7_INT);
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/* do not autoenable these: CPLD has broken edge int handling,
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* and the CD handler setup requires manual enabling to work
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* around that.
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*/
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irq_to_desc(DB1200_SD0_INSERT_INT)->status |= IRQ_NOAUTOEN;
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irq_to_desc(DB1200_SD0_EJECT_INT)->status |= IRQ_NOAUTOEN;
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if (cpu_wait)
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cpu_wait = db1200_wait;
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return 0;
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}
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arch_initcall(db1200_arch_init);
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@@ -58,16 +58,9 @@ void __init board_setup(void)
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{
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char *argptr;
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#ifdef CONFIG_MIPS_PB1200
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printk(KERN_INFO "AMD Alchemy Pb1200 Board\n");
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bcsr_init(PB1200_BCSR_PHYS_ADDR,
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PB1200_BCSR_PHYS_ADDR + PB1200_BCSR_HEXLED_OFS);
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#endif
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#ifdef CONFIG_MIPS_DB1200
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printk(KERN_INFO "AMD Alchemy Db1200 Board\n");
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bcsr_init(DB1200_BCSR_PHYS_ADDR,
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DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS);
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#endif
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argptr = prom_getcmdline();
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#ifdef CONFIG_SERIAL_8250_CONSOLE
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@@ -149,7 +142,6 @@ void __init board_setup(void)
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static int __init pb1200_init_irq(void)
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{
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#ifdef CONFIG_MIPS_PB1200
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/* We have a problem with CPLD rev 3. */
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if (BCSR_WHOAMI_CPLD(bcsr_read(BCSR_WHOAMI)) <= 3) {
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printk(KERN_ERR "WARNING!!!\n");
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@@ -169,7 +161,6 @@ static int __init pb1200_init_irq(void)
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printk(KERN_ERR "WARNING!!!\n");
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panic("Game over. Your score is 0.");
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}
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#endif
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set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW);
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bcsr_init_irq(PB1200_INT_BEGIN, PB1200_INT_END, AU1200_GPIO7_INT);
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@@ -68,7 +68,6 @@ static struct led_classdev pb1200mmc_led = {
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.brightness_set = pb1200_mmcled_set,
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};
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#ifndef CONFIG_MIPS_DB1200
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static void pb1200mmc1_set_power(void *mmc_host, int state)
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{
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if (state)
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@@ -88,7 +87,6 @@ static int pb1200mmc1_card_inserted(void *mmc_host)
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{
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return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT) ? 1 : 0;
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}
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#endif
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const struct au1xmmc_platform_data au1xmmc_platdata[2] = {
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[0] = {
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@@ -98,7 +96,6 @@ const struct au1xmmc_platform_data au1xmmc_platdata[2] = {
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.cd_setup = NULL, /* use poll-timer in driver */
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.led = &pb1200mmc_led,
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},
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#ifndef CONFIG_MIPS_DB1200
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[1] = {
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.set_power = pb1200mmc1_set_power,
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.card_inserted = pb1200mmc1_card_inserted,
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@@ -106,7 +103,6 @@ const struct au1xmmc_platform_data au1xmmc_platdata[2] = {
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.cd_setup = NULL, /* use poll-timer in driver */
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.led = &pb1200mmc_led,
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},
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#endif
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};
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static struct resource ide_resources[] = {
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@@ -174,7 +170,6 @@ static int __init board_register_devices(void)
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{
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int swapped;
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#ifdef CONFIG_MIPS_PB1200
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db1x_register_pcmcia_socket(PCMCIA_ATTR_PSEUDO_PHYS,
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PCMCIA_ATTR_PSEUDO_PHYS + 0x00040000 - 1,
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PCMCIA_MEM_PSEUDO_PHYS,
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@@ -198,38 +193,9 @@ static int __init board_register_devices(void)
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/*PB1200_PC1_STSCHG_INT*/0,
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PB1200_PC1_EJECT_INT,
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1);
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#else
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db1x_register_pcmcia_socket(PCMCIA_ATTR_PSEUDO_PHYS,
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PCMCIA_ATTR_PSEUDO_PHYS + 0x00040000 - 1,
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PCMCIA_MEM_PSEUDO_PHYS,
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PCMCIA_MEM_PSEUDO_PHYS + 0x00040000 - 1,
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PCMCIA_IO_PSEUDO_PHYS,
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PCMCIA_IO_PSEUDO_PHYS + 0x00001000 - 1,
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DB1200_PC0_INT,
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DB1200_PC0_INSERT_INT,
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/*DB1200_PC0_STSCHG_INT*/0,
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DB1200_PC0_EJECT_INT,
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0);
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db1x_register_pcmcia_socket(PCMCIA_ATTR_PSEUDO_PHYS + 0x00400000,
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PCMCIA_ATTR_PSEUDO_PHYS + 0x00440000 - 1,
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PCMCIA_MEM_PSEUDO_PHYS + 0x00400000,
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PCMCIA_MEM_PSEUDO_PHYS + 0x00440000 - 1,
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PCMCIA_IO_PSEUDO_PHYS + 0x00400000,
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PCMCIA_IO_PSEUDO_PHYS + 0x00401000 - 1,
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DB1200_PC1_INT,
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DB1200_PC1_INSERT_INT,
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/*DB1200_PC1_STSCHG_INT*/0,
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DB1200_PC1_EJECT_INT,
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1);
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#endif
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swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT;
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#ifdef CONFIG_MIPS_PB1200
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db1x_register_norflash(128 * 1024 * 1024, 2, swapped);
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#else
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db1x_register_norflash(64 * 1024 * 1024, 2, swapped);
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#endif
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return platform_add_devices(board_platform_devices,
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ARRAY_SIZE(board_platform_devices));
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@@ -28,24 +28,6 @@
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#include <asm/mach-au1x00/au1000.h>
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#include <asm/mach-au1x00/au1xxx_psc.h>
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#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
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#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
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#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX
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#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX
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/*
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* SPI and SMB are muxed on the DBAu1200 board.
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* Refer to board documentation.
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*/
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#define SPI_PSC_BASE PSC0_BASE_ADDR
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#define SMBUS_PSC_BASE PSC0_BASE_ADDR
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/*
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* AC'97 and I2S are muxed on the DBAu1200 board.
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* Refer to board documentation.
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*/
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#define AC97_PSC_BASE PSC1_BASE_ADDR
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#define I2S_PSC_BASE PSC1_BASE_ADDR
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/* Bit positions for the different interrupt sources */
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#define BCSR_INT_IDE 0x0001
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#define BCSR_INT_ETH 0x0002
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@@ -62,17 +44,15 @@
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#define BCSR_INT_SD0INSERT 0x1000
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#define BCSR_INT_SD0EJECT 0x2000
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#define SMC91C111_PHYS_ADDR 0x19000300
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#define SMC91C111_INT DB1200_ETH_INT
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#define IDE_PHYS_ADDR 0x18800000
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#define IDE_REG_SHIFT 5
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#define IDE_PHYS_LEN (16 << IDE_REG_SHIFT)
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#define IDE_INT DB1200_IDE_INT
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#define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1
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#define IDE_RQSIZE 128
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#define NAND_PHYS_ADDR 0x20000000
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#define DB1200_IDE_PHYS_ADDR IDE_PHYS_ADDR
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#define DB1200_IDE_PHYS_LEN (16 << IDE_REG_SHIFT)
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#define DB1200_ETH_PHYS_ADDR 0x19000300
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#define DB1200_NAND_PHYS_ADDR 0x20000000
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/*
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* External Interrupts for DBAu1200 as of 8/6/2004.
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@@ -82,7 +62,7 @@
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* Example: IDE bis pos is = 64 - 64
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* ETH bit pos is = 65 - 64
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*/
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enum external_pb1200_ints {
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enum external_db1200_ints {
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DB1200_INT_BEGIN = AU1000_MAX_INTR + 1,
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DB1200_IDE_INT = DB1200_INT_BEGIN,
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@@ -103,7 +83,4 @@ enum external_pb1200_ints {
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DB1200_INT_END = DB1200_INT_BEGIN + 15,
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};
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/* NAND chip select */
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#define NAND_CS 1
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#endif /* __ASM_DB1200_H */
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