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iommu/riscv: Add RISC-V IOMMU platform device driver
Introduce platform device driver for implementation of RISC-V IOMMU architected hardware. Hardware interface definition located in file iommu-bits.h is based on ratified RISC-V IOMMU Architecture Specification version 1.0.0. This patch implements platform device initialization, early check and configuration of the IOMMU interfaces and enables global pass-through address translation mode (iommu_mode == BARE), without registering hardware instance in the IOMMU subsystem. Link: https://github.com/riscv-non-isa/riscv-iommu Co-developed-by: Nick Kossifidis <mick@ics.forth.gr> Signed-off-by: Nick Kossifidis <mick@ics.forth.gr> Co-developed-by: Sebastien Boeuf <seb@rivosinc.com> Signed-off-by: Sebastien Boeuf <seb@rivosinc.com> Reviewed-by: Lu Baolu <baolu.lu@linux.intel.com> Signed-off-by: Tomasz Jeznach <tjeznach@rivosinc.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Link: https://lore.kernel.org/r/2f2e4530c0ee4a81385efa90f1da932f5179f3fb.1729059707.git.tjeznach@rivosinc.com Signed-off-by: Joerg Roedel <jroedel@suse.de>
This commit is contained in:
Tomasz Jeznach
committed by
Joerg Roedel
Joerg Roedel
parent
14d050cd45
commit
5c0ebbd3c6
@@ -19895,7 +19895,9 @@ M: Tomasz Jeznach <tjeznach@rivosinc.com>
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L: iommu@lists.linux.dev
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L: linux-riscv@lists.infradead.org
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S: Maintained
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T: git git://git.kernel.org/pub/scm/linux/kernel/git/iommu/linux.git
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F: Documentation/devicetree/bindings/iommu/riscv,iommu.yaml
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F: drivers/iommu/riscv/
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RISC-V MICROCHIP FPGA SUPPORT
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M: Conor Dooley <conor.dooley@microchip.com>
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@@ -195,6 +195,7 @@ config MSM_IOMMU
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source "drivers/iommu/amd/Kconfig"
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source "drivers/iommu/intel/Kconfig"
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source "drivers/iommu/iommufd/Kconfig"
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source "drivers/iommu/riscv/Kconfig"
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config IRQ_REMAP
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bool "Support for Interrupt Remapping"
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@@ -1,5 +1,5 @@
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# SPDX-License-Identifier: GPL-2.0
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obj-y += amd/ intel/ arm/ iommufd/
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obj-y += amd/ intel/ arm/ iommufd/ riscv/
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obj-$(CONFIG_IOMMU_API) += iommu.o
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obj-$(CONFIG_IOMMU_API) += iommu-traces.o
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obj-$(CONFIG_IOMMU_API) += iommu-sysfs.o
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@@ -0,0 +1,15 @@
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# SPDX-License-Identifier: GPL-2.0-only
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# RISC-V IOMMU support
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config RISCV_IOMMU
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bool "RISC-V IOMMU Support"
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depends on RISCV && 64BIT
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default y
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select IOMMU_API
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help
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Support for implementations of the RISC-V IOMMU architecture that
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complements the RISC-V MMU capabilities, providing similar address
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translation and protection functions for accesses from I/O devices.
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Say Y here if your SoC includes an IOMMU device implementing
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the RISC-V IOMMU architecture.
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@@ -0,0 +1,2 @@
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# SPDX-License-Identifier: GPL-2.0-only
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obj-$(CONFIG_RISCV_IOMMU) += iommu.o iommu-platform.o
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,92 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* RISC-V IOMMU as a platform device
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*
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* Copyright © 2023 FORTH-ICS/CARV
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* Copyright © 2023-2024 Rivos Inc.
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*
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* Authors
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* Nick Kossifidis <mick@ics.forth.gr>
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* Tomasz Jeznach <tjeznach@rivosinc.com>
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*/
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#include <linux/kernel.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include "iommu-bits.h"
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#include "iommu.h"
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static int riscv_iommu_platform_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct riscv_iommu_device *iommu = NULL;
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struct resource *res = NULL;
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int vec;
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iommu = devm_kzalloc(dev, sizeof(*iommu), GFP_KERNEL);
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if (!iommu)
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return -ENOMEM;
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iommu->dev = dev;
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iommu->reg = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
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if (IS_ERR(iommu->reg))
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return dev_err_probe(dev, PTR_ERR(iommu->reg),
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"could not map register region\n");
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dev_set_drvdata(dev, iommu);
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/* Check device reported capabilities / features. */
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iommu->caps = riscv_iommu_readq(iommu, RISCV_IOMMU_REG_CAPABILITIES);
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iommu->fctl = riscv_iommu_readl(iommu, RISCV_IOMMU_REG_FCTL);
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/* For now we only support WSI */
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switch (FIELD_GET(RISCV_IOMMU_CAPABILITIES_IGS, iommu->caps)) {
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case RISCV_IOMMU_CAPABILITIES_IGS_WSI:
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case RISCV_IOMMU_CAPABILITIES_IGS_BOTH:
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break;
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default:
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return dev_err_probe(dev, -ENODEV,
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"unable to use wire-signaled interrupts\n");
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}
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iommu->irqs_count = platform_irq_count(pdev);
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if (iommu->irqs_count <= 0)
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return dev_err_probe(dev, -ENODEV,
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"no IRQ resources provided\n");
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if (iommu->irqs_count > RISCV_IOMMU_INTR_COUNT)
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iommu->irqs_count = RISCV_IOMMU_INTR_COUNT;
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for (vec = 0; vec < iommu->irqs_count; vec++)
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iommu->irqs[vec] = platform_get_irq(pdev, vec);
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/* Enable wire-signaled interrupts, fctl.WSI */
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if (!(iommu->fctl & RISCV_IOMMU_FCTL_WSI)) {
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iommu->fctl |= RISCV_IOMMU_FCTL_WSI;
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riscv_iommu_writel(iommu, RISCV_IOMMU_REG_FCTL, iommu->fctl);
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}
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return riscv_iommu_init(iommu);
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};
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static void riscv_iommu_platform_remove(struct platform_device *pdev)
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{
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riscv_iommu_remove(dev_get_drvdata(&pdev->dev));
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};
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static const struct of_device_id riscv_iommu_of_match[] = {
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{.compatible = "riscv,iommu",},
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{},
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};
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static struct platform_driver riscv_iommu_platform_driver = {
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.probe = riscv_iommu_platform_probe,
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.remove_new = riscv_iommu_platform_remove,
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.driver = {
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.name = "riscv,iommu",
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.of_match_table = riscv_iommu_of_match,
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.suppress_bind_attrs = true,
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},
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};
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builtin_platform_driver(riscv_iommu_platform_driver);
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@@ -0,0 +1,103 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* IOMMU API for RISC-V IOMMU implementations.
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*
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* Copyright © 2022-2024 Rivos Inc.
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* Copyright © 2023 FORTH-ICS/CARV
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*
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* Authors
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* Tomasz Jeznach <tjeznach@rivosinc.com>
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* Nick Kossifidis <mick@ics.forth.gr>
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*/
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#define pr_fmt(fmt) "riscv-iommu: " fmt
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#include <linux/compiler.h>
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#include <linux/crash_dump.h>
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#include <linux/init.h>
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#include <linux/iommu.h>
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#include <linux/kernel.h>
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#include "iommu-bits.h"
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#include "iommu.h"
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/* Timeouts in [us] */
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#define RISCV_IOMMU_DDTP_TIMEOUT 50000
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/*
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* This is best effort IOMMU translation shutdown flow.
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* Disable IOMMU without waiting for hardware response.
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*/
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static void riscv_iommu_disable(struct riscv_iommu_device *iommu)
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{
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riscv_iommu_writeq(iommu, RISCV_IOMMU_REG_DDTP, 0);
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riscv_iommu_writel(iommu, RISCV_IOMMU_REG_CQCSR, 0);
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riscv_iommu_writel(iommu, RISCV_IOMMU_REG_FQCSR, 0);
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riscv_iommu_writel(iommu, RISCV_IOMMU_REG_PQCSR, 0);
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}
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static int riscv_iommu_init_check(struct riscv_iommu_device *iommu)
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{
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u64 ddtp;
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/*
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* Make sure the IOMMU is switched off or in pass-through mode during
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* regular boot flow and disable translation when we boot into a kexec
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* kernel and the previous kernel left them enabled.
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*/
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ddtp = riscv_iommu_readq(iommu, RISCV_IOMMU_REG_DDTP);
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if (ddtp & RISCV_IOMMU_DDTP_BUSY)
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return -EBUSY;
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if (FIELD_GET(RISCV_IOMMU_DDTP_IOMMU_MODE, ddtp) >
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RISCV_IOMMU_DDTP_IOMMU_MODE_BARE) {
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if (!is_kdump_kernel())
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return -EBUSY;
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riscv_iommu_disable(iommu);
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}
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/* Configure accesses to in-memory data structures for CPU-native byte order. */
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if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN) !=
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!!(iommu->fctl & RISCV_IOMMU_FCTL_BE)) {
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if (!(iommu->caps & RISCV_IOMMU_CAPABILITIES_END))
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return -EINVAL;
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riscv_iommu_writel(iommu, RISCV_IOMMU_REG_FCTL,
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iommu->fctl ^ RISCV_IOMMU_FCTL_BE);
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iommu->fctl = riscv_iommu_readl(iommu, RISCV_IOMMU_REG_FCTL);
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if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN) !=
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!!(iommu->fctl & RISCV_IOMMU_FCTL_BE))
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return -EINVAL;
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}
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return 0;
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}
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void riscv_iommu_remove(struct riscv_iommu_device *iommu)
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{
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iommu_device_sysfs_remove(&iommu->iommu);
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}
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int riscv_iommu_init(struct riscv_iommu_device *iommu)
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{
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int rc;
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rc = riscv_iommu_init_check(iommu);
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if (rc)
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return dev_err_probe(iommu->dev, rc, "unexpected device state\n");
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/*
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* Placeholder for a complete IOMMU device initialization. For now,
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* only bare minimum: enable global identity mapping mode and register sysfs.
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*/
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riscv_iommu_writeq(iommu, RISCV_IOMMU_REG_DDTP,
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FIELD_PREP(RISCV_IOMMU_DDTP_IOMMU_MODE,
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RISCV_IOMMU_DDTP_IOMMU_MODE_BARE));
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rc = iommu_device_sysfs_add(&iommu->iommu, NULL, NULL, "riscv-iommu@%s",
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dev_name(iommu->dev));
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if (rc)
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return dev_err_probe(iommu->dev, rc,
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"cannot register sysfs interface\n");
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return 0;
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}
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@@ -0,0 +1,62 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright © 2022-2024 Rivos Inc.
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* Copyright © 2023 FORTH-ICS/CARV
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*
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* Authors
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* Tomasz Jeznach <tjeznach@rivosinc.com>
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* Nick Kossifidis <mick@ics.forth.gr>
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*/
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#ifndef _RISCV_IOMMU_H_
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#define _RISCV_IOMMU_H_
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#include <linux/iommu.h>
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#include <linux/types.h>
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#include <linux/iopoll.h>
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#include "iommu-bits.h"
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struct riscv_iommu_device {
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/* iommu core interface */
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struct iommu_device iommu;
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/* iommu hardware */
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struct device *dev;
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/* hardware control register space */
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void __iomem *reg;
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/* supported and enabled hardware capabilities */
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u64 caps;
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u32 fctl;
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/* available interrupt numbers, MSI or WSI */
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unsigned int irqs[RISCV_IOMMU_INTR_COUNT];
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unsigned int irqs_count;
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};
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int riscv_iommu_init(struct riscv_iommu_device *iommu);
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void riscv_iommu_remove(struct riscv_iommu_device *iommu);
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#define riscv_iommu_readl(iommu, addr) \
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readl_relaxed((iommu)->reg + (addr))
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#define riscv_iommu_readq(iommu, addr) \
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readq_relaxed((iommu)->reg + (addr))
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#define riscv_iommu_writel(iommu, addr, val) \
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writel_relaxed((val), (iommu)->reg + (addr))
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#define riscv_iommu_writeq(iommu, addr, val) \
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writeq_relaxed((val), (iommu)->reg + (addr))
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#define riscv_iommu_readq_timeout(iommu, addr, val, cond, delay_us, timeout_us) \
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readx_poll_timeout(readq_relaxed, (iommu)->reg + (addr), val, cond, \
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delay_us, timeout_us)
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#define riscv_iommu_readl_timeout(iommu, addr, val, cond, delay_us, timeout_us) \
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readx_poll_timeout(readl_relaxed, (iommu)->reg + (addr), val, cond, \
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delay_us, timeout_us)
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#endif
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