mirror of
https://github.com/linux-msm/laptops-kernel.git
synced 2026-08-13 14:19:53 -07:00
Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
Two trivial overlapping changes conflicts in MPLS and mlx5. Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
@@ -7,7 +7,7 @@ have dual GMAC each represented by a child node..
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* Ethernet controller node
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Required properties:
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- compatible: Should be "mediatek,mt7623-eth"
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- compatible: Should be "mediatek,mt2701-eth"
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- reg: Address and length of the register set for the device
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- interrupts: Should contain the three frame engines interrupts in numeric
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order. These are fe_int0, fe_int1 and fe_int2.
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@@ -19,8 +19,9 @@ Optional Properties:
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specifications. If neither of these are specified, the default is to
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assume clause 22.
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If the phy's identifier is known then the list may contain an entry
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of the form: "ethernet-phy-idAAAA.BBBB" where
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If the PHY reports an incorrect ID (or none at all) then the
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"compatible" list may contain an entry with the correct PHY ID in the
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form: "ethernet-phy-idAAAA.BBBB" where
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AAAA - The value of the 16 bit Phy Identifier 1 register as
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4 hex digits. This is the chip vendor OUI bits 3:18
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BBBB - The value of the 16 bit Phy Identifier 2 register as
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@@ -1,17 +1,23 @@
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Renesas MSIOF spi controller
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Required properties:
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- compatible : "renesas,msiof-<soctype>" for SoCs,
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"renesas,sh-msiof" for SuperH, or
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"renesas,sh-mobile-msiof" for SH Mobile series.
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Examples with soctypes are:
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"renesas,msiof-r8a7790" (R-Car H2)
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- compatible : "renesas,msiof-r8a7790" (R-Car H2)
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"renesas,msiof-r8a7791" (R-Car M2-W)
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"renesas,msiof-r8a7792" (R-Car V2H)
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"renesas,msiof-r8a7793" (R-Car M2-N)
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"renesas,msiof-r8a7794" (R-Car E2)
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"renesas,msiof-r8a7796" (R-Car M3-W)
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"renesas,msiof-sh73a0" (SH-Mobile AG5)
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"renesas,sh-mobile-msiof" (generic SH-Mobile compatibile device)
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"renesas,rcar-gen2-msiof" (generic R-Car Gen2 compatible device)
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"renesas,rcar-gen3-msiof" (generic R-Car Gen3 compatible device)
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"renesas,sh-msiof" (deprecated)
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When compatible with the generic version, nodes
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must list the SoC-specific version corresponding
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to the platform first followed by the generic
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version.
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- reg : A list of offsets and lengths of the register sets for
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the device.
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If only one register set is present, it is to be used
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@@ -61,7 +67,8 @@ Documentation/devicetree/bindings/pinctrl/renesas,*.
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Example:
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msiof0: spi@e6e20000 {
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compatible = "renesas,msiof-r8a7791";
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compatible = "renesas,msiof-r8a7791",
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"renesas,rcar-gen2-msiof";
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reg = <0 0xe6e20000 0 0x0064>;
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interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
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@@ -212,10 +212,11 @@ asynchronous manner and the value may not be very precise. To see a precise
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snapshot of a moment, you can see /proc/<pid>/smaps file and scan page table.
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It's slow but very precise.
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Table 1-2: Contents of the status files (as of 4.1)
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Table 1-2: Contents of the status files (as of 4.8)
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..............................................................................
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Field Content
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Name filename of the executable
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Umask file mode creation mask
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State state (R is running, S is sleeping, D is sleeping
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in an uninterruptible wait, Z is zombie,
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T is traced or stopped)
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@@ -226,7 +227,6 @@ Table 1-2: Contents of the status files (as of 4.1)
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TracerPid PID of process tracing this process (0 if not)
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Uid Real, effective, saved set, and file system UIDs
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Gid Real, effective, saved set, and file system GIDs
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Umask file mode creation mask
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FDSize number of file descriptor slots currently allocated
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Groups supplementary group list
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NStgid descendant namespace thread group ID hierarchy
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@@ -236,6 +236,7 @@ Table 1-2: Contents of the status files (as of 4.1)
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VmPeak peak virtual memory size
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VmSize total program size
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VmLck locked memory size
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VmPin pinned memory size
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VmHWM peak resident set size ("high water mark")
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VmRSS size of memory portions. It contains the three
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following parts (VmRSS = RssAnon + RssFile + RssShmem)
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@@ -35,9 +35,7 @@ only one way to cause the system to go into the Suspend-To-RAM state (write
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The default suspend mode (ie. the one to be used without writing anything into
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/sys/power/mem_sleep) is either "deep" (if Suspend-To-RAM is supported) or
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"s2idle", but it can be overridden by the value of the "mem_sleep_default"
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parameter in the kernel command line. On some ACPI-based systems, depending on
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the information in the FADT, the default may be "s2idle" even if Suspend-To-RAM
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is supported.
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parameter in the kernel command line.
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The properties of all of the sleep states are described below.
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+27
-7
@@ -976,6 +976,7 @@ M: Russell King <linux@armlinux.org.uk>
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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W: http://www.armlinux.org.uk/
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S: Maintained
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T: git git://git.armlinux.org.uk/~rmk/linux-arm.git
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F: arch/arm/
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ARM SUB-ARCHITECTURES
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@@ -1153,6 +1154,7 @@ ARM/CLKDEV SUPPORT
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M: Russell King <linux@armlinux.org.uk>
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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S: Maintained
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T: git git://git.armlinux.org.uk/~rmk/linux-arm.git clkdev
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F: arch/arm/include/asm/clkdev.h
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F: drivers/clk/clkdev.c
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@@ -1688,6 +1690,7 @@ M: Krzysztof Kozlowski <krzk@kernel.org>
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R: Javier Martinez Canillas <javier@osg.samsung.com>
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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L: linux-samsung-soc@vger.kernel.org (moderated for non-subscribers)
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Q: https://patchwork.kernel.org/project/linux-samsung-soc/list/
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S: Maintained
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F: arch/arm/boot/dts/s3c*
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F: arch/arm/boot/dts/s5p*
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@@ -3570,7 +3573,7 @@ F: drivers/infiniband/hw/cxgb3/
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F: include/uapi/rdma/cxgb3-abi.h
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CXGB4 ETHERNET DRIVER (CXGB4)
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M: Hariprasad S <hariprasad@chelsio.com>
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M: Ganesh Goudar <ganeshgr@chelsio.com>
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L: netdev@vger.kernel.org
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W: http://www.chelsio.com
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S: Supported
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@@ -4103,12 +4106,18 @@ F: drivers/gpu/drm/bridge/
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DRM DRIVER FOR BOCHS VIRTUAL GPU
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M: Gerd Hoffmann <kraxel@redhat.com>
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S: Odd Fixes
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L: virtualization@lists.linux-foundation.org
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T: git git://git.kraxel.org/linux drm-qemu
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S: Maintained
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F: drivers/gpu/drm/bochs/
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DRM DRIVER FOR QEMU'S CIRRUS DEVICE
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M: Dave Airlie <airlied@redhat.com>
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S: Odd Fixes
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M: Gerd Hoffmann <kraxel@redhat.com>
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L: virtualization@lists.linux-foundation.org
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T: git git://git.kraxel.org/linux drm-qemu
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S: Obsolete
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W: https://www.kraxel.org/blog/2014/10/qemu-using-cirrus-considered-harmful/
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F: drivers/gpu/drm/cirrus/
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RADEON and AMDGPU DRM DRIVERS
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@@ -4150,7 +4159,7 @@ F: Documentation/gpu/i915.rst
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INTEL GVT-g DRIVERS (Intel GPU Virtualization)
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M: Zhenyu Wang <zhenyuw@linux.intel.com>
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M: Zhi Wang <zhi.a.wang@intel.com>
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L: igvt-g-dev@lists.01.org
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L: intel-gvt-dev@lists.freedesktop.org
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L: intel-gfx@lists.freedesktop.org
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W: https://01.org/igvt-g
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T: git https://github.com/01org/gvt-linux.git
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@@ -4301,7 +4310,10 @@ F: Documentation/devicetree/bindings/display/renesas,du.txt
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DRM DRIVER FOR QXL VIRTUAL GPU
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M: Dave Airlie <airlied@redhat.com>
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S: Odd Fixes
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M: Gerd Hoffmann <kraxel@redhat.com>
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L: virtualization@lists.linux-foundation.org
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T: git git://git.kraxel.org/linux drm-qemu
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S: Maintained
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F: drivers/gpu/drm/qxl/
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F: include/uapi/drm/qxl_drm.h
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@@ -7703,8 +7715,10 @@ F: drivers/net/dsa/mv88e6xxx/
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F: Documentation/devicetree/bindings/net/dsa/marvell.txt
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MARVELL ARMADA DRM SUPPORT
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M: Russell King <rmk+kernel@armlinux.org.uk>
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M: Russell King <linux@armlinux.org.uk>
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S: Maintained
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T: git git://git.armlinux.org.uk/~rmk/linux-arm.git drm-armada-devel
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T: git git://git.armlinux.org.uk/~rmk/linux-arm.git drm-armada-fixes
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F: drivers/gpu/drm/armada/
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F: include/uapi/drm/armada_drm.h
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F: Documentation/devicetree/bindings/display/armada/
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@@ -8909,8 +8923,10 @@ S: Supported
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F: drivers/nfc/nxp-nci
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NXP TDA998X DRM DRIVER
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M: Russell King <rmk+kernel@armlinux.org.uk>
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M: Russell King <linux@armlinux.org.uk>
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S: Supported
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T: git git://git.armlinux.org.uk/~rmk/linux-arm.git drm-tda998x-devel
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T: git git://git.armlinux.org.uk/~rmk/linux-arm.git drm-tda998x-fixes
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F: drivers/gpu/drm/i2c/tda998x_drv.c
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F: include/drm/i2c/tda998x.h
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@@ -13105,6 +13121,7 @@ M: David Airlie <airlied@linux.ie>
|
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M: Gerd Hoffmann <kraxel@redhat.com>
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L: dri-devel@lists.freedesktop.org
|
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L: virtualization@lists.linux-foundation.org
|
||||
T: git git://git.kraxel.org/linux drm-qemu
|
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S: Maintained
|
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F: drivers/gpu/drm/virtio/
|
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F: include/uapi/linux/virtio_gpu.h
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@@ -13456,6 +13473,7 @@ F: arch/x86/
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X86 PLATFORM DRIVERS
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M: Darren Hart <dvhart@infradead.org>
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M: Andy Shevchenko <andy@infradead.org>
|
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L: platform-driver-x86@vger.kernel.org
|
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T: git git://git.infradead.org/users/dvhart/linux-platform-drivers-x86.git
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S: Maintained
|
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@@ -13627,6 +13645,7 @@ F: drivers/net/hamradio/z8530.h
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ZBUD COMPRESSED PAGE ALLOCATOR
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M: Seth Jennings <sjenning@redhat.com>
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M: Dan Streetman <ddstreet@ieee.org>
|
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L: linux-mm@kvack.org
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S: Maintained
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F: mm/zbud.c
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@@ -13682,6 +13701,7 @@ F: Documentation/vm/zsmalloc.txt
|
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|
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ZSWAP COMPRESSED SWAP CACHING
|
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M: Seth Jennings <sjenning@redhat.com>
|
||||
M: Dan Streetman <ddstreet@ieee.org>
|
||||
L: linux-mm@kvack.org
|
||||
S: Maintained
|
||||
F: mm/zswap.c
|
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|
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@@ -1,8 +1,8 @@
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VERSION = 4
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PATCHLEVEL = 10
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SUBLEVEL = 0
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EXTRAVERSION = -rc4
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NAME = Roaring Lionus
|
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EXTRAVERSION = -rc5
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NAME = Anniversary Edition
|
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|
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# *DOCUMENTATION*
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# To see a list of typical targets execute "make help"
|
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|
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+1
-1
@@ -29,7 +29,7 @@ config ARC
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select HAVE_KPROBES
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select HAVE_KRETPROBES
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select HAVE_MEMBLOCK
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select HAVE_MOD_ARCH_SPECIFIC if ARC_DW2_UNWIND
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select HAVE_MOD_ARCH_SPECIFIC
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select HAVE_OPROFILE
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select HAVE_PERF_EVENTS
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select HANDLE_DOMAIN_IRQ
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|
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@@ -67,7 +67,7 @@ extern unsigned long perip_base, perip_end;
|
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#define ARC_REG_IC_PTAG_HI 0x1F
|
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|
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/* Bit val in IC_CTRL */
|
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#define IC_CTRL_CACHE_DISABLE 0x1
|
||||
#define IC_CTRL_DIS 0x1
|
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|
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/* Data cache related Auxiliary registers */
|
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#define ARC_REG_DC_BCR 0x72 /* Build Config reg */
|
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@@ -80,8 +80,9 @@ extern unsigned long perip_base, perip_end;
|
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#define ARC_REG_DC_PTAG_HI 0x5F
|
||||
|
||||
/* Bit val in DC_CTRL */
|
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#define DC_CTRL_INV_MODE_FLUSH 0x40
|
||||
#define DC_CTRL_FLUSH_STATUS 0x100
|
||||
#define DC_CTRL_DIS 0x001
|
||||
#define DC_CTRL_INV_MODE_FLUSH 0x040
|
||||
#define DC_CTRL_FLUSH_STATUS 0x100
|
||||
|
||||
/*System-level cache (L2 cache) related Auxiliary registers */
|
||||
#define ARC_REG_SLC_CFG 0x901
|
||||
@@ -92,8 +93,8 @@ extern unsigned long perip_base, perip_end;
|
||||
#define ARC_REG_SLC_RGN_END 0x916
|
||||
|
||||
/* Bit val in SLC_CONTROL */
|
||||
#define SLC_CTRL_DIS 0x001
|
||||
#define SLC_CTRL_IM 0x040
|
||||
#define SLC_CTRL_DISABLE 0x001
|
||||
#define SLC_CTRL_BUSY 0x100
|
||||
#define SLC_CTRL_RGN_OP_INV 0x200
|
||||
|
||||
|
||||
@@ -16,6 +16,7 @@
|
||||
;
|
||||
; Now manually save: r12, sp, fp, gp, r25
|
||||
|
||||
PUSH r30
|
||||
PUSH r12
|
||||
|
||||
; Saving pt_regs->sp correctly requires some extra work due to the way
|
||||
@@ -72,6 +73,7 @@
|
||||
POPAX AUX_USER_SP
|
||||
1:
|
||||
POP r12
|
||||
POP r30
|
||||
|
||||
.endm
|
||||
|
||||
|
||||
@@ -14,13 +14,13 @@
|
||||
|
||||
#include <asm-generic/module.h>
|
||||
|
||||
#ifdef CONFIG_ARC_DW2_UNWIND
|
||||
struct mod_arch_specific {
|
||||
#ifdef CONFIG_ARC_DW2_UNWIND
|
||||
void *unw_info;
|
||||
int unw_sec_idx;
|
||||
#endif
|
||||
const char *secstr;
|
||||
};
|
||||
#endif
|
||||
|
||||
#define MODULE_PROC_FAMILY "ARC700"
|
||||
|
||||
|
||||
@@ -84,7 +84,7 @@ struct pt_regs {
|
||||
unsigned long fp;
|
||||
unsigned long sp; /* user/kernel sp depending on where we came from */
|
||||
|
||||
unsigned long r12;
|
||||
unsigned long r12, r30;
|
||||
|
||||
/*------- Below list auto saved by h/w -----------*/
|
||||
unsigned long r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11;
|
||||
|
||||
@@ -31,6 +31,7 @@ extern int root_mountflags, end_mem;
|
||||
|
||||
void setup_processor(void);
|
||||
void __init setup_arch_memory(void);
|
||||
long __init arc_get_mem_sz(void);
|
||||
|
||||
/* Helpers used in arc_*_mumbojumbo routines */
|
||||
#define IS_AVAIL1(v, s) ((v) ? s : "")
|
||||
|
||||
@@ -77,20 +77,20 @@ void arc_init_IRQ(void)
|
||||
|
||||
static void arcv2_irq_mask(struct irq_data *data)
|
||||
{
|
||||
write_aux_reg(AUX_IRQ_SELECT, data->irq);
|
||||
write_aux_reg(AUX_IRQ_SELECT, data->hwirq);
|
||||
write_aux_reg(AUX_IRQ_ENABLE, 0);
|
||||
}
|
||||
|
||||
static void arcv2_irq_unmask(struct irq_data *data)
|
||||
{
|
||||
write_aux_reg(AUX_IRQ_SELECT, data->irq);
|
||||
write_aux_reg(AUX_IRQ_SELECT, data->hwirq);
|
||||
write_aux_reg(AUX_IRQ_ENABLE, 1);
|
||||
}
|
||||
|
||||
void arcv2_irq_enable(struct irq_data *data)
|
||||
{
|
||||
/* set default priority */
|
||||
write_aux_reg(AUX_IRQ_SELECT, data->irq);
|
||||
write_aux_reg(AUX_IRQ_SELECT, data->hwirq);
|
||||
write_aux_reg(AUX_IRQ_PRIORITY, ARCV2_IRQ_DEF_PRIO);
|
||||
|
||||
/*
|
||||
|
||||
@@ -57,7 +57,7 @@ static void arc_irq_mask(struct irq_data *data)
|
||||
unsigned int ienb;
|
||||
|
||||
ienb = read_aux_reg(AUX_IENABLE);
|
||||
ienb &= ~(1 << data->irq);
|
||||
ienb &= ~(1 << data->hwirq);
|
||||
write_aux_reg(AUX_IENABLE, ienb);
|
||||
}
|
||||
|
||||
@@ -66,7 +66,7 @@ static void arc_irq_unmask(struct irq_data *data)
|
||||
unsigned int ienb;
|
||||
|
||||
ienb = read_aux_reg(AUX_IENABLE);
|
||||
ienb |= (1 << data->irq);
|
||||
ienb |= (1 << data->hwirq);
|
||||
write_aux_reg(AUX_IENABLE, ienb);
|
||||
}
|
||||
|
||||
|
||||
@@ -10,6 +10,7 @@
|
||||
|
||||
#include <linux/smp.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/irqchip/chained_irq.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <soc/arc/mcip.h>
|
||||
#include <asm/irqflags-arcv2.h>
|
||||
@@ -221,10 +222,13 @@ static irq_hw_number_t idu_first_hwirq;
|
||||
static void idu_cascade_isr(struct irq_desc *desc)
|
||||
{
|
||||
struct irq_domain *idu_domain = irq_desc_get_handler_data(desc);
|
||||
struct irq_chip *core_chip = irq_desc_get_chip(desc);
|
||||
irq_hw_number_t core_hwirq = irqd_to_hwirq(irq_desc_get_irq_data(desc));
|
||||
irq_hw_number_t idu_hwirq = core_hwirq - idu_first_hwirq;
|
||||
|
||||
chained_irq_enter(core_chip, desc);
|
||||
generic_handle_irq(irq_find_mapping(idu_domain, idu_hwirq));
|
||||
chained_irq_exit(core_chip, desc);
|
||||
}
|
||||
|
||||
static int idu_irq_map(struct irq_domain *d, unsigned int virq, irq_hw_number_t hwirq)
|
||||
|
||||
@@ -32,8 +32,8 @@ int module_frob_arch_sections(Elf_Ehdr *hdr, Elf_Shdr *sechdrs,
|
||||
#ifdef CONFIG_ARC_DW2_UNWIND
|
||||
mod->arch.unw_sec_idx = 0;
|
||||
mod->arch.unw_info = NULL;
|
||||
mod->arch.secstr = secstr;
|
||||
#endif
|
||||
mod->arch.secstr = secstr;
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -113,8 +113,10 @@ int apply_relocate_add(Elf32_Shdr *sechdrs,
|
||||
|
||||
}
|
||||
|
||||
#ifdef CONFIG_ARC_DW2_UNWIND
|
||||
if (strcmp(module->arch.secstr+sechdrs[tgtsec].sh_name, ".eh_frame") == 0)
|
||||
module->arch.unw_sec_idx = tgtsec;
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
|
||||
|
||||
+122
-33
@@ -23,7 +23,7 @@
|
||||
|
||||
static int l2_line_sz;
|
||||
static int ioc_exists;
|
||||
int slc_enable = 1, ioc_enable = 0;
|
||||
int slc_enable = 1, ioc_enable = 1;
|
||||
unsigned long perip_base = ARC_UNCACHED_ADDR_SPACE; /* legacy value for boot */
|
||||
unsigned long perip_end = 0xFFFFFFFF; /* legacy value */
|
||||
|
||||
@@ -271,7 +271,11 @@ void __cache_line_loop_v2(phys_addr_t paddr, unsigned long vaddr,
|
||||
|
||||
/*
|
||||
* For ARC700 MMUv3 I-cache and D-cache flushes
|
||||
* Also reused for HS38 aliasing I-cache configuration
|
||||
* - ARC700 programming model requires paddr and vaddr be passed in seperate
|
||||
* AUX registers (*_IV*L and *_PTAG respectively) irrespective of whether the
|
||||
* caches actually alias or not.
|
||||
* - For HS38, only the aliasing I-cache configuration uses the PTAG reg
|
||||
* (non aliasing I-cache version doesn't; while D-cache can't possibly alias)
|
||||
*/
|
||||
static inline
|
||||
void __cache_line_loop_v3(phys_addr_t paddr, unsigned long vaddr,
|
||||
@@ -458,6 +462,21 @@ static inline void __dc_entire_op(const int op)
|
||||
__after_dc_op(op);
|
||||
}
|
||||
|
||||
static inline void __dc_disable(void)
|
||||
{
|
||||
const int r = ARC_REG_DC_CTRL;
|
||||
|
||||
__dc_entire_op(OP_FLUSH_N_INV);
|
||||
write_aux_reg(r, read_aux_reg(r) | DC_CTRL_DIS);
|
||||
}
|
||||
|
||||
static void __dc_enable(void)
|
||||
{
|
||||
const int r = ARC_REG_DC_CTRL;
|
||||
|
||||
write_aux_reg(r, read_aux_reg(r) & ~DC_CTRL_DIS);
|
||||
}
|
||||
|
||||
/* For kernel mappings cache operation: index is same as paddr */
|
||||
#define __dc_line_op_k(p, sz, op) __dc_line_op(p, p, sz, op)
|
||||
|
||||
@@ -483,6 +502,8 @@ static inline void __dc_line_op(phys_addr_t paddr, unsigned long vaddr,
|
||||
#else
|
||||
|
||||
#define __dc_entire_op(op)
|
||||
#define __dc_disable()
|
||||
#define __dc_enable()
|
||||
#define __dc_line_op(paddr, vaddr, sz, op)
|
||||
#define __dc_line_op_k(paddr, sz, op)
|
||||
|
||||
@@ -597,6 +618,40 @@ noinline void slc_op(phys_addr_t paddr, unsigned long sz, const int op)
|
||||
#endif
|
||||
}
|
||||
|
||||
noinline static void slc_entire_op(const int op)
|
||||
{
|
||||
unsigned int ctrl, r = ARC_REG_SLC_CTRL;
|
||||
|
||||
ctrl = read_aux_reg(r);
|
||||
|
||||
if (!(op & OP_FLUSH)) /* i.e. OP_INV */
|
||||
ctrl &= ~SLC_CTRL_IM; /* clear IM: Disable flush before Inv */
|
||||
else
|
||||
ctrl |= SLC_CTRL_IM;
|
||||
|
||||
write_aux_reg(r, ctrl);
|
||||
|
||||
write_aux_reg(ARC_REG_SLC_INVALIDATE, 1);
|
||||
|
||||
/* Important to wait for flush to complete */
|
||||
while (read_aux_reg(r) & SLC_CTRL_BUSY);
|
||||
}
|
||||
|
||||
static inline void arc_slc_disable(void)
|
||||
{
|
||||
const int r = ARC_REG_SLC_CTRL;
|
||||
|
||||
slc_entire_op(OP_FLUSH_N_INV);
|
||||
write_aux_reg(r, read_aux_reg(r) | SLC_CTRL_DIS);
|
||||
}
|
||||
|
||||
static inline void arc_slc_enable(void)
|
||||
{
|
||||
const int r = ARC_REG_SLC_CTRL;
|
||||
|
||||
write_aux_reg(r, read_aux_reg(r) & ~SLC_CTRL_DIS);
|
||||
}
|
||||
|
||||
/***********************************************************
|
||||
* Exported APIs
|
||||
*/
|
||||
@@ -923,21 +978,54 @@ SYSCALL_DEFINE3(cacheflush, uint32_t, start, uint32_t, sz, uint32_t, flags)
|
||||
return 0;
|
||||
}
|
||||
|
||||
void arc_cache_init(void)
|
||||
/*
|
||||
* IO-Coherency (IOC) setup rules:
|
||||
*
|
||||
* 1. Needs to be at system level, so only once by Master core
|
||||
* Non-Masters need not be accessing caches at that time
|
||||
* - They are either HALT_ON_RESET and kick started much later or
|
||||
* - if run on reset, need to ensure that arc_platform_smp_wait_to_boot()
|
||||
* doesn't perturb caches or coherency unit
|
||||
*
|
||||
* 2. caches (L1 and SLC) need to be purged (flush+inv) before setting up IOC,
|
||||
* otherwise any straggler data might behave strangely post IOC enabling
|
||||
*
|
||||
* 3. All Caches need to be disabled when setting up IOC to elide any in-flight
|
||||
* Coherency transactions
|
||||
*/
|
||||
noinline void __init arc_ioc_setup(void)
|
||||
{
|
||||
unsigned int __maybe_unused cpu = smp_processor_id();
|
||||
char str[256];
|
||||
unsigned int ap_sz;
|
||||
|
||||
printk(arc_cache_mumbojumbo(0, str, sizeof(str)));
|
||||
/* Flush + invalidate + disable L1 dcache */
|
||||
__dc_disable();
|
||||
|
||||
/* Flush + invalidate SLC */
|
||||
if (read_aux_reg(ARC_REG_SLC_BCR))
|
||||
slc_entire_op(OP_FLUSH_N_INV);
|
||||
|
||||
/* IOC Aperture start: TDB: handle non default CONFIG_LINUX_LINK_BASE */
|
||||
write_aux_reg(ARC_REG_IO_COH_AP0_BASE, 0x80000);
|
||||
|
||||
/*
|
||||
* Only master CPU needs to execute rest of function:
|
||||
* - Assume SMP so all cores will have same cache config so
|
||||
* any geomtry checks will be same for all
|
||||
* - IOC setup / dma callbacks only need to be setup once
|
||||
* IOC Aperture size:
|
||||
* decoded as 2 ^ (SIZE + 2) KB: so setting 0x11 implies 512M
|
||||
* TBD: fix for PGU + 1GB of low mem
|
||||
* TBD: fix for PAE
|
||||
*/
|
||||
if (cpu)
|
||||
return;
|
||||
ap_sz = order_base_2(arc_get_mem_sz()/1024) - 2;
|
||||
write_aux_reg(ARC_REG_IO_COH_AP0_SIZE, ap_sz);
|
||||
|
||||
write_aux_reg(ARC_REG_IO_COH_PARTIAL, 1);
|
||||
write_aux_reg(ARC_REG_IO_COH_ENABLE, 1);
|
||||
|
||||
/* Re-enable L1 dcache */
|
||||
__dc_enable();
|
||||
}
|
||||
|
||||
void __init arc_cache_init_master(void)
|
||||
{
|
||||
unsigned int __maybe_unused cpu = smp_processor_id();
|
||||
|
||||
if (IS_ENABLED(CONFIG_ARC_HAS_ICACHE)) {
|
||||
struct cpuinfo_arc_cache *ic = &cpuinfo_arc700[cpu].icache;
|
||||
@@ -985,30 +1073,14 @@ void arc_cache_init(void)
|
||||
}
|
||||
}
|
||||
|
||||
if (is_isa_arcv2() && l2_line_sz && !slc_enable) {
|
||||
/* Note that SLC disable not formally supported till HS 3.0 */
|
||||
if (is_isa_arcv2() && l2_line_sz && !slc_enable)
|
||||
arc_slc_disable();
|
||||
|
||||
/* IM set : flush before invalidate */
|
||||
write_aux_reg(ARC_REG_SLC_CTRL,
|
||||
read_aux_reg(ARC_REG_SLC_CTRL) | SLC_CTRL_IM);
|
||||
|
||||
write_aux_reg(ARC_REG_SLC_INVALIDATE, 1);
|
||||
|
||||
/* Important to wait for flush to complete */
|
||||
while (read_aux_reg(ARC_REG_SLC_CTRL) & SLC_CTRL_BUSY);
|
||||
write_aux_reg(ARC_REG_SLC_CTRL,
|
||||
read_aux_reg(ARC_REG_SLC_CTRL) | SLC_CTRL_DISABLE);
|
||||
}
|
||||
if (is_isa_arcv2() && ioc_enable)
|
||||
arc_ioc_setup();
|
||||
|
||||
if (is_isa_arcv2() && ioc_enable) {
|
||||
/* IO coherency base - 0x8z */
|
||||
write_aux_reg(ARC_REG_IO_COH_AP0_BASE, 0x80000);
|
||||
/* IO coherency aperture size - 512Mb: 0x8z-0xAz */
|
||||
write_aux_reg(ARC_REG_IO_COH_AP0_SIZE, 0x11);
|
||||
/* Enable partial writes */
|
||||
write_aux_reg(ARC_REG_IO_COH_PARTIAL, 1);
|
||||
/* Enable IO coherency */
|
||||
write_aux_reg(ARC_REG_IO_COH_ENABLE, 1);
|
||||
|
||||
__dma_cache_wback_inv = __dma_cache_wback_inv_ioc;
|
||||
__dma_cache_inv = __dma_cache_inv_ioc;
|
||||
__dma_cache_wback = __dma_cache_wback_ioc;
|
||||
@@ -1022,3 +1094,20 @@ void arc_cache_init(void)
|
||||
__dma_cache_wback = __dma_cache_wback_l1;
|
||||
}
|
||||
}
|
||||
|
||||
void __ref arc_cache_init(void)
|
||||
{
|
||||
unsigned int __maybe_unused cpu = smp_processor_id();
|
||||
char str[256];
|
||||
|
||||
printk(arc_cache_mumbojumbo(0, str, sizeof(str)));
|
||||
|
||||
/*
|
||||
* Only master CPU needs to execute rest of function:
|
||||
* - Assume SMP so all cores will have same cache config so
|
||||
* any geomtry checks will be same for all
|
||||
* - IOC setup / dma callbacks only need to be setup once
|
||||
*/
|
||||
if (!cpu)
|
||||
arc_cache_init_master();
|
||||
}
|
||||
|
||||
@@ -40,6 +40,11 @@ struct pglist_data node_data[MAX_NUMNODES] __read_mostly;
|
||||
EXPORT_SYMBOL(node_data);
|
||||
#endif
|
||||
|
||||
long __init arc_get_mem_sz(void)
|
||||
{
|
||||
return low_mem_sz;
|
||||
}
|
||||
|
||||
/* User can over-ride above with "mem=nnn[KkMm]" in cmdline */
|
||||
static int __init setup_mem_sz(char *str)
|
||||
{
|
||||
|
||||
@@ -846,6 +846,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
|
||||
sun8i-a83t-allwinner-h8homlet-v2.dtb \
|
||||
sun8i-a83t-cubietruck-plus.dtb \
|
||||
sun8i-h3-bananapi-m2-plus.dtb \
|
||||
sun8i-h3-nanopi-m1.dtb \
|
||||
sun8i-h3-nanopi-neo.dtb \
|
||||
sun8i-h3-orangepi-2.dtb \
|
||||
sun8i-h3-orangepi-lite.dtb \
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user