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media: chips-media: wave5: Add vpuapi layer
Add the vpuapi layer of the wave5 codec driver. This layer is used to configure the hardware according to the parameters. Signed-off-by: Sebastian Fricke <sebastian.fricke@collabora.com> Signed-off-by: Nicolas Dufresne <nicolas.dufresne@collabora.com> Signed-off-by: Dafna Hirschfeld <dafna.hirschfeld@collabora.com> Signed-off-by: Robert Beckett <bob.beckett@collabora.com> Signed-off-by: Nas Chung <nas.chung@chipsnmedia.com> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
This commit is contained in:
Nas Chung
Hans Verkuil
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// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
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/*
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* Wave5 series multi-standard codec IP - low level access functions
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*
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* Copyright (C) 2021-2023 CHIPS&MEDIA INC
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*/
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#include <linux/bug.h>
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#include "wave5-vdi.h"
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#include "wave5-vpu.h"
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#include "wave5-regdefine.h"
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#include <linux/delay.h>
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static int wave5_vdi_allocate_common_memory(struct device *dev)
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{
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struct vpu_device *vpu_dev = dev_get_drvdata(dev);
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if (!vpu_dev->common_mem.vaddr) {
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int ret;
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vpu_dev->common_mem.size = SIZE_COMMON;
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ret = wave5_vdi_allocate_dma_memory(vpu_dev, &vpu_dev->common_mem);
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if (ret) {
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dev_err(dev, "unable to allocate common buffer\n");
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return ret;
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}
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}
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dev_dbg(dev, "[VDI] common_mem: daddr=%pad size=%zu vaddr=0x%p\n",
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&vpu_dev->common_mem.daddr, vpu_dev->common_mem.size, vpu_dev->common_mem.vaddr);
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return 0;
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}
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int wave5_vdi_init(struct device *dev)
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{
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struct vpu_device *vpu_dev = dev_get_drvdata(dev);
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int ret;
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ret = wave5_vdi_allocate_common_memory(dev);
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if (ret < 0) {
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dev_err(dev, "[VDI] failed to get vpu common buffer from driver\n");
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return ret;
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}
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if (!PRODUCT_CODE_W_SERIES(vpu_dev->product_code)) {
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WARN_ONCE(1, "unsupported product code: 0x%x\n", vpu_dev->product_code);
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return -EOPNOTSUPP;
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}
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/* if BIT processor is not running. */
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if (wave5_vdi_read_register(vpu_dev, W5_VCPU_CUR_PC) == 0) {
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int i;
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for (i = 0; i < 64; i++)
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wave5_vdi_write_register(vpu_dev, (i * 4) + 0x100, 0x0);
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}
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dev_dbg(dev, "[VDI] driver initialized successfully\n");
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return 0;
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}
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int wave5_vdi_release(struct device *dev)
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{
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struct vpu_device *vpu_dev = dev_get_drvdata(dev);
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vpu_dev->vdb_register = NULL;
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wave5_vdi_free_dma_memory(vpu_dev, &vpu_dev->common_mem);
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return 0;
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}
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void wave5_vdi_write_register(struct vpu_device *vpu_dev, u32 addr, u32 data)
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{
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writel(data, vpu_dev->vdb_register + addr);
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}
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unsigned int wave5_vdi_read_register(struct vpu_device *vpu_dev, u32 addr)
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{
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return readl(vpu_dev->vdb_register + addr);
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}
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int wave5_vdi_clear_memory(struct vpu_device *vpu_dev, struct vpu_buf *vb)
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{
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if (!vb || !vb->vaddr) {
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dev_err(vpu_dev->dev, "%s: unable to clear unmapped buffer\n", __func__);
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return -EINVAL;
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}
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memset(vb->vaddr, 0, vb->size);
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return vb->size;
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}
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int wave5_vdi_write_memory(struct vpu_device *vpu_dev, struct vpu_buf *vb, size_t offset,
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u8 *data, size_t len)
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{
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if (!vb || !vb->vaddr) {
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dev_err(vpu_dev->dev, "%s: unable to write to unmapped buffer\n", __func__);
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return -EINVAL;
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}
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if (offset > vb->size || len > vb->size || offset + len > vb->size) {
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dev_err(vpu_dev->dev, "%s: buffer too small\n", __func__);
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return -ENOSPC;
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}
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memcpy(vb->vaddr + offset, data, len);
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return len;
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}
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int wave5_vdi_allocate_dma_memory(struct vpu_device *vpu_dev, struct vpu_buf *vb)
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{
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void *vaddr;
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dma_addr_t daddr;
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if (!vb->size) {
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dev_err(vpu_dev->dev, "%s: requested size==0\n", __func__);
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return -EINVAL;
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}
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vaddr = dma_alloc_coherent(vpu_dev->dev, vb->size, &daddr, GFP_KERNEL);
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if (!vaddr)
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return -ENOMEM;
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vb->vaddr = vaddr;
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vb->daddr = daddr;
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return 0;
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}
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int wave5_vdi_free_dma_memory(struct vpu_device *vpu_dev, struct vpu_buf *vb)
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{
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if (vb->size == 0)
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return -EINVAL;
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if (!vb->vaddr)
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dev_err(vpu_dev->dev, "%s: requested free of unmapped buffer\n", __func__);
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else
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dma_free_coherent(vpu_dev->dev, vb->size, vb->vaddr, vb->daddr);
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memset(vb, 0, sizeof(*vb));
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return 0;
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}
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int wave5_vdi_allocate_array(struct vpu_device *vpu_dev, struct vpu_buf *array, unsigned int count,
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size_t size)
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{
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struct vpu_buf vb_buf;
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int i, ret = 0;
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vb_buf.size = size;
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for (i = 0; i < count; i++) {
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if (array[i].size == size)
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continue;
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if (array[i].size != 0)
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wave5_vdi_free_dma_memory(vpu_dev, &array[i]);
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ret = wave5_vdi_allocate_dma_memory(vpu_dev, &vb_buf);
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if (ret)
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return -ENOMEM;
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array[i] = vb_buf;
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}
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for (i = count; i < MAX_REG_FRAME; i++)
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wave5_vdi_free_dma_memory(vpu_dev, &array[i]);
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return 0;
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}
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void wave5_vdi_allocate_sram(struct vpu_device *vpu_dev)
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{
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struct vpu_buf *vb = &vpu_dev->sram_buf;
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if (!vpu_dev->sram_pool || !vpu_dev->sram_size)
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return;
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if (!vb->vaddr) {
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vb->size = vpu_dev->sram_size;
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vb->vaddr = gen_pool_dma_alloc(vpu_dev->sram_pool, vb->size,
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&vb->daddr);
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if (!vb->vaddr)
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vb->size = 0;
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}
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dev_dbg(vpu_dev->dev, "%s: sram daddr: %pad, size: %zu, vaddr: 0x%p\n",
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__func__, &vb->daddr, vb->size, vb->vaddr);
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}
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void wave5_vdi_free_sram(struct vpu_device *vpu_dev)
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{
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struct vpu_buf *vb = &vpu_dev->sram_buf;
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if (!vb->size || !vb->vaddr)
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return;
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if (vb->vaddr)
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gen_pool_free(vpu_dev->sram_pool, (unsigned long)vb->vaddr,
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vb->size);
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memset(vb, 0, sizeof(*vb));
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}
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@@ -0,0 +1,35 @@
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/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
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/*
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* Wave5 series multi-standard codec IP - low level access functions
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*
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* Copyright (C) 2021-2023 CHIPS&MEDIA INC
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*/
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#ifndef _VDI_H_
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#define _VDI_H_
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#include "wave5-vpuconfig.h"
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#include <linux/string.h>
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#include <linux/slab.h>
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#include <linux/device.h>
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/************************************************************************/
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/* COMMON REGISTERS */
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/************************************************************************/
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#define VPU_PRODUCT_CODE_REGISTER 0x1044
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/* system register write */
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#define vpu_write_reg(VPU_INST, ADDR, DATA) wave5_vdi_write_register(VPU_INST, ADDR, DATA)
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/* system register read */
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#define vpu_read_reg(CORE, ADDR) wave5_vdi_read_register(CORE, ADDR)
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struct vpu_buf {
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size_t size;
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dma_addr_t daddr;
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void *vaddr;
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};
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int wave5_vdi_init(struct device *dev);
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int wave5_vdi_release(struct device *dev); //this function may be called only at system off.
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#endif //#ifndef _VDI_H_
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/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
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/*
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* Wave5 series multi-standard codec IP - product config definitions
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*
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* Copyright (C) 2021-2023 CHIPS&MEDIA INC
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*/
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#ifndef _VPU_CONFIG_H_
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#define _VPU_CONFIG_H_
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#define WAVE517_CODE 0x5170
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#define WAVE537_CODE 0x5370
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#define WAVE511_CODE 0x5110
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#define WAVE521_CODE 0x5210
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#define WAVE521C_CODE 0x521c
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#define WAVE521C_DUAL_CODE 0x521d // wave521 dual core
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#define WAVE521E1_CODE 0x5211
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#define PRODUCT_CODE_W_SERIES(x) ({ \
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int c = x; \
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((c) == WAVE517_CODE || (c) == WAVE537_CODE || \
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(c) == WAVE511_CODE || (c) == WAVE521_CODE || \
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(c) == WAVE521E1_CODE || (c) == WAVE521C_CODE || \
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(c) == WAVE521C_DUAL_CODE); \
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})
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#define WAVE517_WORKBUF_SIZE (2 * 1024 * 1024)
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#define WAVE521ENC_WORKBUF_SIZE (128 * 1024) //HEVC 128K, AVC 40K
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#define WAVE521DEC_WORKBUF_SIZE (1784 * 1024)
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#define MAX_NUM_INSTANCE 32
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#define W5_MIN_ENC_PIC_WIDTH 256
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#define W5_MIN_ENC_PIC_HEIGHT 128
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#define W5_MAX_ENC_PIC_WIDTH 8192
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#define W5_MAX_ENC_PIC_HEIGHT 8192
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// application specific configuration
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#define VPU_ENC_TIMEOUT 60000
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#define VPU_DEC_TIMEOUT 60000
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// for WAVE encoder
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#define USE_SRC_PRP_AXI 0
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#define USE_SRC_PRI_AXI 1
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#define DEFAULT_SRC_AXI USE_SRC_PRP_AXI
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/************************************************************************/
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/* VPU COMMON MEMORY */
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/************************************************************************/
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#define VLC_BUF_NUM (2)
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#define COMMAND_QUEUE_DEPTH (2)
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#define W5_REMAP_INDEX0 0
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#define W5_REMAP_INDEX1 1
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#define W5_REMAP_MAX_SIZE (1024 * 1024)
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#define WAVE5_MAX_CODE_BUF_SIZE (2 * 1024 * 1024)
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#define WAVE5_TEMPBUF_OFFSET WAVE5_MAX_CODE_BUF_SIZE
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#define WAVE5_TEMPBUF_SIZE (1024 * 1024)
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#define SIZE_COMMON (WAVE5_MAX_CODE_BUF_SIZE + WAVE5_TEMPBUF_SIZE)
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//=====4. VPU REPORT MEMORY ======================//
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#define WAVE5_UPPER_PROC_AXI_ID 0x0
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#define WAVE5_PROC_AXI_ID 0x0
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#define WAVE5_PRP_AXI_ID 0x0
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#define WAVE5_FBD_Y_AXI_ID 0x0
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#define WAVE5_FBC_Y_AXI_ID 0x0
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#define WAVE5_FBD_C_AXI_ID 0x0
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#define WAVE5_FBC_C_AXI_ID 0x0
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#define WAVE5_SEC_AXI_ID 0x0
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#define WAVE5_PRI_AXI_ID 0x0
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#endif /* _VPU_CONFIG_H_ */
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@@ -0,0 +1,292 @@
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/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
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/*
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* Wave5 series multi-standard codec IP - error values
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*
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* Copyright (C) 2021-2023 CHIPS&MEDIA INC
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*/
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#ifndef ERROR_CODE_H_INCLUDED
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#define ERROR_CODE_H_INCLUDED
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/*
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* WAVE5
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*/
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/************************************************************************/
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/* WAVE5 COMMON SYSTEM ERROR (FAIL_REASON) */
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/************************************************************************/
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#define WAVE5_SYSERR_QUEUEING_FAIL 0x00000001
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#define WAVE5_SYSERR_ACCESS_VIOLATION_HW 0x00000040
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#define WAVE5_SYSERR_BUS_ERROR 0x00000200
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#define WAVE5_SYSERR_DOUBLE_FAULT 0x00000400
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#define WAVE5_SYSERR_RESULT_NOT_READY 0x00000800
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#define WAVE5_SYSERR_VPU_STILL_RUNNING 0x00001000
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#define WAVE5_SYSERR_UNKNOWN_CMD 0x00002000
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#define WAVE5_SYSERR_UNKNOWN_CODEC_STD 0x00004000
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#define WAVE5_SYSERR_UNKNOWN_QUERY_OPTION 0x00008000
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#define WAVE5_SYSERR_VLC_BUF_FULL 0x00010000
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#define WAVE5_SYSERR_WATCHDOG_TIMEOUT 0x00020000
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#define WAVE5_SYSERR_VCPU_TIMEOUT 0x00080000
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#define WAVE5_SYSERR_TEMP_SEC_BUF_OVERFLOW 0x00200000
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#define WAVE5_SYSERR_NEED_MORE_TASK_BUF 0x00400000
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#define WAVE5_SYSERR_PRESCAN_ERR 0x00800000
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#define WAVE5_SYSERR_ENC_GBIN_OVERCONSUME 0x01000000
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#define WAVE5_SYSERR_ENC_MAX_ZERO_DETECT 0x02000000
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#define WAVE5_SYSERR_ENC_LVL_FIRST_ERROR 0x04000000
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#define WAVE5_SYSERR_ENC_EG_RANGE_OVER 0x08000000
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#define WAVE5_SYSERR_ENC_IRB_FRAME_DROP 0x10000000
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#define WAVE5_SYSERR_INPLACE_V 0x20000000
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#define WAVE5_SYSERR_FATAL_VPU_HANGUP 0xf0000000
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/************************************************************************/
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/* WAVE5 COMMAND QUEUE ERROR (FAIL_REASON) */
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/************************************************************************/
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#define WAVE5_CMDQ_ERR_NOT_QUEABLE_CMD 0x00000001
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#define WAVE5_CMDQ_ERR_SKIP_MODE_ENABLE 0x00000002
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#define WAVE5_CMDQ_ERR_INST_FLUSHING 0x00000003
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#define WAVE5_CMDQ_ERR_INST_INACTIVE 0x00000004
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#define WAVE5_CMDQ_ERR_QUEUE_FAIL 0x00000005
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#define WAVE5_CMDQ_ERR_CMD_BUF_FULL 0x00000006
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/************************************************************************/
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/* WAVE5 ERROR ON DECODER (ERR_INFO) */
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/************************************************************************/
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// HEVC
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#define HEVC_SPSERR_SEQ_PARAMETER_SET_ID 0x00001000
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#define HEVC_SPSERR_CHROMA_FORMAT_IDC 0x00001001
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#define HEVC_SPSERR_PIC_WIDTH_IN_LUMA_SAMPLES 0x00001002
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#define HEVC_SPSERR_PIC_HEIGHT_IN_LUMA_SAMPLES 0x00001003
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#define HEVC_SPSERR_CONF_WIN_LEFT_OFFSET 0x00001004
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#define HEVC_SPSERR_CONF_WIN_RIGHT_OFFSET 0x00001005
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#define HEVC_SPSERR_CONF_WIN_TOP_OFFSET 0x00001006
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#define HEVC_SPSERR_CONF_WIN_BOTTOM_OFFSET 0x00001007
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#define HEVC_SPSERR_BIT_DEPTH_LUMA_MINUS8 0x00001008
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#define HEVC_SPSERR_BIT_DEPTH_CHROMA_MINUS8 0x00001009
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#define HEVC_SPSERR_LOG2_MAX_PIC_ORDER_CNT_LSB_MINUS4 0x0000100A
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#define HEVC_SPSERR_SPS_MAX_DEC_PIC_BUFFERING 0x0000100B
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#define HEVC_SPSERR_SPS_MAX_NUM_REORDER_PICS 0x0000100C
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#define HEVC_SPSERR_SPS_MAX_LATENCY_INCREASE 0x0000100D
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#define HEVC_SPSERR_LOG2_MIN_LUMA_CODING_BLOCK_SIZE_MINUS3 0x0000100E
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#define HEVC_SPSERR_LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE 0x0000100F
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#define HEVC_SPSERR_LOG2_MIN_TRANSFORM_BLOCK_SIZE_MINUS2 0x00001010
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#define HEVC_SPSERR_LOG2_DIFF_MAX_MIN_TRANSFORM_BLOCK_SIZE 0x00001011
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#define HEVC_SPSERR_MAX_TRANSFORM_HIERARCHY_DEPTH_INTER 0x00001012
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#define HEVC_SPSERR_MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA 0x00001013
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#define HEVC_SPSERR_SCALING_LIST 0x00001014
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#define HEVC_SPSERR_LOG2_DIFF_MIN_PCM_LUMA_CODING_BLOCK_SIZE_MINUS3 0x00001015
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#define HEVC_SPSERR_LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE 0x00001016
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#define HEVC_SPSERR_NUM_SHORT_TERM_REF_PIC_SETS 0x00001017
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#define HEVC_SPSERR_NUM_LONG_TERM_REF_PICS_SPS 0x00001018
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#define HEVC_SPSERR_GBU_PARSING_ERROR 0x00001019
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#define HEVC_SPSERR_EXTENSION_FLAG 0x0000101A
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#define HEVC_SPSERR_VUI_ERROR 0x0000101B
|
||||
#define HEVC_SPSERR_ACTIVATE_SPS 0x0000101C
|
||||
#define HEVC_SPSERR_PROFILE_SPACE 0x0000101D
|
||||
#define HEVC_PPSERR_PPS_PIC_PARAMETER_SET_ID 0x00002000
|
||||
#define HEVC_PPSERR_PPS_SEQ_PARAMETER_SET_ID 0x00002001
|
||||
#define HEVC_PPSERR_NUM_REF_IDX_L0_DEFAULT_ACTIVE_MINUS1 0x00002002
|
||||
#define HEVC_PPSERR_NUM_REF_IDX_L1_DEFAULT_ACTIVE_MINUS1 0x00002003
|
||||
#define HEVC_PPSERR_INIT_QP_MINUS26 0x00002004
|
||||
#define HEVC_PPSERR_DIFF_CU_QP_DELTA_DEPTH 0x00002005
|
||||
#define HEVC_PPSERR_PPS_CB_QP_OFFSET 0x00002006
|
||||
#define HEVC_PPSERR_PPS_CR_QP_OFFSET 0x00002007
|
||||
#define HEVC_PPSERR_NUM_TILE_COLUMNS_MINUS1 0x00002008
|
||||
#define HEVC_PPSERR_NUM_TILE_ROWS_MINUS1 0x00002009
|
||||
#define HEVC_PPSERR_COLUMN_WIDTH_MINUS1 0x0000200A
|
||||
#define HEVC_PPSERR_ROW_HEIGHT_MINUS1 0x0000200B
|
||||
#define HEVC_PPSERR_PPS_BETA_OFFSET_DIV2 0x0000200C
|
||||
#define HEVC_PPSERR_PPS_TC_OFFSET_DIV2 0x0000200D
|
||||
#define HEVC_PPSERR_SCALING_LIST 0x0000200E
|
||||
#define HEVC_PPSERR_LOG2_PARALLEL_MERGE_LEVEL_MINUS2 0x0000200F
|
||||
#define HEVC_PPSERR_NUM_TILE_COLUMNS_RANGE_OUT 0x00002010
|
||||
#define HEVC_PPSERR_NUM_TILE_ROWS_RANGE_OUT 0x00002011
|
||||
#define HEVC_PPSERR_MORE_RBSP_DATA_ERROR 0x00002012
|
||||
#define HEVC_PPSERR_PPS_PIC_PARAMETER_SET_ID_RANGE_OUT 0x00002013
|
||||
#define HEVC_PPSERR_PPS_SEQ_PARAMETER_SET_ID_RANGE_OUT 0x00002014
|
||||
#define HEVC_PPSERR_NUM_REF_IDX_L0_DEFAULT_ACTIVE_MINUS1_RANGE_OUT 0x00002015
|
||||
#define HEVC_PPSERR_NUM_REF_IDX_L1_DEFAULT_ACTIVE_MINUS1_RANGE_OUT 0x00002016
|
||||
#define HEVC_PPSERR_PPS_CB_QP_OFFSET_RANGE_OUT 0x00002017
|
||||
#define HEVC_PPSERR_PPS_CR_QP_OFFSET_RANGE_OUT 0x00002018
|
||||
#define HEVC_PPSERR_COLUMN_WIDTH_MINUS1_RANGE_OUT 0x00002019
|
||||
#define HEVC_PPSERR_ROW_HEIGHT_MINUS1_RANGE_OUT 0x00002020
|
||||
#define HEVC_PPSERR_PPS_BETA_OFFSET_DIV2_RANGE_OUT 0x00002021
|
||||
#define HEVC_PPSERR_PPS_TC_OFFSET_DIV2_RANGE_OUT 0x00002022
|
||||
#define HEVC_SHERR_SLICE_PIC_PARAMETER_SET_ID 0x00003000
|
||||
#define HEVC_SHERR_ACTIVATE_PPS 0x00003001
|
||||
#define HEVC_SHERR_ACTIVATE_SPS 0x00003002
|
||||
#define HEVC_SHERR_SLICE_TYPE 0x00003003
|
||||
#define HEVC_SHERR_FIRST_SLICE_IS_DEPENDENT_SLICE 0x00003004
|
||||
#define HEVC_SHERR_SHORT_TERM_REF_PIC_SET_SPS_FLAG 0x00003005
|
||||
#define HEVC_SHERR_SHORT_TERM_REF_PIC_SET 0x00003006
|
||||
#define HEVC_SHERR_SHORT_TERM_REF_PIC_SET_IDX 0x00003007
|
||||
#define HEVC_SHERR_NUM_LONG_TERM_SPS 0x00003008
|
||||
#define HEVC_SHERR_NUM_LONG_TERM_PICS 0x00003009
|
||||
#define HEVC_SHERR_LT_IDX_SPS_IS_OUT_OF_RANGE 0x0000300A
|
||||
#define HEVC_SHERR_DELTA_POC_MSB_CYCLE_LT 0x0000300B
|
||||
#define HEVC_SHERR_NUM_REF_IDX_L0_ACTIVE_MINUS1 0x0000300C
|
||||
#define HEVC_SHERR_NUM_REF_IDX_L1_ACTIVE_MINUS1 0x0000300D
|
||||
#define HEVC_SHERR_COLLOCATED_REF_IDX 0x0000300E
|
||||
#define HEVC_SHERR_PRED_WEIGHT_TABLE 0x0000300F
|
||||
#define HEVC_SHERR_FIVE_MINUS_MAX_NUM_MERGE_CAND 0x00003010
|
||||
#define HEVC_SHERR_SLICE_QP_DELTA 0x00003011
|
||||
#define HEVC_SHERR_SLICE_QP_DELTA_IS_OUT_OF_RANGE 0x00003012
|
||||
#define HEVC_SHERR_SLICE_CB_QP_OFFSET 0x00003013
|
||||
#define HEVC_SHERR_SLICE_CR_QP_OFFSET 0x00003014
|
||||
#define HEVC_SHERR_SLICE_BETA_OFFSET_DIV2 0x00003015
|
||||
#define HEVC_SHERR_SLICE_TC_OFFSET_DIV2 0x00003016
|
||||
#define HEVC_SHERR_NUM_ENTRY_POINT_OFFSETS 0x00003017
|
||||
#define HEVC_SHERR_OFFSET_LEN_MINUS1 0x00003018
|
||||
#define HEVC_SHERR_SLICE_SEGMENT_HEADER_EXTENSION_LENGTH 0x00003019
|
||||
#define HEVC_SHERR_WRONG_POC_IN_STILL_PICTURE_PROFILE 0x0000301A
|
||||
#define HEVC_SHERR_SLICE_TYPE_ERROR_IN_STILL_PICTURE_PROFILE 0x0000301B
|
||||
#define HEVC_SHERR_PPS_ID_NOT_EQUAL_PREV_VALUE 0x0000301C
|
||||
#define HEVC_SPECERR_OVER_PICTURE_WIDTH_SIZE 0x00004000
|
||||
#define HEVC_SPECERR_OVER_PICTURE_HEIGHT_SIZE 0x00004001
|
||||
#define HEVC_SPECERR_OVER_CHROMA_FORMAT 0x00004002
|
||||
#define HEVC_SPECERR_OVER_BIT_DEPTH 0x00004003
|
||||
#define HEVC_SPECERR_OVER_BUFFER_OVER_FLOW 0x00004004
|
||||
#define HEVC_SPECERR_OVER_WRONG_BUFFER_ACCESS 0x00004005
|
||||
#define HEVC_ETCERR_INIT_SEQ_SPS_NOT_FOUND 0x00005000
|
||||
#define HEVC_ETCERR_DEC_PIC_VCL_NOT_FOUND 0x00005001
|
||||
#define HEVC_ETCERR_NO_VALID_SLICE_IN_AU 0x00005002
|
||||
#define HEVC_ETCERR_INPLACE_V 0x0000500F
|
||||
|
||||
// AVC
|
||||
#define AVC_SPSERR_SEQ_PARAMETER_SET_ID 0x00001000
|
||||
#define AVC_SPSERR_CHROMA_FORMAT_IDC 0x00001001
|
||||
#define AVC_SPSERR_PIC_WIDTH_IN_LUMA_SAMPLES 0x00001002
|
||||
#define AVC_SPSERR_PIC_HEIGHT_IN_LUMA_SAMPLES 0x00001003
|
||||
#define AVC_SPSERR_CONF_WIN_LEFT_OFFSET 0x00001004
|
||||
#define AVC_SPSERR_CONF_WIN_RIGHT_OFFSET 0x00001005
|
||||
#define AVC_SPSERR_CONF_WIN_TOP_OFFSET 0x00001006
|
||||
#define AVC_SPSERR_CONF_WIN_BOTTOM_OFFSET 0x00001007
|
||||
#define AVC_SPSERR_BIT_DEPTH_LUMA_MINUS8 0x00001008
|
||||
#define AVC_SPSERR_BIT_DEPTH_CHROMA_MINUS8 0x00001009
|
||||
#define AVC_SPSERR_SPS_MAX_DEC_PIC_BUFFERING 0x0000100B
|
||||
#define AVC_SPSERR_SPS_MAX_NUM_REORDER_PICS 0x0000100C
|
||||
#define AVC_SPSERR_SCALING_LIST 0x00001014
|
||||
#define AVC_SPSERR_GBU_PARSING_ERROR 0x00001019
|
||||
#define AVC_SPSERR_VUI_ERROR 0x0000101B
|
||||
#define AVC_SPSERR_ACTIVATE_SPS 0x0000101C
|
||||
#define AVC_PPSERR_PPS_PIC_PARAMETER_SET_ID 0x00002000
|
||||
#define AVC_PPSERR_PPS_SEQ_PARAMETER_SET_ID 0x00002001
|
||||
#define AVC_PPSERR_NUM_REF_IDX_L0_DEFAULT_ACTIVE_MINUS1 0x00002002
|
||||
#define AVC_PPSERR_NUM_REF_IDX_L1_DEFAULT_ACTIVE_MINUS1 0x00002003
|
||||
#define AVC_PPSERR_INIT_QP_MINUS26 0x00002004
|
||||
#define AVC_PPSERR_PPS_CB_QP_OFFSET 0x00002006
|
||||
#define AVC_PPSERR_PPS_CR_QP_OFFSET 0x00002007
|
||||
#define AVC_PPSERR_SCALING_LIST 0x0000200E
|
||||
#define AVC_PPSERR_MORE_RBSP_DATA_ERROR 0x00002012
|
||||
#define AVC_PPSERR_PPS_PIC_PARAMETER_SET_ID_RANGE_OUT 0x00002013
|
||||
#define AVC_PPSERR_PPS_SEQ_PARAMETER_SET_ID_RANGE_OUT 0x00002014
|
||||
#define AVC_PPSERR_NUM_REF_IDX_L0_DEFAULT_ACTIVE_MINUS1_RANGE_OUT 0x00002015
|
||||
#define AVC_PPSERR_NUM_REF_IDX_L1_DEFAULT_ACTIVE_MINUS1_RANGE_OUT 0x00002016
|
||||
#define AVC_PPSERR_PPS_CB_QP_OFFSET_RANGE_OUT 0x00002017
|
||||
#define AVC_PPSERR_PPS_CR_QP_OFFSET_RANGE_OUT 0x00002018
|
||||
#define AVC_SHERR_SLICE_PIC_PARAMETER_SET_ID 0x00003000
|
||||
#define AVC_SHERR_ACTIVATE_PPS 0x00003001
|
||||
#define AVC_SHERR_ACTIVATE_SPS 0x00003002
|
||||
#define AVC_SHERR_SLICE_TYPE 0x00003003
|
||||
#define AVC_SHERR_FIRST_MB_IN_SLICE 0x00003004
|
||||
#define AVC_SHERR_RPLM 0x00003006
|
||||
#define AVC_SHERR_LT_IDX_SPS_IS_OUT_OF_RANGE 0x0000300A
|
||||
#define AVC_SHERR_NUM_REF_IDX_L0_ACTIVE_MINUS1 0x0000300C
|
||||
#define AVC_SHERR_NUM_REF_IDX_L1_ACTIVE_MINUS1 0x0000300D
|
||||
#define AVC_SHERR_PRED_WEIGHT_TABLE 0x0000300F
|
||||
#define AVC_SHERR_SLICE_QP_DELTA 0x00003011
|
||||
#define AVC_SHERR_SLICE_BETA_OFFSET_DIV2 0x00003015
|
||||
#define AVC_SHERR_SLICE_TC_OFFSET_DIV2 0x00003016
|
||||
#define AVC_SHERR_DISABLE_DEBLOCK_FILTER_IDC 0x00003017
|
||||
#define AVC_SPECERR_OVER_PICTURE_WIDTH_SIZE 0x00004000
|
||||
#define AVC_SPECERR_OVER_PICTURE_HEIGHT_SIZE 0x00004001
|
||||
#define AVC_SPECERR_OVER_CHROMA_FORMAT 0x00004002
|
||||
#define AVC_SPECERR_OVER_BIT_DEPTH 0x00004003
|
||||
#define AVC_SPECERR_OVER_BUFFER_OVER_FLOW 0x00004004
|
||||
#define AVC_SPECERR_OVER_WRONG_BUFFER_ACCESS 0x00004005
|
||||
#define AVC_ETCERR_INIT_SEQ_SPS_NOT_FOUND 0x00005000
|
||||
#define AVC_ETCERR_DEC_PIC_VCL_NOT_FOUND 0x00005001
|
||||
#define AVC_ETCERR_NO_VALID_SLICE_IN_AU 0x00005002
|
||||
#define AVC_ETCERR_ASO 0x00005004
|
||||
#define AVC_ETCERR_FMO 0x00005005
|
||||
#define AVC_ETCERR_INPLACE_V 0x0000500F
|
||||
|
||||
/************************************************************************/
|
||||
/* WAVE5 WARNING ON DECODER (WARN_INFO) */
|
||||
/************************************************************************/
|
||||
// HEVC
|
||||
#define HEVC_SPSWARN_MAX_SUB_LAYERS_MINUS1 0x00000001
|
||||
#define HEVC_SPSWARN_GENERAL_RESERVED_ZERO_44BITS 0x00000002
|
||||
#define HEVC_SPSWARN_RESERVED_ZERO_2BITS 0x00000004
|
||||
#define HEVC_SPSWARN_SUB_LAYER_RESERVED_ZERO_44BITS 0x00000008
|
||||
#define HEVC_SPSWARN_GENERAL_LEVEL_IDC 0x00000010
|
||||
#define HEVC_SPSWARN_SPS_MAX_DEC_PIC_BUFFERING_VALUE_OVER 0x00000020
|
||||
#define HEVC_SPSWARN_RBSP_TRAILING_BITS 0x00000040
|
||||
#define HEVC_SPSWARN_ST_RPS_UE_ERROR 0x00000080
|
||||
#define HEVC_SPSWARN_EXTENSION_FLAG 0x01000000
|
||||
#define HEVC_SPSWARN_REPLACED_WITH_PREV_SPS 0x02000000
|
||||
#define HEVC_PPSWARN_RBSP_TRAILING_BITS 0x00000100
|
||||
#define HEVC_PPSWARN_REPLACED_WITH_PREV_PPS 0x00000200
|
||||
#define HEVC_SHWARN_FIRST_SLICE_SEGMENT_IN_PIC_FLAG 0x00001000
|
||||
#define HEVC_SHWARN_NO_OUTPUT_OF_PRIOR_PICS_FLAG 0x00002000
|
||||
#define HEVC_SHWARN_PIC_OUTPUT_FLAG 0x00004000
|
||||
#define HEVC_SHWARN_DUPLICATED_SLICE_SEGMENT 0x00008000
|
||||
#define HEVC_ETCWARN_INIT_SEQ_VCL_NOT_FOUND 0x00010000
|
||||
#define HEVC_ETCWARN_MISSING_REFERENCE_PICTURE 0x00020000
|
||||
#define HEVC_ETCWARN_WRONG_TEMPORAL_ID 0x00040000
|
||||
#define HEVC_ETCWARN_ERROR_PICTURE_IS_REFERENCED 0x00080000
|
||||
#define HEVC_SPECWARN_OVER_PROFILE 0x00100000
|
||||
#define HEVC_SPECWARN_OVER_LEVEL 0x00200000
|
||||
#define HEVC_PRESWARN_PARSING_ERR 0x04000000
|
||||
#define HEVC_PRESWARN_MVD_OUT_OF_RANGE 0x08000000
|
||||
#define HEVC_PRESWARN_CU_QP_DELTA_VAL_OUT_OF_RANGE 0x09000000
|
||||
#define HEVC_PRESWARN_COEFF_LEVEL_REMAINING_OUT_OF_RANGE 0x0A000000
|
||||
#define HEVC_PRESWARN_PCM_ERR 0x0B000000
|
||||
#define HEVC_PRESWARN_OVERCONSUME 0x0C000000
|
||||
#define HEVC_PRESWARN_END_OF_SUBSET_ONE_BIT_ERR 0x10000000
|
||||
#define HEVC_PRESWARN_END_OF_SLICE_SEGMENT_FLAG 0x20000000
|
||||
|
||||
// AVC
|
||||
#define AVC_SPSWARN_RESERVED_ZERO_2BITS 0x00000004
|
||||
#define AVC_SPSWARN_GENERAL_LEVEL_IDC 0x00000010
|
||||
#define AVC_SPSWARN_RBSP_TRAILING_BITS 0x00000040
|
||||
#define AVC_PPSWARN_RBSP_TRAILING_BITS 0x00000100
|
||||
#define AVC_SHWARN_NO_OUTPUT_OF_PRIOR_PICS_FLAG 0x00002000
|
||||
#define AVC_ETCWARN_INIT_SEQ_VCL_NOT_FOUND 0x00010000
|
||||
#define AVC_ETCWARN_MISSING_REFERENCE_PICTURE 0x00020000
|
||||
#define AVC_ETCWARN_ERROR_PICTURE_IS_REFERENCED 0x00080000
|
||||
#define AVC_SPECWARN_OVER_PROFILE 0x00100000
|
||||
#define AVC_SPECWARN_OVER_LEVEL 0x00200000
|
||||
#define AVC_PRESWARN_MVD_RANGE_OUT 0x00400000
|
||||
#define AVC_PRESWARN_MB_QPD_RANGE_OUT 0x00500000
|
||||
#define AVC_PRESWARN_COEFF_RANGE_OUT 0x00600000
|
||||
#define AVC_PRESWARN_MV_RANGE_OUT 0x00700000
|
||||
#define AVC_PRESWARN_MB_SKIP_RUN_RANGE_OUT 0x00800000
|
||||
#define AVC_PRESWARN_MB_TYPE_RANGE_OUT 0x00900000
|
||||
#define AVC_PRESWARN_SUB_MB_TYPE_RANGE_OUT 0x00A00000
|
||||
#define AVC_PRESWARN_CBP_RANGE_OUT 0x00B00000
|
||||
#define AVC_PRESWARN_INTRA_CHROMA_PRED_MODE_RANGE_OUT 0x00C00000
|
||||
#define AVC_PRESWARN_REF_IDX_RANGE_OUT 0x00D00000
|
||||
#define AVC_PRESWARN_COEFF_TOKEN_RANGE_OUT 0x00E00000
|
||||
#define AVC_PRESWARN_TOTAL_ZERO_RANGE_OUT 0x00F00000
|
||||
#define AVC_PRESWARN_RUN_BEFORE_RANGE_OUT 0x01000000
|
||||
#define AVC_PRESWARN_OVERCONSUME 0x01100000
|
||||
#define AVC_PRESWARN_MISSING_SLICE 0x01200000
|
||||
|
||||
/************************************************************************/
|
||||
/* WAVE5 ERROR ON ENCODER (ERR_INFO) */
|
||||
/************************************************************************/
|
||||
|
||||
/************************************************************************/
|
||||
/* WAVE5 WARNING ON ENCODER (WARN_INFO) */
|
||||
/************************************************************************/
|
||||
#define WAVE5_ETCWARN_FORCED_SPLIT_BY_CU8X8 0x000000001
|
||||
|
||||
/************************************************************************/
|
||||
/* WAVE5 debug info (PRI_REASON) */
|
||||
/************************************************************************/
|
||||
#define WAVE5_DEC_VCORE_VCE_HANGUP 0x0001
|
||||
#define WAVE5_DEC_VCORE_UNDETECTED_SYNTAX_ERR 0x0002
|
||||
#define WAVE5_DEC_VCORE_MIB_BUSY 0x0003
|
||||
#define WAVE5_DEC_VCORE_VLC_BUSY 0x0004
|
||||
|
||||
#endif /* ERROR_CODE_H_INCLUDED */
|
||||
@@ -0,0 +1,114 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
|
||||
/*
|
||||
* Wave5 series multi-standard codec IP - wave5 backend definitions
|
||||
*
|
||||
* Copyright (C) 2021-2023 CHIPS&MEDIA INC
|
||||
*/
|
||||
|
||||
#ifndef __WAVE5_FUNCTION_H__
|
||||
#define __WAVE5_FUNCTION_H__
|
||||
|
||||
#define WAVE5_SUBSAMPLED_ONE_SIZE(_w, _h) (ALIGN((_w) / 4, 16) * ALIGN((_h) / 4, 8))
|
||||
#define WAVE5_SUBSAMPLED_ONE_SIZE_AVC(_w, _h) (ALIGN((_w) / 4, 32) * ALIGN((_h) / 4, 4))
|
||||
|
||||
/*
|
||||
* Bitstream buffer option: Explicit End
|
||||
* When set to 1 the VPU assumes that the bitstream has at least one frame and
|
||||
* will read until the end of the bitstream buffer.
|
||||
* When set to 0 the VPU will not read the last few bytes.
|
||||
* This option can be set anytime but cannot be cleared during processing.
|
||||
* It can be set to force finish decoding even though there is not enough
|
||||
* bitstream data for a full frame.
|
||||
*/
|
||||
#define BSOPTION_ENABLE_EXPLICIT_END BIT(0)
|
||||
#define BSOPTION_HIGHLIGHT_STREAM_END BIT(1)
|
||||
|
||||
/*
|
||||
* Currently the driver only supports hardware with little endian but for source
|
||||
* picture format, the bitstream and the report parameter the hardware works
|
||||
* with the opposite endianness, thus hard-code big endian for the register
|
||||
* writes
|
||||
*/
|
||||
#define PIC_SRC_ENDIANNESS_BIG_ENDIAN 0xf
|
||||
#define BITSTREAM_ENDIANNESS_BIG_ENDIAN 0xf
|
||||
#define REPORT_PARAM_ENDIANNESS_BIG_ENDIAN 0xf
|
||||
|
||||
#define WTL_RIGHT_JUSTIFIED 0
|
||||
#define WTL_LEFT_JUSTIFIED 1
|
||||
#define WTL_PIXEL_8BIT 0
|
||||
#define WTL_PIXEL_16BIT 1
|
||||
#define WTL_PIXEL_32BIT 2
|
||||
|
||||
/* Mirror & rotation modes of the PRP (pre-processing) module */
|
||||
#define NONE_ROTATE 0x0
|
||||
#define ROT_CLOCKWISE_90 0x3
|
||||
#define ROT_CLOCKWISE_180 0x5
|
||||
#define ROT_CLOCKWISE_270 0x7
|
||||
#define MIR_HOR_FLIP 0x11
|
||||
#define MIR_VER_FLIP 0x9
|
||||
#define MIR_HOR_VER_FLIP (MIR_HOR_FLIP | MIR_VER_FLIP)
|
||||
|
||||
bool wave5_vpu_is_init(struct vpu_device *vpu_dev);
|
||||
|
||||
unsigned int wave5_vpu_get_product_id(struct vpu_device *vpu_dev);
|
||||
|
||||
int wave5_vpu_get_version(struct vpu_device *vpu_dev, u32 *revision);
|
||||
|
||||
int wave5_vpu_init(struct device *dev, u8 *fw, size_t size);
|
||||
|
||||
int wave5_vpu_reset(struct device *dev, enum sw_reset_mode reset_mode);
|
||||
|
||||
int wave5_vpu_build_up_dec_param(struct vpu_instance *inst, struct dec_open_param *param);
|
||||
|
||||
int wave5_vpu_dec_set_bitstream_flag(struct vpu_instance *inst, bool eos);
|
||||
|
||||
int wave5_vpu_hw_flush_instance(struct vpu_instance *inst);
|
||||
|
||||
int wave5_vpu_dec_register_framebuffer(struct vpu_instance *inst,
|
||||
struct frame_buffer *fb_arr, enum tiled_map_type map_type,
|
||||
unsigned int count);
|
||||
|
||||
int wave5_vpu_re_init(struct device *dev, u8 *fw, size_t size);
|
||||
|
||||
int wave5_vpu_dec_init_seq(struct vpu_instance *inst);
|
||||
|
||||
int wave5_vpu_dec_get_seq_info(struct vpu_instance *inst, struct dec_initial_info *info);
|
||||
|
||||
int wave5_vpu_decode(struct vpu_instance *inst, u32 *fail_res);
|
||||
|
||||
int wave5_vpu_dec_get_result(struct vpu_instance *inst, struct dec_output_info *result);
|
||||
|
||||
int wave5_vpu_dec_finish_seq(struct vpu_instance *inst, u32 *fail_res);
|
||||
|
||||
int wave5_dec_clr_disp_flag(struct vpu_instance *inst, unsigned int index);
|
||||
|
||||
int wave5_dec_set_disp_flag(struct vpu_instance *inst, unsigned int index);
|
||||
|
||||
int wave5_vpu_clear_interrupt(struct vpu_instance *inst, u32 flags);
|
||||
|
||||
dma_addr_t wave5_dec_get_rd_ptr(struct vpu_instance *inst);
|
||||
|
||||
int wave5_dec_set_rd_ptr(struct vpu_instance *inst, dma_addr_t addr);
|
||||
|
||||
/***< WAVE5 encoder >******/
|
||||
|
||||
int wave5_vpu_build_up_enc_param(struct device *dev, struct vpu_instance *inst,
|
||||
struct enc_open_param *open_param);
|
||||
|
||||
int wave5_vpu_enc_init_seq(struct vpu_instance *inst);
|
||||
|
||||
int wave5_vpu_enc_get_seq_info(struct vpu_instance *inst, struct enc_initial_info *info);
|
||||
|
||||
int wave5_vpu_enc_register_framebuffer(struct device *dev, struct vpu_instance *inst,
|
||||
struct frame_buffer *fb_arr, enum tiled_map_type map_type,
|
||||
unsigned int count);
|
||||
|
||||
int wave5_vpu_encode(struct vpu_instance *inst, struct enc_param *option, u32 *fail_res);
|
||||
|
||||
int wave5_vpu_enc_get_result(struct vpu_instance *inst, struct enc_output_info *result);
|
||||
|
||||
int wave5_vpu_enc_finish_seq(struct vpu_instance *inst, u32 *fail_res);
|
||||
|
||||
int wave5_vpu_enc_check_open_param(struct vpu_instance *inst, struct enc_open_param *open_param);
|
||||
|
||||
#endif /* __WAVE5_FUNCTION_H__ */
|
||||
Reference in New Issue
Block a user